using algebraic addition of the input signals

Industry

CPC
G06F7/5013

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/5013using algebraic addition of the input signals

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Multi-bit full adder based on resistive-switching devices and opera...
- Patent number 9,733,900
- Issue date Aug 15, 2017
- Peking University
- Lifeng Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of pattern recognition for artificial intelligence
- Patent number 8,880,453
- Issue date Nov 4, 2014
- Steven Howard Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast chainable carry look-ahead adder
- Patent number 6,658,446
- Issue date Dec 2, 2003
- Atmel Grenoble S.A.
- Laurent Simony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor and a digital signal processor including adder and m...
- Patent number 6,516,331
- Issue date Feb 4, 2003
- RN2R, L.L.C.
- Valeriu Beiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuit employing logic gates having discrete weighted inputs...
- Patent number 6,502,120
- Issue date Dec 31, 2002
- RN2R, L.L.C.
- Valeriu Beiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder having reduced number of internal layers and method of operat...
- Patent number 6,438,572
- Issue date Aug 20, 2002
- RN2R, L.L.C.
- Valeriu Beiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise tolerant conductance-based logic gate and methods of operatio...
- Patent number 6,430,585
- Issue date Aug 6, 2002
- RN2R, L.L.C.
- Valeriu Beiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analog to digital converter using remainder feedback loop
- Patent number 6,333,709
- Issue date Dec 25, 2001
- Fujitsu Limited
- Yoshihiro Miyamoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
A/D converter with input capacitor, feedback capacitor, and two inv...
- Patent number 6,208,282
- Issue date Mar 27, 2001
- Fujitsu Limited
- Yoshihiro Miyamoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder and multiplier circuits employing logic gates having discrete...
- Patent number 6,205,458
- Issue date Mar 20, 2001
- RN2R, L.L.C.
- Valeriu Beiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuit utilizing capacitive coupling, an AD converter and a...
- Patent number 6,043,675
- Issue date Mar 28, 2000
- Fujitsu Limited
- Yoshihiro Miyamoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangement for realizing logic elements that can be repres...
- Patent number 5,991,789
- Issue date Nov 23, 1999
- Siemens Aktiengesellschaft
- Stefan Prange
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor devices utilizing neuron MOS transistors
- Patent number 5,587,668
- Issue date Dec 24, 1996
- Tadashi Shibata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple resonant tunneling circuits for positive digit range-4 bas...
- Patent number 5,469,163
- Issue date Nov 21, 1995
- Texas Instruments Incorporated
- Albert H. Taddiken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Majority logic circuit
- Patent number 5,281,871
- Issue date Jan 25, 1994
- Fujitsu Limited
- Toshihiko Mori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed arithmetic and logic generator with reduced complexity u...
- Patent number 5,265,044
- Issue date Nov 23, 1993
- Tejinder Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural network implementation of a binary adder
- Patent number 5,016,211
- Issue date May 14, 1991
- Samsung Electronics Co., Ltd.
- Ho-sun Jeong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor functional element
- Patent number 5,003,360
- Issue date Mar 26, 1991
- Fujitsu Limited
- Makoto Okada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder using multi-state logic
- Patent number 4,916,653
- Issue date Apr 10, 1990
- Hitachi, Ltd.
- Toshihiko Shimizu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-function logic gate with one gate delay
- Patent number 4,133,040
- Issue date Jan 2, 1979
- RCA Corporation
- Daniel Hampel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3628000
- Patent number 3,628,000
- Issue date Dec 14, 1971
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3440413
- Patent number 3,440,413
- Issue date Apr 22, 1969
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3420992
- Patent number 3,420,992
- Issue date Jan 7, 1969
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3348033
- Patent number 3,348,033
- Issue date Oct 17, 1967
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3315100
- Patent number 3,315,100
- Issue date Apr 18, 1967
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3280316
- Patent number 3,280,316
- Issue date Oct 18, 1966
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3278755
- Patent number 3,278,755
- Issue date Oct 11, 1966
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3275813
- Patent number 3,275,813
- Issue date Sep 27, 1966
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3253133
- Patent number 3,253,133
- Issue date May 24, 1966
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3248529
- Patent number 3,248,529
- Issue date Apr 26, 1966
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-BIT FULL ADDER BASED ON RESISTIVE-SWITCHING DEVICES AND OPERA...
- Publication number 20160313975
- Publication date Oct 27, 2016
- Peking University
- Lifeng Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Pattern Recognition for Artificial Intelligence
- Publication number 20130054504
- Publication date Feb 28, 2013
- Steven Howard Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A Microprocessor and a digital signal processor including adder and...
- Publication number 20030028575
- Publication date Feb 6, 2003
- RN2R, L.L.C.
- Valeriu Beiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adder and multiplier circuits employing logic gates having discrete...
- Publication number 20030009504
- Publication date Jan 9, 2003
- RN2R, L.L.C.
- Valeriu Beiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adder and multiplier circuits employing logic gates having discrete...
- Publication number 20010001862
- Publication date May 24, 2001
- Valeriu Beiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adder and multiplier circuits employing logic gates having discrete...
- Publication number 20010001860
- Publication date May 24, 2001
- Valeriu Beiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adder and multiplier circuits employing logic gates having discrete...
- Publication number 20010001861
- Publication date May 24, 2001
- Valeriu Beiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic circuit utilizing capacitive coupling, an AD converter and a...
- Publication number 20010000661
- Publication date May 3, 2001
- FUJITSU LIMITED
- Yoshihiro Miyamoto
- G06 - COMPUTING CALCULATING COUNTING

using algebraic addition of the input signals

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Multi-bit full adder based on resistive-switching devices and opera...

Method of pattern recognition for artificial intelligence

Fast chainable carry look-ahead adder

Microprocessor and a digital signal processor including adder and m...

Adder circuit employing logic gates having discrete weighted inputs...

Adder having reduced number of internal layers and method of operat...

Noise tolerant conductance-based logic gate and methods of operatio...

Analog to digital converter using remainder feedback loop

A/D converter with input capacitor, feedback capacitor, and two inv...

Adder and multiplier circuits employing logic gates having discrete...

Logic circuit utilizing capacitive coupling, an AD converter and a...

Circuit arrangement for realizing logic elements that can be repres...

Semiconductor devices utilizing neuron MOS transistors

Multiple resonant tunneling circuits for positive digit range-4 bas...

Majority logic circuit

High speed arithmetic and logic generator with reduced complexity u...

Neural network implementation of a binary adder

Semiconductor functional element

Adder using multi-state logic

Multi-function logic gate with one gate delay

3628000

3440413

3420992

3348033

3315100

3280316

3278755

3275813

3253133

3248529

Patents Applicationslast 30 patents

MULTI-BIT FULL ADDER BASED ON RESISTIVE-SWITCHING DEVICES AND OPERA...

Method of Pattern Recognition for Artificial Intelligence

A Microprocessor and a digital signal processor including adder and...

Adder and multiplier circuits employing logic gates having discrete...

Adder and multiplier circuits employing logic gates having discrete...

Adder and multiplier circuits employing logic gates having discrete...

Adder and multiplier circuits employing logic gates having discrete...

Logic circuit utilizing capacitive coupling, an AD converter and a...