using an AND matrix followed by an OR matrix

Industry

CPC
H03K19/17708

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

HELECTRICITY H03Electronic circuits H03KPULSE TECHNIQUE H03K19/00Logic circuits

Current Industry

H03K19/17708using an AND matrix followed by an OR matrix

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Logic drive based on multichip package using interconnection bridge
- Patent number 12,027,491
- Issue date Jul 2, 2024
- iCometrue Company Ltd.
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FPGA-based design method and device for equally dividing interval
- Patent number 11,923,863
- Issue date Mar 5, 2024
- INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD
- Xiankun Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic array with reliable timing
- Patent number 11,855,633
- Issue date Dec 26, 2023
- STMicroelectronics (Rousset) SAS
- Jean-Francois Link
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for providing multiple power domains to a prog...
- Patent number 11,664,806
- Issue date May 30, 2023
- Gowin Semiconductor Corporation
- Grant Thomas Jennings
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sectional configuration for programmable logic devices
- Patent number 11,652,486
- Issue date May 16, 2023
- QuickLogic Corporation
- Ket Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logic drive based on chip scale package comprising standardized com...
- Patent number 11,616,046
- Issue date Mar 28, 2023
- iCometrue Company Ltd.
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for providing multiple power domains a program...
- Patent number 11,496,135
- Issue date Nov 8, 2022
- Gowin Semiconductor Corporation
- Grant Thomas Jennings
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Detection and mitigation of unstable cells in unclonable cell array
- Patent number 11,411,563
- Issue date Aug 9, 2022
- NVIDIA Corp.
- Sudhir Shrikantha Kudva
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data processing engine array architecture with memory tiles
- Patent number 11,336,287
- Issue date May 17, 2022
- Xilinx, Inc.
- Javier Cabezas Rodriguez
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data processing engine array architecture with memory tiles
- Patent number 11,296,707
- Issue date Apr 5, 2022
- Xilinx, Inc.
- Javier Cabezas Rodriguez
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field-programmable gate array with updatable security schemes
- Patent number 11,264,991
- Issue date Mar 1, 2022
- Andrew Lukefahr
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interface for parallel configuration of programmable devices
- Patent number 11,223,361
- Issue date Jan 11, 2022
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Thermal load balancing of programmable devices
- Patent number 11,012,072
- Issue date May 18, 2021
- Xilinx, Inc.
- John K. Jennings
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logic integrated circuit
- Patent number 10,979,053
- Issue date Apr 13, 2021
- NANOBRIDGE SEMICONDUCTOR, INC.
- Ryusuke Nebashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Logic drive based on multichip package using interconnection bridge
- Patent number 10,937,762
- Issue date Mar 2, 2021
- iCometrue Company Ltd.
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
JTL-based superconducting logic arrays and FPGAS
- Patent number 10,756,738
- Issue date Aug 25, 2020
- Northrop Grumman Systems Corporation
- William Robert Reohr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sum-of-products accelerator array
- Patent number 10,719,296
- Issue date Jul 21, 2020
- Macronix International Co., Ltd.
- Feng-Min Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device, display system, and electronic device
- Patent number 10,686,080
- Issue date Jun 16, 2020
- Semiconductor Energy Laboratory Co., Ltd.
- Takashi Nakagawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuration engine for a programmable circuit
- Patent number 10,666,266
- Issue date May 26, 2020
- Xilinx, Inc.
- Karthy Rajasekharan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable array logic
- Patent number 10,666,262
- Issue date May 26, 2020
- Nuvoton Technology Corporation
- Cheng-Chih Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interface for parallel configuration of programmable devices
- Patent number 10,666,265
- Issue date May 26, 2020
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock synchronization in multi-die field programmable gate array de...
- Patent number 10,530,367
- Issue date Jan 7, 2020
- Intel Corporation
- Chooi Pei Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable operation block array
- Patent number 10,482,209
- Issue date Nov 19, 2019
- HLS Logix LLC
- Jason Daniel Gorski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
JTL-based superconducting logic arrays and FPGAs
- Patent number 10,447,278
- Issue date Oct 15, 2019
- Northrop Grumman Systems Corporation
- William Robert Reohr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic circuit and method for implementing a boolean fu...
- Patent number 10,418,999
- Issue date Sep 17, 2019
- Infineon Technologies AG
- Thomas Kuenemund
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method to proxy networking statistics for FPGA cards
- Patent number 10,409,940
- Issue date Sep 10, 2019
- Dell Products, L.P.
- Johan Rahardjo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Increasing available flip-flop count for placement of a circuit des...
- Patent number 10,387,594
- Issue date Aug 20, 2019
- Xilinx, Inc.
- Chinmaya Dash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Four-input josephson gates
- Patent number 10,389,361
- Issue date Aug 20, 2019
- Northrop Grumman Systems Corporation
- Jack R. Powell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential offset calibration of chopping switches in time-interl...
- Patent number 10,298,248
- Issue date May 21, 2019
- Xilinx, Inc.
- Bruno Miguel Vaz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for editing video and audio clips
- Patent number 10,289,916
- Issue date May 14, 2019
- Shred Video, Inc.
- Michael Allen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOGIC DRIVE BASED ON MULTICHIP PACKAGE USING INTERCONNECTION BRIDGE
- Publication number 20240266322
- Publication date Aug 8, 2024
- iCometrue Company Ltd.
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAMMABLE LOGIC ARRAY WITH RELIABLE TIMING
- Publication number 20230387917
- Publication date Nov 30, 2023
- STMicroelectronics (Rousset) SAS
- Jean-Francois LINK
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SECTIONAL CONFIGURATION FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20230353156
- Publication date Nov 2, 2023
- QuickLogic Corporation
- Ket Chong YAP
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and Apparatus for Providing Multiple Power Domains in A Prog...
- Publication number 20230268926
- Publication date Aug 24, 2023
- Gowin Semiconductor Corporation
- Grant Thomas Jennings
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and Apparatus for Providing Multiple Power Domains to A Prog...
- Publication number 20220393685
- Publication date Dec 8, 2022
- Gowin Semiconductor Corporation
- Grant Thomas Jennings
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CHAINED COMMAND ARCHITECTURE FOR PACKET PROCESSING
- Publication number 20220337249
- Publication date Oct 20, 2022
- Sreedhar Ravipalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
VIRTUAL MEMORY WITH DYNAMIC SEGMENTATION FOR MULTI-TENANT FPGAS
- Publication number 20220327063
- Publication date Oct 13, 2022
- Nokia Solutions and Networks Oy
- Andrea ENRICI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTION AND MITIGATION OF UNSTABLE CELLS IN UNCLONABLE CELL ARRAY
- Publication number 20220271951
- Publication date Aug 25, 2022
- NVIDIA Corp.
- Sudhir Shrikantha Kudva
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR PROVIDING MULTIPLE POWER DOMAINS A PROGRAM...
- Publication number 20210376834
- Publication date Dec 2, 2021
- Gowin Semiconductor Corporation
- Grant Thomas Jennings
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FIELD-PROGRAMMABLE GATE ARRAY WITH UPDATABLE SECURITY SCHEMES
- Publication number 20210159902
- Publication date May 27, 2021
- The Trustees of Indiana University
- Andrew Lukefahr
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOGIC DRIVE BASED ON MULTICHIP PACKAGE USING INTERCONNECTION BRIDGE
- Publication number 20210143124
- Publication date May 13, 2021
- iCometrue Company Ltd.
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Determining Sums Using Logic Circuits
- Publication number 20210099174
- Publication date Apr 1, 2021
- SUPERFASTFPGA LIMITED
- Paul James Metzgen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE FOR PARALLEL CONFIGURATION OF PROGRAMMABLE DEVICES
- Publication number 20200358444
- Publication date Nov 12, 2020
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOGIC INTEGRATED CIRCUIT
- Publication number 20200336145
- Publication date Oct 22, 2020
- NEC Corporation
- Ryusuke NEBASHI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOGIC DRIVE BASED ON CHIP SCALE PACKAGE COMPRISING STANDARDIZED COM...
- Publication number 20200144224
- Publication date May 7, 2020
- iCometrue Company Ltd.
- Mou-Shiung Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOGIC DRIVE BASED ON MULTICHIP PACKAGE USING INTERCONNECTION BRIDGE
- Publication number 20200111734
- Publication date Apr 9, 2020
- iCometrue Company Ltd.
- Mou-Shiung Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE ARRAY LOGIC
- Publication number 20200044655
- Publication date Feb 6, 2020
- Nuvoton Technology Corporation
- Cheng-Chih Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
JTL-BASED SUPERCONDUCTING LOGIC ARRAYS AND FPGAS
- Publication number 20200028512
- Publication date Jan 23, 2020
- Northrop Grumman Systems Corporation
- WILLIAM ROBERT REOHR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FOUR-INPUT JOSEPHSON GATES
- Publication number 20190238137
- Publication date Aug 1, 2019
- Northrop Grumman Systems Corporation
- JACK R. POWELL
- B82 - NANO-TECHNOLOGY
Information Patent Application
SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE
- Publication number 20190229216
- Publication date Jul 25, 2019
- Semiconductor Energy Laboratory Co., Ltd.
- Takashi NAKAGAWA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SUM-OF-PRODUCTS ACCELERATOR ARRAY
- Publication number 20190220249
- Publication date Jul 18, 2019
- Macronix International Co., Ltd.
- Feng-Min LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK SYNCHRONIZATION IN MULTI-DIE FIELD PROGRAMMABLE GATE ARRAY DE...
- Publication number 20190140647
- Publication date May 9, 2019
- Intel Corporation
- Chooi Pei Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REDUCING IDLE POWER CONSUMPTION FROM PROGR...
- Publication number 20190107881
- Publication date Apr 11, 2019
- Intel Corporation
- George S. POWLEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE FOR PARALLEL CONFIGURATION OF PROGRAMMABLE DEVICES
- Publication number 20190103872
- Publication date Apr 4, 2019
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR ADDRESS-MAPPED CONTROL OF FIELD PROGRAMMABLE...
- Publication number 20180234383
- Publication date Aug 16, 2018
- Raytheon Company
- Brandon H. Daugherty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FEEDBACK CONTROLLER FOR RESONANT GATE DRIVE
- Publication number 20180234092
- Publication date Aug 16, 2018
- ABB Schweiz AG
- Jukka-Pekka Sjoroos
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE LOGIC CIRCUIT AND METHOD FOR IMPLEMENTING A BOOLEAN FU...
- Publication number 20180091155
- Publication date Mar 29, 2018
- INFINEON TECHNOLOGIES AG
- Thomas Kuenemund
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE
- Publication number 20180090616
- Publication date Mar 29, 2018
- Semiconductor Energy Laboratory Co., Ltd
- Takashi NAKAGAWA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FEEDBACK CONTROL SYSTEMS WITH PULSE DENSITY SIGNAL PROCESSING CAPAB...
- Publication number 20180026642
- Publication date Jan 25, 2018
- Altera Corporation
- Benjamin Peter Jeppesen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DEVICES WITH AN ARRAY OF SUPERCONDUCTING LOGIC CELLS
- Publication number 20170104491
- Publication date Apr 13, 2017
- Microsoft Technology Licensing, LLC
- Steven B. Shauck
- G06 - COMPUTING CALCULATING COUNTING

using an AND matrix followed by an OR matrix

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Logic drive based on multichip package using interconnection bridge

FPGA-based design method and device for equally dividing interval

Programmable logic array with reliable timing

Method and apparatus for providing multiple power domains to a prog...

Sectional configuration for programmable logic devices

Logic drive based on chip scale package comprising standardized com...

Method and apparatus for providing multiple power domains a program...

Detection and mitigation of unstable cells in unclonable cell array

Data processing engine array architecture with memory tiles

Data processing engine array architecture with memory tiles

Field-programmable gate array with updatable security schemes

Interface for parallel configuration of programmable devices

Thermal load balancing of programmable devices

Logic integrated circuit

Logic drive based on multichip package using interconnection bridge

JTL-based superconducting logic arrays and FPGAS

Sum-of-products accelerator array

Semiconductor device, display system, and electronic device

Configuration engine for a programmable circuit

Programmable array logic

Interface for parallel configuration of programmable devices

Clock synchronization in multi-die field programmable gate array de...

Field programmable operation block array

JTL-based superconducting logic arrays and FPGAs

Programmable logic circuit and method for implementing a boolean fu...

System and method to proxy networking statistics for FPGA cards

Increasing available flip-flop count for placement of a circuit des...

Four-input josephson gates

Differential offset calibration of chopping switches in time-interl...

System and method for editing video and audio clips

Patents Applicationslast 30 patents

LOGIC DRIVE BASED ON MULTICHIP PACKAGE USING INTERCONNECTION BRIDGE

PROGRAMMABLE LOGIC ARRAY WITH RELIABLE TIMING

SECTIONAL CONFIGURATION FOR PROGRAMMABLE LOGIC DEVICES

Method and Apparatus for Providing Multiple Power Domains in A Prog...

Method and Apparatus for Providing Multiple Power Domains to A Prog...

CHAINED COMMAND ARCHITECTURE FOR PACKET PROCESSING

VIRTUAL MEMORY WITH DYNAMIC SEGMENTATION FOR MULTI-TENANT FPGAS

DETECTION AND MITIGATION OF UNSTABLE CELLS IN UNCLONABLE CELL ARRAY

METHOD AND APPARATUS FOR PROVIDING MULTIPLE POWER DOMAINS A PROGRAM...

FIELD-PROGRAMMABLE GATE ARRAY WITH UPDATABLE SECURITY SCHEMES

LOGIC DRIVE BASED ON MULTICHIP PACKAGE USING INTERCONNECTION BRIDGE

Determining Sums Using Logic Circuits

INTERFACE FOR PARALLEL CONFIGURATION OF PROGRAMMABLE DEVICES

LOGIC INTEGRATED CIRCUIT

LOGIC DRIVE BASED ON CHIP SCALE PACKAGE COMPRISING STANDARDIZED COM...

LOGIC DRIVE BASED ON MULTICHIP PACKAGE USING INTERCONNECTION BRIDGE

PROGRAMMABLE ARRAY LOGIC

JTL-BASED SUPERCONDUCTING LOGIC ARRAYS AND FPGAS

FOUR-INPUT JOSEPHSON GATES

SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE

SUM-OF-PRODUCTS ACCELERATOR ARRAY

CLOCK SYNCHRONIZATION IN MULTI-DIE FIELD PROGRAMMABLE GATE ARRAY DE...

METHOD AND APPARATUS FOR REDUCING IDLE POWER CONSUMPTION FROM PROGR...

INTERFACE FOR PARALLEL CONFIGURATION OF PROGRAMMABLE DEVICES

SYSTEM AND METHOD FOR ADDRESS-MAPPED CONTROL OF FIELD PROGRAMMABLE...

FEEDBACK CONTROLLER FOR RESONANT GATE DRIVE

PROGRAMMABLE LOGIC CIRCUIT AND METHOD FOR IMPLEMENTING A BOOLEAN FU...

SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE

FEEDBACK CONTROL SYSTEMS WITH PULSE DENSITY SIGNAL PROCESSING CAPAB...

DEVICES WITH AN ARRAY OF SUPERCONDUCTING LOGIC CELLS