using clearing, invalidating or resetting means

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0891using clearing, invalidating or resetting means

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Patents Grantslast 30 patents

Information Patent Grant
Synchronous write coalescing
- Patent number 12,271,316
- Issue date Apr 8, 2025
- Avago Technologies International Sales Pte. Limited
- Arun Prakash Jana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reactive deep-frozen adaptive replacement cache and drive interface
- Patent number 12,259,819
- Issue date Mar 25, 2025
- International Business Machines Corporation
- Ben Sasson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor-based system for allocating cache lines to a higher-level...
- Patent number 12,259,820
- Issue date Mar 25, 2025
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with branch target buffer whose entries include fetc...
- Patent number 12,253,951
- Issue date Mar 18, 2025
- Ventana Micro Systems Inc.
- John G Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying and consenting to permissions for workflow and code exe...
- Patent number 12,254,069
- Issue date Mar 18, 2025
- Microsoft Technology Licensing, LLC
- Sunay Vaishnav
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for cache management in a network device
- Patent number 12,253,946
- Issue date Mar 18, 2025
- Telefonaktiebolaget LM Ericsson (publ)
- Anju Thomas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-block cache fetch techniques
- Patent number 12,248,399
- Issue date Mar 11, 2025
- Apple Inc.
- Winnie W. Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory efficient multi-versioned concurrency for a hypercube memory...
- Patent number 12,248,403
- Issue date Mar 11, 2025
- Workday, Inc.
- Srinivas Vemuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recording a memory value trace for use with a separate cache cohere...
- Patent number 12,242,383
- Issue date Mar 4, 2025
- Microsoft Technology Licensing, LLC
- Jordi Mola
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peripheral component handling of memory read requests
- Patent number 12,242,399
- Issue date Mar 4, 2025
- ARM Limited
- Jacob Joseph
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache invalidation across distributed microservices
- Patent number 12,242,382
- Issue date Mar 4, 2025
- Oracle International Corporation
- Riaz Ahmad Aimandi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache locality when using repurposed cache memory
- Patent number 12,235,765
- Issue date Feb 25, 2025
- NVIDIA Corporation
- Ariel Szapiro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Criticality-informed caching policies with multiple criticality levels
- Patent number 12,235,769
- Issue date Feb 25, 2025
- Apple Inc.
- Tyler J. Huberty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable caches for improving performance of graphics process...
- Patent number 12,229,054
- Issue date Feb 18, 2025
- QUALCOMM Incorporated
- Suryanarayana Murthy Durbhakula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanisms for a contention free lookup in a cache with concurrent...
- Patent number 12,222,866
- Issue date Feb 11, 2025
- Samsung Electronics Co., Ltd.
- Vijaya Jakkula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor, computer system, and method for flushing hierarchical ca...
- Patent number 12,222,867
- Issue date Feb 11, 2025
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Weilin Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore, multibank, fully concurrent coherence controller
- Patent number 12,223,165
- Issue date Feb 11, 2025
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and method designating an in-core cache of a hierarchical...
- Patent number 12,222,860
- Issue date Feb 11, 2025
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Weilin Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching techniques using a two-level read cache
- Patent number 12,222,862
- Issue date Feb 11, 2025
- Dell Products L.P.
- Vladimir Shveidel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and operating method for a homogeneous dual computing system
- Patent number 12,222,868
- Issue date Feb 11, 2025
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Yingbing Guan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with dynamic cache management
- Patent number 12,216,573
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically sized redundant write buffer with sector-based tracking
- Patent number 12,216,586
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Cagdas Dirik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recording a memory value trace for use with a separate cache cohere...
- Patent number 12,210,455
- Issue date Jan 28, 2025
- Microsoft Technology Licensing, LLC
- Jordi Mola
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor data cache with shared mid-level cache and low-level cache
- Patent number 12,210,457
- Issue date Jan 28, 2025
- Marvell Asia Pte, Ltd.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Flushing Cache Lines Involving Persistent Memory
- Publication number 20250117319
- Publication date Apr 10, 2025
- Altera Corporation
- Sharath Raghava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-STALLING, NON-BLOCKING TRANSLATION LOOKASIDE BUFFER INVALIDATION
- Publication number 20250117338
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Daniel Brad WU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE PURGING IN A DISTRIBUTED NETWORKED SYSTEM
- Publication number 20250117334
- Publication date Apr 10, 2025
- CLOUDFLARE, INC.
- Zaidoon Abd Al Hadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Preemptive Flushing of Processing-in-Memory Data Structures
- Publication number 20250110887
- Publication date Apr 3, 2025
- ADVANCED MICRO DEVICES, INC.
- David Andrew Werner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING CONTAINERIZED APPLICATIONS WITH CACHING
- Publication number 20250110883
- Publication date Apr 3, 2025
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP.
- Lianjie Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selective Transfer of Cache Block Data
- Publication number 20250110884
- Publication date Apr 3, 2025
- ADVANCED MICRO DEVICES, INC.
- Shaizeen Dilawarhusen Aga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Speculative Cache Invalidation for Processing-in-Memory Instructions
- Publication number 20250110886
- Publication date Apr 3, 2025
- ADVANCED MICRO DEVICES, INC.
- Travis Henry Boraten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH TARGET BUFFER RUN-AHEAD
- Publication number 20250110882
- Publication date Apr 3, 2025
- Microsoft Technology Licensing, LLC
- Julio Gago Alonso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CACHE OPTIMIZATION
- Publication number 20250103511
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coherency Control for Compressed Graphics Data
- Publication number 20250104181
- Publication date Mar 27, 2025
- Apple Inc.
- Karthik Ramani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Random-Access Memory (DRAM) Efficiency Calculation and Util...
- Publication number 20250103479
- Publication date Mar 27, 2025
- QUALCOMM Incorporated
- Shriharsha CHEBBI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coherence Directory Way Tracking in Coherent Agents
- Publication number 20250103496
- Publication date Mar 27, 2025
- Apple Inc.
- Ilya Granovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SMART FACTORY RESET PROCEDURE
- Publication number 20250094339
- Publication date Mar 20, 2025
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Control to Preserve Register Data
- Publication number 20250094357
- Publication date Mar 20, 2025
- Apple Inc.
- Jonathan M. Redshaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20250094044
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Atomic Smashing
- Publication number 20250086116
- Publication date Mar 13, 2025
- Apple Inc.
- Jedd O. Haberstro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE DEVICE FOR CHANGING MAP UPDATE MODE
- Publication number 20250086105
- Publication date Mar 13, 2025
- SK HYNIX INC.
- Sung Jin PARK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ROUTING FOR POOLED AND TIERED DATA ARCHITECTURES
- Publication number 20250086123
- Publication date Mar 13, 2025
- Intel Corporation
- Karthik Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR UTILIZING PREFETCH CACHE FOR MEMORY DEVICE
- Publication number 20250077434
- Publication date Mar 6, 2025
- Samsung Electronics Co., Ltd.
- Tung Pham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DEVICE, MEMORY DEVICE, AND OPERATING METHOD OF MEMORY DE...
- Publication number 20250077427
- Publication date Mar 6, 2025
- Samsung Electronics Co., Ltd.
- Moongyung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROPROCESSOR WITH BRANCH TARGET BUFFER WHOSE ENTRIES INCLUDE FETC...
- Publication number 20250077438
- Publication date Mar 6, 2025
- Ventana Micro Systems Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DEVICES, INCLUDING MEMORY DEVICES, AND OPERATING METHODS...
- Publication number 20250077437
- Publication date Mar 6, 2025
- Samsung Electronics Co., Ltd.
- Moongyung Kim
- G06 - COMPUTING CALCULATING COUNTING

using clearing, invalidating or resetting means

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Synchronous write coalescing

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for multi-banked victim cache with dual datapath

Reactive deep-frozen adaptive replacement cache and drive interface

Processor-based system for allocating cache lines to a higher-level...

Microprocessor with branch target buffer whose entries include fetc...

Identifying and consenting to permissions for workflow and code exe...

Method and system for cache management in a network device

Multi-block cache fetch techniques

Memory efficient multi-versioned concurrency for a hypercube memory...

Recording a memory value trace for use with a separate cache cohere...

Peripheral component handling of memory read requests

Cache invalidation across distributed microservices

Data initialization techniques

Cache locality when using repurposed cache memory

Criticality-informed caching policies with multiple criticality levels

Reconfigurable caches for improving performance of graphics process...

Mechanisms for a contention free lookup in a cache with concurrent...

Processor, computer system, and method for flushing hierarchical ca...

Multicore, multibank, fully concurrent coherence controller

Processor and method designating an in-core cache of a hierarchical...

Caching techniques using a two-level read cache

Processor and operating method for a homogeneous dual computing system

Memory device with dynamic cache management

Dynamically sized redundant write buffer with sector-based tracking

Atomic compare and swap in a coherent cache system

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Recording a memory value trace for use with a separate cache cohere...

Processor data cache with shared mid-level cache and low-level cache

Patents Applicationslast 30 patents

Flushing Cache Lines Involving Persistent Memory

NON-STALLING, NON-BLOCKING TRANSLATION LOOKASIDE BUFFER INVALIDATION

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

MULTI-TILE MEMORY MANAGEMENT

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

CACHE PURGING IN A DISTRIBUTED NETWORKED SYSTEM

Preemptive Flushing of Processing-in-Memory Data Structures

ACCELERATING CONTAINERIZED APPLICATIONS WITH CACHING

Selective Transfer of Cache Block Data

Speculative Cache Invalidation for Processing-in-Memory Instructions

BRANCH TARGET BUFFER RUN-AHEAD

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

SYSTEMS AND METHODS FOR CACHE OPTIMIZATION

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

Coherency Control for Compressed Graphics Data

Dynamic Random-Access Memory (DRAM) Efficiency Calculation and Util...

Coherence Directory Way Tracking in Coherent Agents

SMART FACTORY RESET PROCEDURE

Cache Control to Preserve Register Data

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

MULTICORE SHARED CACHE OPERATION ENGINE

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

Atomic Smashing

STORAGE DEVICE FOR CHANGING MAP UPDATE MODE

ADAPTIVE ROUTING FOR POOLED AND TIERED DATA ARCHITECTURES

SYSTEM AND METHOD FOR UTILIZING PREFETCH CACHE FOR MEMORY DEVICE

ELECTRONIC DEVICE, MEMORY DEVICE, AND OPERATING METHOD OF MEMORY DE...

MICROPROCESSOR WITH BRANCH TARGET BUFFER WHOSE ENTRIES INCLUDE FETC...

ELECTRONIC DEVICES, INCLUDING MEMORY DEVICES, AND OPERATING METHODS...