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H03K2005/00247

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HELECTRICITY H03Electronic circuits H03KPULSE TECHNIQUE

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Patents Grantslast 30 patents

Information Patent Grant
Clock mode determination in a memory system
- Patent number 11,880,569
- Issue date Jan 23, 2024
- Mosaid Technologies Incorporated
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive control of non-overlapping drive signals
- Patent number 11,855,615
- Issue date Dec 26, 2023
- Silanna Asia Pte Ltd
- Joseph H. Colles
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory package, semiconductor device, and storage device
- Patent number 11,736,098
- Issue date Aug 22, 2023
- Samsung Electronics Co., Ltd.
- Tongsung Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital timer delay line with sub-sample accuracy
- Patent number 11,695,399
- Issue date Jul 4, 2023
- Dialog Semiconductor (UK) Limited
- Michael Kramer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock mode determination in a memory system
- Patent number 11,669,248
- Issue date Jun 6, 2023
- Mosaid Technologies Incorporated
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive control of non-overlapping drive signals
- Patent number 11,611,337
- Issue date Mar 21, 2023
- Silanna Asia Pte Ltd
- Joseph H. Colles
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Dual clock signal to pulse-width modulated signal conversion circuit
- Patent number 11,451,221
- Issue date Sep 20, 2022
- LINEARIN TECHNOLOGY CORPORATION
- Jinqiao Zhu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock mode determination in a memory system
- Patent number 11,347,396
- Issue date May 31, 2022
- Mosaid Technologies Incorporated
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power fast-setting delay circuit
- Patent number 10,879,882
- Issue date Dec 29, 2020
- QUALCOMM Incorporated
- George Shing
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock mode determination in a memory system
- Patent number 10,866,739
- Issue date Dec 15, 2020
- Conversant Intellectual Property Management Inc.
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive control of non-overlapping drive signals
- Patent number 10,855,270
- Issue date Dec 1, 2020
- Silanna Asia Pte Ltd
- Joseph H. Colles
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ring oscillator-based programmable delay line
- Patent number 10,587,253
- Issue date Mar 10, 2020
- QUALCOMM Incorporated
- Yu Huang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock mode determination in a memory system
- Patent number 10,489,057
- Issue date Nov 26, 2019
- Conversant Intellectual Property Management Inc.
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arbitrary delay buffer
- Patent number 10,250,242
- Issue date Apr 2, 2019
- Integrated Device Technology, Inc.
- Chengming He
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Precision modulation timer (PMT) integrated in a programmable logic...
- Patent number 10,200,040
- Issue date Feb 5, 2019
- AnDAPT, Inc.
- Patrick J. Crotty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock mode determination in a memory system
- Patent number 10,140,028
- Issue date Nov 27, 2018
- Conversant Intellectual Property Management Inc.
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock mode determination in a memory system
- Patent number 9,971,518
- Issue date May 15, 2018
- Conversant Intellectual Property Management Inc.
- Peter B. Gillingham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay structure for a memory interface
- Patent number 9,520,864
- Issue date Dec 13, 2016
- QUALCOMM Incorporated
- Jan Christian Diffenderfer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-adjusting duty cycle tuner
- Patent number 9,484,894
- Issue date Nov 1, 2016
- International Business Machines Corporation
- Takeo Yasuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-adjusting duty cycle tuner
- Patent number 9,484,895
- Issue date Nov 1, 2016
- International Business Machines Corporation
- Takeo Yasuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tunable clock system
- Patent number 9,407,248
- Issue date Aug 2, 2016
- Laurence H. Cooke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock mode determination in a memory system
- Patent number 9,384,847
- Issue date Jul 5, 2016
- Conversant Intellectual Property Management Inc.
- Peter B. Gillingham
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable clock system
- Patent number 9,124,256
- Issue date Sep 1, 2015
- Laurence H. Cooke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock mode determination in a memory system
- Patent number 8,854,915
- Issue date Oct 7, 2014
- Conversant Intellectual Property Management Inc.
- Peter B. Gillingham
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing controller counts clock signals to produce a control signal...
- Patent number 8,659,530
- Issue date Feb 25, 2014
- Samsung Display Co., Ltd.
- Sang-don Bae
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Clock mode determination in a memory system
- Patent number 8,644,108
- Issue date Feb 4, 2014
- MOSAID Technologies Incorporated
- Peter B. Gillingham
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock mode determination in a memory system
- Patent number 8,432,767
- Issue date Apr 30, 2013
- MOSAID Technologies Incorporated
- Peter B. Gillingham
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse width modulation circuit and liquid jet printing apparatus
- Patent number 8,022,743
- Issue date Sep 20, 2011
- Seiko Epson Corporation
- Shinichi Miyazaki
- B41 - PRINTING LINING MACHINES TYPEWRITERS STAMPS
Information Patent Grant
Method and system for providing a power-on reset pulse
- Patent number 8,018,256
- Issue date Sep 13, 2011
- Broadcom Corporation
- Alireza Zolfaghari
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay circuit
- Patent number 7,911,250
- Issue date Mar 22, 2011
- Renesas Electronics Corporation
- Junya Okubo
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20240168636
- Publication date May 23, 2024
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20230384935
- Publication date Nov 30, 2023
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Control of Non-Overlapping Drive Signals
- Publication number 20230188132
- Publication date Jun 15, 2023
- Silanna Asia Pte Ltd
- Joseph H. Colles
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE
- Publication number 20230179193
- Publication date Jun 8, 2023
- Samsung Electronics Co., Ltd.
- Tongsung Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20230046725
- Publication date Feb 16, 2023
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL CLOCK SIGNAL TO PULSE-WIDTH MODULATED SIGNAL CONVERSION CIRCUIT
- Publication number 20220038086
- Publication date Feb 3, 2022
- SHANGHAI GUESTGOOD ELECTRONICS CO. LTD.
- Jinqiao Zhu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital Timer Delay Line with Sub-Sample Accuracy
- Publication number 20220038084
- Publication date Feb 3, 2022
- Dialog Semiconductor (UK) Limited
- Michael Kramer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20210132799
- Publication date May 6, 2021
- Conversant Intellectual Property Management Inc.
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Control of Non-Overlapping Drive Signals
- Publication number 20210111715
- Publication date Apr 15, 2021
- Silanna Asia Pte Ltd
- Joseph H. Colles
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20200110535
- Publication date Apr 9, 2020
- Conversant Intellectual Property Management Inc.
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20190163365
- Publication date May 30, 2019
- Conversant Intellectual Property Management Inc.
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20180314424
- Publication date Nov 1, 2018
- Conversant Intellectual Property Management Inc.
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20170322730
- Publication date Nov 9, 2017
- Conversant Intellectual Property Management Inc.
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY CONTROL CIRCUIT
- Publication number 20140368249
- Publication date Dec 18, 2014
- SK HYNIX INC.
- Kwang Su LEE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TUNABLE CLOCK DISTRIBUTION SYSTEM
- Publication number 20140333364
- Publication date Nov 13, 2014
- Laurence H. Cooke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20140133243
- Publication date May 15, 2014
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-ADJUSTING DUTY CYCLE TUNER
- Publication number 20140084979
- Publication date Mar 27, 2014
- International Business Machines Corporation
- Takeo Yasuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SELF-ADJUSTING DUTY CYCLE TUNER
- Publication number 20140009197
- Publication date Jan 9, 2014
- International Business Machines Corporation
- Takeo Yasuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20130235659
- Publication date Sep 12, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20110110165
- Publication date May 12, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay Circuit
- Publication number 20100134169
- Publication date Jun 3, 2010
- NEC Electronics Corporation
- Junya Okubo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PULSE WIDTH MODULATION CIRCUIT AND LIQUID JET PRINTING APPARATUS
- Publication number 20100097114
- Publication date Apr 22, 2010
- SEIKO EPSON CORPORATION
- Shinichi MIYAZAKI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and System for Providing a Power-On Reset Pulse
- Publication number 20090167378
- Publication date Jul 2, 2009
- Alireza Zolfaghari
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20090039927
- Publication date Feb 12, 2009
- MOSAID Technologies Incorporated
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Oscillation Circuit, Power Supply Circuit, Display Device, and Elec...
- Publication number 20090002083
- Publication date Jan 1, 2009
- SONY CORPORATION
- Yusuke Takahashi
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
TIMING CONTROLLER, LIQUID CRYSTAL DISPLAY INCLUDING TIMING CONTROLL...
- Publication number 20080309606
- Publication date Dec 18, 2008
- Sang-don Bae
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
Delay unit
- Publication number 20080180182
- Publication date Jul 31, 2008
- Yen-An Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Electronic Circuit Wherein an Asynchronous Delay is Realized
- Publication number 20080164929
- Publication date Jul 10, 2008
- Koninklijke Philips Electronics, N.V.
- Jozef Laurentius Wilhelmus Kessels
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY CIRCUIT AND DELAY SYNCHRONIZATION LOOP DEVICE
- Publication number 20080136485
- Publication date Jun 12, 2008
- ELPIDA MEMORY INC.
- Yasuhiro TAKAI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL POWER-ON RESET
- Publication number 20080122512
- Publication date May 29, 2008
- LSI Logic Corporation
- David H. Lin
- G06 - COMPUTING CALCULATING COUNTING

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Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Clock mode determination in a memory system

Adaptive control of non-overlapping drive signals

Memory package, semiconductor device, and storage device

Digital timer delay line with sub-sample accuracy

Clock mode determination in a memory system

Adaptive control of non-overlapping drive signals

Dual clock signal to pulse-width modulated signal conversion circuit

Clock mode determination in a memory system

Low-power fast-setting delay circuit

Clock mode determination in a memory system

Adaptive control of non-overlapping drive signals

Ring oscillator-based programmable delay line

Clock mode determination in a memory system

Arbitrary delay buffer

Precision modulation timer (PMT) integrated in a programmable logic...

Clock mode determination in a memory system

Clock mode determination in a memory system

Delay structure for a memory interface

Self-adjusting duty cycle tuner

Self-adjusting duty cycle tuner

Tunable clock system

Clock mode determination in a memory system

Tunable clock system

Clock mode determination in a memory system

Timing controller counts clock signals to produce a control signal...

Clock mode determination in a memory system

Clock mode determination in a memory system

Pulse width modulation circuit and liquid jet printing apparatus

Method and system for providing a power-on reset pulse

Delay circuit

Patents Applicationslast 30 patents

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

Adaptive Control of Non-Overlapping Drive Signals

MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

DUAL CLOCK SIGNAL TO PULSE-WIDTH MODULATED SIGNAL CONVERSION CIRCUIT

Digital Timer Delay Line with Sub-Sample Accuracy

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

Adaptive Control of Non-Overlapping Drive Signals

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

DELAY CONTROL CIRCUIT

TUNABLE CLOCK DISTRIBUTION SYSTEM

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

SELF-ADJUSTING DUTY CYCLE TUNER

SELF-ADJUSTING DUTY CYCLE TUNER

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

Delay Circuit

PULSE WIDTH MODULATION CIRCUIT AND LIQUID JET PRINTING APPARATUS

Method and System for Providing a Power-On Reset Pulse

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

Oscillation Circuit, Power Supply Circuit, Display Device, and Elec...

TIMING CONTROLLER, LIQUID CRYSTAL DISPLAY INCLUDING TIMING CONTROLL...

Delay unit

Electronic Circuit Wherein an Asynchronous Delay is Realized

DELAY CIRCUIT AND DELAY SYNCHRONIZATION LOOP DEVICE

DIGITAL POWER-ON RESET