Patent Application
20080122512
The present invention relates to a power-on reset circuit generally and, more particularly, to a method and/or apparatus for implementing a digital power-on reset.
When power is first applied to a chip (or integrated circuit) a reset signal is often asserted to put the chip into a known state to allow proper operation. In conventional systems, a Power-On-Reset (POR) circuit applies a reset signal for a specified amount of time after power has been applied. The reset signal is held long enough to extend longer than the time for the chip to completely receive power.
Conventional approaches often use an analog circuit to assert the reset signal after the power achieves a certain voltage threshold level. The reset signal is held for a specified amount of time. The POR circuit can be implemented externally to the chip with the reset signal being supplied as an input to the chip. In some cases, the POR circuit can be implemented as an analog component on the integrated circuit.
It would be desirable to implement a power-on reset circuit using only digital circuitry.
The present invention concerns an apparatus comprising a plurality of flip-flops and a compare circuit. The flip-flops may each be configured to (i) receive a clock signal and an input signal and (ii) generate an output signal. The flip-flops may be configured in series such that the output,signal of a first of the flip-flops is presented as the input signal to a second of the flip-flops. The compare circuit may be configured to generate a reset signal in response to each of the output signals. The reset signal is generated until each of the output signals matches a set of predetermined values stored in the compare circuit.
The objects, features and advantages of the present invention include implementing a power-on reset circuit that may (i) be implemented using all digital components, (ii) implement the reset starting from the beginning of a circuit power up, (iii) adjust a pulse width of the reset signal (iv) minimize the pulse width of the reset signal by adapting to a characteristic of a stable system, (v) provide a simplified chip design by only using digital logic (instead of analog components), (vi) be implemented inexpensively by using only a very small amount of silicon area, (vii) use only a small amount of power, and/or (viii) provide low-leakage cells that may be used to minimize power consumption.
These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
Referring to
The flip-flops 102a-102n may be configured in a shift register configuration. In general, each of the flip-flops 102a-102n has one of a number of inputs 106a-106n that receives a signal (e.g., CLOCK). The signal CLOCK may be a periodic clock signal that has a particular frequency of oscillation. Each of the flip-flops 102a-102n also has one or a number of data inputs 108a-108n and one of a number of outputs 110a-110n (e.g., the flip-flop 108a has an input 106a, an input 108a and an output 110a). The data input (e.g., 108b) of each of the flip-flops (e.g., 102b) is normally connected to an output (e.g., 110a) of a previous one of the flip-flops (e.g., 102a). In general, the flip-flops 102a-102n do not use a feedback of the signal CLOCK.
The first flip-flop 102a normally receives a feedback of the output 110a of the first flip-flop 102a. The feedback is normally inverted through an inverter 112. The outputs 110a-110n of each of the flip-flops 102a-102n are normally presented to a number of inputs 114a-114n of the compare circuit 104. After a specified maximum number of clock cycles, the flip-flops 102a-102n normally achieve a known state. The compare circuit 104 compares the state of the signals presented at each of the outputs 110a-110n to a known state (or pattern). If all of the flip-flops 102a-102n have not yet achieved the known state, the compare circuit 104 will assert a signal (e.g., RESET). The signal RESET will remain asserted until the outputs 110a-110n of the flip-flops 102a-102n reach the known state. Settling into the known state of the flip-flops normally indicates a characteristic of a stable system.
The flip-flops 102a-102n may be implemented as a shift register, with the leading flip-flop 102a toggling each clock cycle. The toggling of the flip-flop 102a will propagate through the chain of flip-flops 102a-102n. When power is first applied to the circuit 100, the flip-flops 102a-102n will have a random distribution of 1s and 0s presented to the respective data inputs 108a-108n. Since the pattern stored in the flip-flops 102a-102n is very unlikely to match the two known patterns in the compare circuit 104 (e.g., 0x5555555555 and 0xAAAAAAAAAA), the signal RESET will initially be asserted. After a number of clock cycles (between 1 and 40 depending on the initial power-up pattern), the flip-flops 102a-102n will contain an alternating pattern of 1s and 0s. Until the alternate pattern matches 0x5555555555 or 0xAAAAAAAAAA each clock cycle, the signal RESET will remain asserted.
The circuit 100 relies on the probability being extremely low that the steady-state pattern is achieved when power is first applied to the circuit. Given a random distribution of 1s and 0s, the likelihood is only 2 in 240, (in the example when 40 flip-flops 102a-102n are implemented), or one in half a trillion chance that a steady state is achieved immediately upon the application of power and resulting in the signal RESET not being asserted. The circuit employs checking for a pattern of both 1s and 0s (as opposed to all 1s or all 0s) so that if the semiconductor characteristics favor a flip-flop value of 1 or 0 when power is first applied, the steady-state patterns will not be achieved.
The length of the signal RESET may be varied to meet the design criteria of a particular implementation. The length of the signal RESET normally depends on the initial power-up pattern. However, the maximum length (or pulse) of the signal RESET is normally 40 (for the example when the number of flip-flops 102a-102n implemented is 40).
The length of the shift register may be adjusted to meet the design criteria of a particular implementation by adding or subtracting the number of the flip-flops 102a-102n. Having a longer shift register chain lessens the probability that the steady-state pattern would be achieved upon power-up. Having a longer shift register chain also lengthens (on average) the time the signal RESET is asserted. Having a shorter shift register chain shortens the average time the signal RESET is asserted. A shorter shift register chain also uses less logic, but has a higher probability that the steady-state pattern would be achieved upon power-up.
The digital POR circuit 100 will normally assert the signal RESET from the onset of power being applied, until enough clock cycles have been received to achieve a steady-state condition. In the steady-state condition, the circuit 100 does not assert the signal RESET. The particular number of flip-flops 102a-102n normally determines the chance that the circuit 100 will be in the steady-state condition at the onset of power being applied. The larger the number of flip-flops 102a-102n, the less chance of a random steady state condition on power up.
The greater the number of flip-flops 102a-102n, the longer the signal RESET will be asserted. A shorter assertion of the signal RESET may be useful for systems in which a shorter time from power-on to functional operation is important. In such a case, the chain of flip-flops 102a-102n may be split into a number of shorter chains (to be described in more detail in connection with
Referring to
Another shift register chain may be implemented with the flip-flops 222a-222n. Similar to the circuit 100 of
In general, the circuit 200 implements multiple shift register chains. Each of the chains is shown having 24 flip-flops. However, the particular number of chains may be varied (e.g., increased or decreased) to meet the design criteria of a particular implementation. The multiple chains normally allow the use of a large number of flip-flops 202a-202n and 222a-222n. Increasing the number of flip-flops decreases the probability that the steady-state pattern would be achieved upon power-up. However, a balance is normally used in selecting the number of flip-flops 222a-222n. Since fewer flip-flops 202a-202n and 222a-222n may achieve steady-state in fewer clock cycles.
The steady-state pattern that is achieved may be adjusted. The particular predetermined pattern may be modified in a number of ways. For example, logic may be placed within the shift register chains 202a-202n and 222a-222n. In another example, separate chains may be implemented with different steady-state patterns in each chain.
The following TABLE 1 illustrates the operation of the circuit 200:
After a variable number of clock cycles, which depends on the initial power-up conditions of the flip-flops, the steady state condition of the circuit 200 is achieved. In the example shown, 24 cycles are needed to achieve the steady state condition. With different initial conditions, the circuit 200 may settle to the steady-state in a different number of cycles. In the following TABLE 2, 16 cycles are needed to achieve the steady state condition:
Referring to
Referring to
Each of the flip-flops 302a-302n has one of a number of inputs 304a-304n that receive the gated clock signal CLOCK1, one of a number of data inputs 306a-306n and one of a number of outputs 308a-308n. Similar to the circuit 100 of
Gating the flip-flops 302a-302n of shift register when the steady-state pattern is achieved saves power. The flip-flops 302a-302n are normally clocked while the signal RESET is asserted. When the steady-state pattern is detected, the signal RESET is deasserted and the flip-flops are no longer clocked.
Referring to
The following TABLE 3 shows the operation of the alternate implementation of the circuit 300:
Again, after a number of clock cycles, which depends on the initial power-up conditions of the flip-flops 302a-302n, 304a-304n, 306a-306n, and 308a-308n, the steady state condition of the circuit 300 is achieved. Since the chains 302a-302n, 304a-304n, 306a-306n, and 308a-308n are shorter (e.g., shown as 124 flip-flop chains), the average time to achieve the steady state is shorter.
The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed)to meet the design criteria of a particular implementation. Additionally, inverters may be added to change a particular polarity of the signals.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.
