using field-effect transistors

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H03K19/215

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Parent Industries

HELECTRICITY H03Electronic circuits H03KPULSE TECHNIQUE H03K19/00Logic circuits

Current Industry

H03K19/215using field-effect transistors

Industries

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for generating low-density parity-check (LDPC)...
- Patent number 12,126,360
- Issue date Oct 22, 2024
- Silicon Motion, Inc.
- Shiuan-Hao Kuo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-speed communication link with self-aligned scrambling
- Patent number 11,843,486
- Issue date Dec 12, 2023
- QUALCOMM Incorporated
- Tomer Rafael Ben-Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data compressor logic circuit
- Patent number 11,831,341
- Issue date Nov 28, 2023
- ARM Limited
- Shardendu Shekhar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-loss arithmetic circuit and operating method of the same
- Patent number 11,816,449
- Issue date Nov 14, 2023
- NEONEXUS PTE. LTD.
- Zhenlong Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static random-access memory (SRAM) compute in-memory integration
- Patent number 11,776,608
- Issue date Oct 3, 2023
- QUALCOMM Incorporated
- Xia Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fabrication of a majority logic gate having non-linear input capaci...
- Patent number 11,742,860
- Issue date Aug 29, 2023
- Kepler Computing Inc.
- Sasikanth Manipatruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamically weighted exclusive or gate having weighted output segme...
- Patent number 11,677,539
- Issue date Jun 13, 2023
- KANDOU LABS, S.A.
- Armin Tajalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
In-memory computing device supporting arithmetic operations
- Patent number 11,664,069
- Issue date May 30, 2023
- Korea University Research and Business Foundation
- Jongsun Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed communication link with self-aligned scrambling
- Patent number 11,522,738
- Issue date Dec 6, 2022
- QUALCOMM Incorporated
- Tomer Rafael Ben-Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logical operations using a logical operation component
- Patent number 11,508,431
- Issue date Nov 22, 2022
- Micron Technology, Inc.
- Glen E. Hush
- G11 - INFORMATION STORAGE
Information Patent Grant
Compact 3D stacked-CFET architecture for complex logic cells
- Patent number 11,437,376
- Issue date Sep 6, 2022
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamically weighted exclusive or gate having weighted output segme...
- Patent number 11,362,800
- Issue date Jun 14, 2022
- KANDOU LABS, S.A.
- Armin Tajalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Full adder cell with improved power efficiency
- Patent number 11,294,631
- Issue date Apr 5, 2022
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for providing a variation resistant magnetic junc...
- Patent number 11,290,110
- Issue date Mar 29, 2022
- Samsung Electronics Co., Ltd.
- Borna J. Obradovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Majority logic gate with non-linear input capacitors
- Patent number 11,277,137
- Issue date Mar 15, 2022
- Kepler Computing, Inc.
- Sasikanth Manipatruni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clockless delay adaptation loop for random data
- Patent number 11,239,834
- Issue date Feb 1, 2022
- Texas Instruments Incorporated
- Abishek Manian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Full adder cell with improved power efficiency
- Patent number 11,169,779
- Issue date Nov 9, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-input exclusive NOR/OR gate using a CMOS circuit
- Patent number 11,152,942
- Issue date Oct 19, 2021
- Samsung Electronics Co., Ltd.
- Hareharan Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Processing method for applying analog dynamic circuit to digital te...
- Patent number 11,144,697
- Issue date Oct 12, 2021
- RDC Semiconductor Co., Ltd.
- Hsin-Hsiung Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level shifter circuit with intermediate power domain
- Patent number 11,128,300
- Issue date Sep 21, 2021
- Apple Inc.
- Nathan F. Hanagami
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Asynchronous polymorphic logic gate design
- Patent number 11,095,287
- Issue date Aug 17, 2021
- Jia Di
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and devices for detecting open and/or shorts circuits in ME...
- Patent number 11,042,024
- Issue date Jun 22, 2021
- Google LLC
- Eric Chevallaz
- G02 - OPTICS
Information Patent Grant
Code word generating method, erroneous bit determining method, and...
- Patent number 10,992,319
- Issue date Apr 27, 2021
- Shenzhen Goodix Technology Co., Ltd.
- Xiaozu Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-port memory cell and array for in-memory computing
- Patent number 10,964,362
- Issue date Mar 30, 2021
- Marvell Asia Pte, Ltd.
- Zhewei Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computational memory cell and processing array device using complem...
- Patent number 10,958,272
- Issue date Mar 23, 2021
- GSI Technology, Inc.
- Lee-Lean Shu
- G11 - INFORMATION STORAGE
Information Patent Grant
Positive feedback XOR/XNOR gate and low-delay hybrid logic adder
- Patent number 10,924,118
- Issue date Feb 16, 2021
- Ningbo University
- Pengjun Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clockless delay adaptation loop for random data
- Patent number 10,897,245
- Issue date Jan 19, 2021
- Texas Instruments Incorporated
- Abishek Manian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Radio frequency switching circuitry with reduced switching time
- Patent number 10,897,246
- Issue date Jan 19, 2021
- Qorvo US, Inc.
- Baker Scott
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and circuit for de-biasing PUF bits
- Patent number 10,880,101
- Issue date Dec 29, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shih-Lien Linus Lu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for leveraging path delay variations in a circu...
- Patent number 10,868,535
- Issue date Dec 15, 2020
- STC.UNM
- James Plusquellic
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS
- Publication number 20240311082
- Publication date Sep 19, 2024
- Samsung Electronics Co., Ltd.
- Saurabh Shankar ZOND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD WITH IN-MEMORY COMPUTING (IMC) PROCESSOR
- Publication number 20240177768
- Publication date May 30, 2024
- Samsung Electronics Co., Ltd.
- Seungchul JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus comprising a comparator circuit
- Publication number 20240088881
- Publication date Mar 14, 2024
- Fraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.
- Raik FIEDLER
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHOD FOR GENERATING LOW-DENSITY PARITY-CHECK (LDPC)...
- Publication number 20230421178
- Publication date Dec 28, 2023
- SILICON MOTION, INC.
- Shiuan-Hao Kuo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMICALLY WEIGHTED EXCLUSIVE OR GATE HAVING WEIGHTED OUTPUT SEGME...
- Publication number 20230327846
- Publication date Oct 12, 2023
- Kandou Labs, SA
- Armin Tajalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH-SPEED COMMUNICATION LINK WITH SELF-ALIGNED SCRAMBLING
- Publication number 20230076957
- Publication date Mar 9, 2023
- QUALCOMM Incorporated
- Tomer Rafael Ben-Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATA MULTIPLEXER SINGLE PHASE FLIP-FLOP
- Publication number 20220399893
- Publication date Dec 15, 2022
- Intel Corporation
- Chinmay Joshi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW-LOSS ARITHMETIC CIRCUIT AND OPERATING METHOD OF THE SAME
- Publication number 20220334803
- Publication date Oct 20, 2022
- NeoNexus Pte. Ltd.
- Zhenlong XU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY WEIGHTED EXCLUSIVE OR GATE HAVING WEIGHTED OUTPUT SEGME...
- Publication number 20220311593
- Publication date Sep 29, 2022
- Kandou Labs, SA
- Armin Tajalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS FOR GENERATING RANDOM DATA AND A METHOD THEREOF
- Publication number 20220113946
- Publication date Apr 14, 2022
- SILICONCH SYSTEMS PVT LTD
- Jaswanth AMMINENI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-MEMORY COMPUTING DEVICE SUPPORTING ARITHMETIC OPERATIONS
- Publication number 20220028445
- Publication date Jan 27, 2022
- Korea University Research and Business Foundation
- Jongsun PARK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Level Shifter Circuit with Intermediate Power Domain
- Publication number 20210288648
- Publication date Sep 16, 2021
- Apple Inc.
- Nathan F. Hanagami
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
THREE-INPUT EXCLUSIVE NOR/OR GATE USING A CMOS CIRCUIT
- Publication number 20210167781
- Publication date Jun 3, 2021
- Samsung Electronics Co., Ltd.
- Hareharan Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCKLESS DELAY ADAPTATION LOOP FOR RANDOM DATA
- Publication number 20210152165
- Publication date May 20, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Abishek MANIAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
- Publication number 20210124559
- Publication date Apr 29, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING COMPLEM...
- Publication number 20200403616
- Publication date Dec 24, 2020
- GSI TECHNOLOGY, INC.
- Lee-Lean SHU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data Compressor Logic Circuit
- Publication number 20200389181
- Publication date Dec 10, 2020
- ARM Limited
- Shardendu Shekhar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOGICAL OPERATIONS USING A LOGICAL OPERATION COMPONENT
- Publication number 20200388321
- Publication date Dec 10, 2020
- Micron Technology, Inc.
- Glen E. Hush
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COMPACT 3D STACKED-CFET ARCHITECTURE FOR COMPLEX LOGIC CELLS
- Publication number 20200381430
- Publication date Dec 3, 2020
- TOKYO ELECTRON LIMITED
- Lars Liebmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
THREE-PORT MEMORY CELL AND ARRAY FOR IN-MEMORY COMPUTING
- Publication number 20200342921
- Publication date Oct 29, 2020
- Marvell International Ltd.
- Zhewei Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCU...
- Publication number 20200235735
- Publication date Jul 23, 2020
- STC.UNM
- James Plusquellic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMICALLY WEIGHTED EXCLUSIVE OR GATE HAVING WEIGHTED OUTPUT SEGME...
- Publication number 20200177363
- Publication date Jun 4, 2020
- Kandou Labs SA
- Armin Tajalli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Data Compressor Logic Circuit
- Publication number 20200136643
- Publication date Apr 30, 2020
- ARM Limited
- Shardendu Shekhar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOGICAL OPERATIONS USING A LOGICAL OPERATION COMPONENT
- Publication number 20200075081
- Publication date Mar 5, 2020
- Micron Technology, Inc.
- Glen E. Hush
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Logic Gate Designs for 3D Monolithic Direct Stacked VTFET
- Publication number 20190326279
- Publication date Oct 24, 2019
- International Business Machines Corporation
- Chen Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND CIRCUIT FOR DE-BIASING PUF BITS
- Publication number 20190319810
- Publication date Oct 17, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Shih-Lien Linus Lu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods and Devices for Detecting Open and/or Shorts Circuits in ME...
- Publication number 20190273900
- Publication date Sep 5, 2019
- North Inc.
- Eric CHEVALLAZ
- G01 - MEASURING TESTING
Information Patent Application
DYNAMICALLY WEIGHTED EXCLUSIVE OR GATE HAVING WEIGHTED OUTPUT SEGME...
- Publication number 20190238308
- Publication date Aug 1, 2019
- Kandou Labs, SA
- Armin Tajalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR TUNABLE PRECISION OF DOT-PRODUCT ENGINE
- Publication number 20190205095
- Publication date Jul 4, 2019
- IMEC vzw
- Mohit Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH MULTIPLE MEMORY ARRAYS TO FACILITATE IN-MEMORY C...
- Publication number 20190205273
- Publication date Jul 4, 2019
- Jack KAVALIEROS
- G06 - COMPUTING CALCULATING COUNTING

using field-effect transistors

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Apparatus and method for generating low-density parity-check (LDPC)...

High-speed communication link with self-aligned scrambling

Data compressor logic circuit

Low-loss arithmetic circuit and operating method of the same

Static random-access memory (SRAM) compute in-memory integration

Fabrication of a majority logic gate having non-linear input capaci...

Dynamically weighted exclusive or gate having weighted output segme...

In-memory computing device supporting arithmetic operations

High-speed communication link with self-aligned scrambling

Logical operations using a logical operation component

Compact 3D stacked-CFET architecture for complex logic cells

Dynamically weighted exclusive or gate having weighted output segme...

Full adder cell with improved power efficiency

Method and system for providing a variation resistant magnetic junc...

Majority logic gate with non-linear input capacitors

Clockless delay adaptation loop for random data

Full adder cell with improved power efficiency

Three-input exclusive NOR/OR gate using a CMOS circuit

Processing method for applying analog dynamic circuit to digital te...

Level shifter circuit with intermediate power domain

Asynchronous polymorphic logic gate design

Methods and devices for detecting open and/or shorts circuits in ME...

Code word generating method, erroneous bit determining method, and...

Three-port memory cell and array for in-memory computing

Computational memory cell and processing array device using complem...

Positive feedback XOR/XNOR gate and low-delay hybrid logic adder

Clockless delay adaptation loop for random data

Radio frequency switching circuitry with reduced switching time

Method and circuit for de-biasing PUF bits

Systems and methods for leveraging path delay variations in a circu...

Patents Applicationslast 30 patents

STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS

APPARATUS AND METHOD WITH IN-MEMORY COMPUTING (IMC) PROCESSOR

Apparatus comprising a comparator circuit

APPARATUS AND METHOD FOR GENERATING LOW-DENSITY PARITY-CHECK (LDPC)...

DYNAMICALLY WEIGHTED EXCLUSIVE OR GATE HAVING WEIGHTED OUTPUT SEGME...

HIGH-SPEED COMMUNICATION LINK WITH SELF-ALIGNED SCRAMBLING

DATA MULTIPLEXER SINGLE PHASE FLIP-FLOP

LOW-LOSS ARITHMETIC CIRCUIT AND OPERATING METHOD OF THE SAME

DYNAMICALLY WEIGHTED EXCLUSIVE OR GATE HAVING WEIGHTED OUTPUT SEGME...

APPARATUS FOR GENERATING RANDOM DATA AND A METHOD THEREOF

IN-MEMORY COMPUTING DEVICE SUPPORTING ARITHMETIC OPERATIONS

Level Shifter Circuit with Intermediate Power Domain

THREE-INPUT EXCLUSIVE NOR/OR GATE USING A CMOS CIRCUIT

CLOCKLESS DELAY ADAPTATION LOOP FOR RANDOM DATA

FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY

COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING COMPLEM...

Data Compressor Logic Circuit

LOGICAL OPERATIONS USING A LOGICAL OPERATION COMPONENT

COMPACT 3D STACKED-CFET ARCHITECTURE FOR COMPLEX LOGIC CELLS

THREE-PORT MEMORY CELL AND ARRAY FOR IN-MEMORY COMPUTING

SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCU...

DYNAMICALLY WEIGHTED EXCLUSIVE OR GATE HAVING WEIGHTED OUTPUT SEGME...

Data Compressor Logic Circuit

LOGICAL OPERATIONS USING A LOGICAL OPERATION COMPONENT

Logic Gate Designs for 3D Monolithic Direct Stacked VTFET

METHOD AND CIRCUIT FOR DE-BIASING PUF BITS

Methods and Devices for Detecting Open and/or Shorts Circuits in ME...

DYNAMICALLY WEIGHTED EXCLUSIVE OR GATE HAVING WEIGHTED OUTPUT SEGME...

SYSTEM AND METHOD FOR TUNABLE PRECISION OF DOT-PRODUCT ENGINE

MEMORY DEVICE WITH MULTIPLE MEMORY ARRAYS TO FACILITATE IN-MEMORY C...