using selection between two conditionally calculated carry or sum values

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CPC
G06F7/507

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/507using selection between two conditionally calculated carry or sum values

Industries

Patents Grantslast 30 patents

Information Patent Grant
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Information Patent Grant
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Information Patent Grant
Split and duplicate ripple circuits
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Information Patent Grant
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Operation processing device, information processing device, and inf...
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Information Patent Grant
Domino full adder based on delayed gating positive feedback
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Information Patent Grant
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Information Patent Grant
Memristor-based dividers using memristors-as-drivers (MAD) gates
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- Issue date Mar 31, 2020
- Board of Regents, The University of Texas System
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Information Patent Grant
Apparatus and methods for vector operations
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Information Patent Grant
Apparatus and methods for vector operations
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Information Patent Grant
Apparatus and methods for vector operations
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- Cambricon Technologies Corporation Limited
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Information Patent Grant
Memristor-based multipliers using memristors-as-drivers (MAD) gates
- Patent number 10,558,431
- Issue date Feb 11, 2020
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memristor-based dividers using memristors-as-drivers (MAD) gates
- Patent number 10,447,271
- Issue date Oct 15, 2019
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memristor-based multipliers using memristors-as-drivers (MAD) gates
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- Issue date Jun 11, 2019
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memristor-based dividers using memristors-as-drivers (MAD) gates
- Patent number 10,305,484
- Issue date May 28, 2019
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memristor-based adders using memristors-as-drivers (MAD) gates
- Patent number 9,971,564
- Issue date May 15, 2018
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memristor-based adders using memristors-as-drivers (MAD) gates
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- Issue date Mar 20, 2018
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for vector processing
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- Issue date Mar 13, 2018
- ARM Limited
- David Raymond Lutz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Exponent monitoring
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- Issue date Feb 6, 2018
- ARM Limited
- Guy Larri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Lookup table sharing for memory-based computing
- Patent number 9,851,743
- Issue date Dec 26, 2017
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder capable of supporting addition and subtraction of up to n-bit...
- Patent number 9,842,085
- Issue date Dec 12, 2017
- Samsung Electronics Co., Ltd.
- Hyeong-Seok Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for performing conversion operation
- Patent number 9,778,906
- Issue date Oct 3, 2017
- ARM Limited
- David Raymond Lutz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Vector operands with component representing different significance...
- Patent number 9,766,858
- Issue date Sep 19, 2017
- ARM Limited
- David Raymond Lutz
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

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METHOD AND APPARATUS FOR OPERATING MEMORY PROCESSOR
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FLOATING POINT FUSED MULTIPLY ADD WITH REDUCED 1'S COMPLEMENT DELAY
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SPLIT AND DUPLICATE RIPPLE CIRCUITS
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- Publication date Jan 26, 2023
- Micron Technology, Inc.
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ARITHMETIC LOGIC UNIT DESIGN IN COLUMN ANALOG TO DIGITAL CONVERTER...
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ARITHMETIC PROCESSING DEVICE
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Systems and Methods for Low Latency Modular Multiplication
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DOMINO FULL ADDER BASED ON DELAYED GATING POSITIVE FEEDBACK
- Publication number 20210109710
- Publication date Apr 15, 2021
- Ningbo University
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Information Patent Application
MEMRISTOR-BASED DIVIDERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES
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- Board of Regents, The University of Texas System
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OPERATION PROCESSING DEVICE, INFORMATION PROCESSING DEVICE, AND INF...
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MEMRISTOR-BASED MULTIPLIERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES
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MEMRISTOR-BASED DIVIDERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES
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LOOKUP TABLE SHARING FOR MEMORY-BASED COMPUTING
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HYBRID ADDER USING DYNAMIC AND STATIC CIRCUITS
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LIST STRUCTURE CONTROL CIRCUIT
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CARRY-SELECT ADDER
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Information Patent Application
METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHME...
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- International Business Machines Corporation
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using selection between two conditionally calculated carry or sum values

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Systems and methods for low latency modular multiplication

Secure multi-party computation and communication

Secure multi-party computation and communication

Split and duplicate ripple circuits

Arithmetic logic unit design in column analog to digital converter...

Apparatus and methods for vector operations

Apparatus and methods for vector operations

Split and duplicate ripple circuits

Apparatus and methods for vector operations

Extendable multiple-digit base-2n in-memory adder device

Operation processing device, information processing device, and inf...

Apparatus and methods for vector operations

Domino full adder based on delayed gating positive feedback

Apparatus and methods for vector operations

Memristor-based dividers using memristors-as-drivers (MAD) gates

Apparatus and methods for vector operations

Apparatus and methods for vector operations

Apparatus and methods for vector operations

Memristor-based multipliers using memristors-as-drivers (MAD) gates

Memristor-based dividers using memristors-as-drivers (MAD) gates

Memristor-based multipliers using memristors-as-drivers (MAD) gates

Memristor-based dividers using memristors-as-drivers (MAD) gates

Memristor-based adders using memristors-as-drivers (MAD) gates

Memristor-based adders using memristors-as-drivers (MAD) gates

Apparatus and method for vector processing

Exponent monitoring

Lookup table sharing for memory-based computing

Adder capable of supporting addition and subtraction of up to n-bit...

Apparatus and method for performing conversion operation

Vector operands with component representing different significance...

Patents Applicationslast 30 patents

SIGNED EXTENSION CARRY-LOOK-AHEAD FOR ACCUMULATOR WITH BIT WIDTH DI...

METHOD AND APPARATUS FOR OPERATING MEMORY PROCESSOR

ADDER WITH FIRST AND SECOND ADDER CIRCUITS FOR NON-POWER OF TWO INP...

FLOATING POINT FUSED MULTIPLY ADD WITH REDUCED 1'S COMPLEMENT DELAY

PARALLEL COMPUTATION OF A LOGIC OPERATION, INCREMENT, AND DECREMENT...

SPLIT AND DUPLICATE RIPPLE CIRCUITS

ARITHMETIC LOGIC UNIT DESIGN IN COLUMN ANALOG TO DIGITAL CONVERTER...

ARITHMETIC PROCESSING DEVICE

Systems and Methods for Low Latency Modular Multiplication

DOMINO FULL ADDER BASED ON DELAYED GATING POSITIVE FEEDBACK

MEMRISTOR-BASED DIVIDERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES

OPERATION PROCESSING DEVICE, INFORMATION PROCESSING DEVICE, AND INF...

MEMRISTOR-BASED MULTIPLIERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES

MEMRISTOR-BASED DIVIDERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES

MEMRISTOR-BASED MULTIPLIERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES

MEMRISTOR-BASED DIVIDERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES

LOOKUP TABLE SHARING FOR MEMORY-BASED COMPUTING

BINARY ADDER AND MULTIPLIER CIRCUIT

ADDER CAPABLE OF SUPPORTING ADDITION AND SUBTRACTION OF UP TO N-BIT...

HYBRID ADDER USING DYNAMIC AND STATIC CIRCUITS

LIST STRUCTURE CONTROL CIRCUIT

M-BIT RACE DELAY ADDER AND METHOD OF OPERATION

STATIC LOGIC LING ADDER

CONFIGURABLE HYBRID ADDER CIRCUITRY

Address generating circuit and semiconductor memory device

METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHME...

System and Method for Providing a Double Adder for Decimal Floating...

CARRY-SELECT ADDER

METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHME...

Carry-Select Adder Structure and Method to Generate Orthogonal Sign...