using table look-up using programmable logic arrays

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/5057using table look-up using programmable logic arrays

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Patents Grantslast 30 patents

Information Patent Grant
Surface code computations using Auto-CCZ quantum states
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- Issue date Apr 23, 2024
- Google LLC
- Craig Gidney
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Information Patent Grant
Determining sums using logic circuits
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- Issue date Aug 1, 2023
- SUPERFASTFPGA LIMITED
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Information Patent Grant
Oblivious carry runway registers for performing piecewise additions
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- Issue date Jul 25, 2023
- Google LLC
- Craig Gidney
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Information Patent Grant
Logarithmic addition-accumulator circuitry, processing pipeline inc...
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- Issue date Jul 4, 2023
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- Frederick A. Ware
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Information Patent Grant
In-memory arithmetic processors
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- FlashSilicon Incorporation
- Lee Wang
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Measurement based uncomputation for quantum circuit optimization
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- Issue date Apr 25, 2023
- Google LLC
- Craig Gidney
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Information Patent Grant
Quantum circuit optimization using windowed quantum arithmetic
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- Issue date Feb 21, 2023
- Google LLC
- Craig Gidney
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Information Patent Grant
Surface code computations using auto-CCZ quantum states
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- Issue date Jan 31, 2023
- Google LLC
- Craig Gidney
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Information Patent Grant
Measurement based uncomputation for quantum circuit optimization
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- Issue date Dec 20, 2022
- Google LLC
- Craig Gidney
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Information Patent Grant
Oblivious carry runway registers for performing piecewise additions
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- Issue date Oct 18, 2022
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Information Patent Grant
Integer and characters prefix based methodologies combined with par...
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- Issue date Jun 7, 2022
- Khalid Omar Thabit
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Information Patent Grant
Real time configuration of multiple true random number generator so...
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- International Business Machines Corporation
- Kirk David Lamb
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Information Patent Grant
Measurement based uncomputation for quantum circuit optimization
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- Issue date Jun 8, 2021
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Information Patent Grant
Efficient FPGA multipliers
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Selectable peripheral logic in programmable apparatus
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- Issue date Jun 2, 2020
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- Yutaka Kawai
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Information Patent Grant
Selectable peripheral logic in programmable apparatus
- Patent number 10,599,599
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Yutaka Kawai
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Information Patent Grant
Selectable peripheral logic in programmable apparatus
- Patent number 10,540,310
- Issue date Jan 21, 2020
- International Business Machines Corporation
- Yutaka Kawai
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Information Patent Grant
Selectable peripheral logic in programmable apparatus
- Patent number 10,311,002
- Issue date Jun 4, 2019
- International Business Machines Corporation
- Yutaka Kawai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable peripheral logic in programmable apparatus
- Patent number 10,061,731
- Issue date Aug 28, 2018
- International Business Machines Corporation
- Yutaka Kawai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques and devices for performing arithmetic
- Patent number 9,916,131
- Issue date Mar 13, 2018
- The Penn State Research Foundation
- Eugene George Walters
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lookup table sharing for memory-based computing
- Patent number 9,851,743
- Issue date Dec 26, 2017
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lookup table sharing for memory-based computing
- Patent number 9,760,110
- Issue date Sep 12, 2017
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lookup table sharing for memory-based computing
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- Issue date Apr 5, 2016
- International Business Machines Corporation
- Minsik Cho
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Information Patent Grant
Lookup table sharing for memory-based computing
- Patent number 9,304,972
- Issue date Apr 5, 2016
- International Business Machines Corporation
- Minsik Cho
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Information Patent Grant
Look up table (LUT) structure supporting exclusive OR (XOR) circuit...
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- Issue date Apr 29, 2014
- Altera Corporation
- Martin Langhammer
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Information Patent Grant
Operation unit and program
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- Issue date Jan 14, 2014
- Kabushiki Kaisha Toshiba
- Masanobu Koike
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Iterative carrier phase compensation in coherent fiber optic receivers
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- Issue date Jul 30, 2013
- Mitsubishi Electric Research Laboratories, Inc.
- Chunjie Duan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Secure multi-party computation of normalized sum-type functions
- Patent number 8,473,537
- Issue date Jun 25, 2013
- Mitsubishi Electric Research Laboratories, Inc.
- Shantanu Rane
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Look up table (LUT) structure supporting exclusive or (XOR) circuit...
- Patent number 8,447,798
- Issue date May 21, 2013
- Altera Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for decoding graph-based codes using message-pass...
- Patent number 8,407,550
- Issue date Mar 26, 2013
- Mitsubishi Electric Research Laboratories, Inc.
- Jonathan S. Yedidia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
CONSTANT MODULO VIA RECIRCULANT REDUCTION
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- Publication date Apr 25, 2024
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- Theo Drane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS
- Publication number 20240020560
- Publication date Jan 18, 2024
- Google LLC
- Craig Gidney
- G06 - COMPUTING CALCULATING COUNTING
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QUANTUM CIRCUIT OPTIMIZATION USING WINDOWED QUANTUM ARITHMETIC
- Publication number 20230281497
- Publication date Sep 7, 2023
- Google LLC
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- G06 - COMPUTING CALCULATING COUNTING
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MEASUREMENT BASED UNCOMPUTATION FOR QUANTUM CIRCUIT OPTIMIZATION
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Embedded Arithmetic Blocks for Structured ASICs
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- Publication date Jun 22, 2023
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PARALLEL COMPUTATION OF A LOGIC OPERATION, INCREMENT, AND DECREMENT...
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SURFACE CODE COMPUTATIONS USING AUTO-CCZ QUANTUM STATES
- Publication number 20230177373
- Publication date Jun 8, 2023
- Google LLC
- Craig Gidney
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OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS
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- Publication date May 25, 2023
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MEASUREMENT BASED UNCOMPUTATION FOR QUANTUM CIRCUIT OPTIMIZATION
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Measurement Based Uncomputation for Quantum Circuit Optimization
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- Publication date Sep 23, 2021
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REAL TIME CONFIGURATION OF MULTIPLE TRUE RANDOM NUMBER GENERATOR SO...
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- International Business Machines Corporation
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Logarithmic Addition-Accumulator Circuitry, Processing Pipeline inc...
- Publication number 20210173617
- Publication date Jun 10, 2021
- Flex Logix Technologies, Inc.
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Information Patent Application
QUANTUM CIRCUIT OPTIMIZATION USING WINDOWED QUANTUM ARITHMETIC
- Publication number 20200311592
- Publication date Oct 1, 2020
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SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS
- Publication number 20190251053
- Publication date Aug 15, 2019
- International Business Machines Corporation
- Yutaka Kawai
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Information Patent Application
SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS
- Publication number 20190220432
- Publication date Jul 18, 2019
- International Business Machines Corporation
- Yutaka Kawai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS
- Publication number 20190220433
- Publication date Jul 18, 2019
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Information Patent Application
SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS
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TECHNIQUES AND DEVICES FOR PERFORMING ARITHMETIC
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- The Penn State Research Foundation
- Eugene George Walters
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DEVICE WITH LOGIC CIRCUITRY SUPPORTING QUATERNARY ADDITION
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- Publication date Nov 21, 2013
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- Martin Langhammer
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Information Patent Application
OPERATION UNIT AND PROGRAM
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- Masanobu Koike
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Information Patent Application
LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS
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- Publication date Sep 29, 2011
- Altera Corporation
- Martin Langhammer
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Information Patent Application
Iterative Carrier Phase Compensation in Coherent Fiber Optic Receivers
- Publication number 20110129234
- Publication date Jun 2, 2011
- Chunjie Duan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure Multi-Party Computation of Normalized Sum-Type Functions
- Publication number 20110040820
- Publication date Feb 17, 2011
- Shantanu Rane
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Information Patent Application
Method and System for Decoding Graph-Based Codes Using Message-Pass...
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Information Patent Application
Method and System for Decoding Graph-Based Codes Using Message-Pass...
- Publication number 20110041033
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Information Patent Application
MEMORY BASED COMPUTATION SYSTEMS AND METHODS FOR HIGH PERFORMANCE A...
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- Toshiba America Research, Inc.
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Information Patent Application
N-bit constant adder/subtractor
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- STMicroelectronics Pvt. Ltd.
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- G06 - COMPUTING CALCULATING COUNTING

using table look-up using programmable logic arrays

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Surface code computations using Auto-CCZ quantum states

Determining sums using logic circuits

Oblivious carry runway registers for performing piecewise additions

Logarithmic addition-accumulator circuitry, processing pipeline inc...

In-memory arithmetic processors

Measurement based uncomputation for quantum circuit optimization

Quantum circuit optimization using windowed quantum arithmetic

Surface code computations using auto-CCZ quantum states

Measurement based uncomputation for quantum circuit optimization

Oblivious carry runway registers for performing piecewise additions

Integer and characters prefix based methodologies combined with par...

Real time configuration of multiple true random number generator so...

Measurement based uncomputation for quantum circuit optimization

Efficient FPGA multipliers

Selectable peripheral logic in programmable apparatus

Selectable peripheral logic in programmable apparatus

Selectable peripheral logic in programmable apparatus

Selectable peripheral logic in programmable apparatus

Selectable peripheral logic in programmable apparatus

Techniques and devices for performing arithmetic

Lookup table sharing for memory-based computing

Lookup table sharing for memory-based computing

Lookup table sharing for memory-based computing

Lookup table sharing for memory-based computing

Look up table (LUT) structure supporting exclusive OR (XOR) circuit...

Operation unit and program

Iterative carrier phase compensation in coherent fiber optic receivers

Secure multi-party computation of normalized sum-type functions

Look up table (LUT) structure supporting exclusive or (XOR) circuit...

Method and system for decoding graph-based codes using message-pass...

Patents Applicationslast 30 patents

CONSTANT MODULO VIA RECIRCULANT REDUCTION

OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS

QUANTUM CIRCUIT OPTIMIZATION USING WINDOWED QUANTUM ARITHMETIC

MEASUREMENT BASED UNCOMPUTATION FOR QUANTUM CIRCUIT OPTIMIZATION

Embedded Arithmetic Blocks for Structured ASICs

PARALLEL COMPUTATION OF A LOGIC OPERATION, INCREMENT, AND DECREMENT...

SURFACE CODE COMPUTATIONS USING AUTO-CCZ QUANTUM STATES

OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS

MEASUREMENT BASED UNCOMPUTATION FOR QUANTUM CIRCUIT OPTIMIZATION

Measurement Based Uncomputation for Quantum Circuit Optimization

REAL TIME CONFIGURATION OF MULTIPLE TRUE RANDOM NUMBER GENERATOR SO...

Logarithmic Addition-Accumulator Circuitry, Processing Pipeline inc...

QUANTUM CIRCUIT OPTIMIZATION USING WINDOWED QUANTUM ARITHMETIC

SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS

SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS

SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS

SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS

TECHNIQUES AND DEVICES FOR PERFORMING ARITHMETIC

DEVICE WITH LOGIC CIRCUITRY SUPPORTING QUATERNARY ADDITION

OPERATION UNIT AND PROGRAM

LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS

Iterative Carrier Phase Compensation in Coherent Fiber Optic Receivers

Secure Multi-Party Computation of Normalized Sum-Type Functions

Method and System for Decoding Graph-Based Codes Using Message-Pass...

Method and System for Decoding Graph-Based Codes Using Message-Pass...

MEMORY BASED COMPUTATION SYSTEMS AND METHODS FOR HIGH PERFORMANCE A...

N-bit constant adder/subtractor