using table look-up using programmable logic arrays

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/5057using table look-up using programmable logic arrays

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Patents Grantslast 30 patents

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Determining sums using logic circuits
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Oblivious carry runway registers for performing piecewise additions
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In-memory arithmetic processors
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Quantum circuit optimization using windowed quantum arithmetic
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Surface code computations using auto-CCZ quantum states
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Measurement based uncomputation for quantum circuit optimization
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Oblivious carry runway registers for performing piecewise additions
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Real time configuration of multiple true random number generator so...
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Efficient FPGA multipliers
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Selectable peripheral logic in programmable apparatus
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Selectable peripheral logic in programmable apparatus
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Selectable peripheral logic in programmable apparatus
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Selectable peripheral logic in programmable apparatus
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Information Patent Grant
Selectable peripheral logic in programmable apparatus
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- International Business Machines Corporation
- Yutaka Kawai
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Information Patent Grant
Techniques and devices for performing arithmetic
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- Issue date Mar 13, 2018
- The Penn State Research Foundation
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Information Patent Grant
Lookup table sharing for memory-based computing
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Lookup table sharing for memory-based computing
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Lookup table sharing for memory-based computing
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Information Patent Grant
Lookup table sharing for memory-based computing
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Information Patent Grant
Look up table (LUT) structure supporting exclusive OR (XOR) circuit...
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Operation unit and program
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Iterative carrier phase compensation in coherent fiber optic receivers
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- Chunjie Duan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Secure multi-party computation of normalized sum-type functions
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- Issue date Jun 25, 2013
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- Shantanu Rane
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Look up table (LUT) structure supporting exclusive or (XOR) circuit...
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Information Patent Grant
Method and system for decoding graph-based codes using message-pass...
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- Issue date Mar 26, 2013
- Mitsubishi Electric Research Laboratories, Inc.
- Jonathan S. Yedidia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

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CONSTANT MODULO VIA RECIRCULANT REDUCTION
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MEASUREMENT BASED UNCOMPUTATION FOR QUANTUM CIRCUIT OPTIMIZATION
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OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS
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REAL TIME CONFIGURATION OF MULTIPLE TRUE RANDOM NUMBER GENERATOR SO...
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SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS
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SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS
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SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS
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LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS
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Iterative Carrier Phase Compensation in Coherent Fiber Optic Receivers
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Secure Multi-Party Computation of Normalized Sum-Type Functions
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N-bit constant adder/subtractor
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using table look-up using programmable logic arrays

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Surface code computations using Auto-CCZ quantum states

Determining sums using logic circuits

Oblivious carry runway registers for performing piecewise additions

Logarithmic addition-accumulator circuitry, processing pipeline inc...

In-memory arithmetic processors

Measurement based uncomputation for quantum circuit optimization

Quantum circuit optimization using windowed quantum arithmetic

Surface code computations using auto-CCZ quantum states

Measurement based uncomputation for quantum circuit optimization

Oblivious carry runway registers for performing piecewise additions

Integer and characters prefix based methodologies combined with par...

Real time configuration of multiple true random number generator so...

Measurement based uncomputation for quantum circuit optimization

Efficient FPGA multipliers

Selectable peripheral logic in programmable apparatus

Selectable peripheral logic in programmable apparatus

Selectable peripheral logic in programmable apparatus

Selectable peripheral logic in programmable apparatus

Selectable peripheral logic in programmable apparatus

Techniques and devices for performing arithmetic

Lookup table sharing for memory-based computing

Lookup table sharing for memory-based computing

Lookup table sharing for memory-based computing

Lookup table sharing for memory-based computing

Look up table (LUT) structure supporting exclusive OR (XOR) circuit...

Operation unit and program

Iterative carrier phase compensation in coherent fiber optic receivers

Secure multi-party computation of normalized sum-type functions

Look up table (LUT) structure supporting exclusive or (XOR) circuit...

Method and system for decoding graph-based codes using message-pass...

Patents Applicationslast 30 patents

OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS

CONSTANT MODULO VIA RECIRCULANT REDUCTION

OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS

QUANTUM CIRCUIT OPTIMIZATION USING WINDOWED QUANTUM ARITHMETIC

MEASUREMENT BASED UNCOMPUTATION FOR QUANTUM CIRCUIT OPTIMIZATION

Embedded Arithmetic Blocks for Structured ASICs

PARALLEL COMPUTATION OF A LOGIC OPERATION, INCREMENT, AND DECREMENT...

SURFACE CODE COMPUTATIONS USING AUTO-CCZ QUANTUM STATES

OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS

MEASUREMENT BASED UNCOMPUTATION FOR QUANTUM CIRCUIT OPTIMIZATION

Measurement Based Uncomputation for Quantum Circuit Optimization

REAL TIME CONFIGURATION OF MULTIPLE TRUE RANDOM NUMBER GENERATOR SO...

Logarithmic Addition-Accumulator Circuitry, Processing Pipeline inc...

QUANTUM CIRCUIT OPTIMIZATION USING WINDOWED QUANTUM ARITHMETIC

SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS

SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS

SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS

SELECTABLE PERIPHERAL LOGIC IN PROGRAMMABLE APPARATUS

TECHNIQUES AND DEVICES FOR PERFORMING ARITHMETIC

DEVICE WITH LOGIC CIRCUITRY SUPPORTING QUATERNARY ADDITION

OPERATION UNIT AND PROGRAM

LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS

Iterative Carrier Phase Compensation in Coherent Fiber Optic Receivers

Secure Multi-Party Computation of Normalized Sum-Type Functions

Method and System for Decoding Graph-Based Codes Using Message-Pass...

Method and System for Decoding Graph-Based Codes Using Message-Pass...

MEMORY BASED COMPUTATION SYSTEMS AND METHODS FOR HIGH PERFORMANCE A...

N-bit constant adder/subtractor