using trapping sets

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CPC
H03M13/1142

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HELECTRICITY H03Electronic circuits H03MCODING DECODING CODE CONVERSION IN GENERAL H03M13/00Coding, decoding or code conversion, for error detection or error correction Coding theory basic assumptions Coding bounds Error probability evaluation methods Channel models Simulation or testing of codes

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H03M13/1142using trapping sets

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Methods and systems of stall mitigation in iterative decoders
- Patent number 11,689,217
- Issue date Jun 27, 2023
- Micron Technology, Inc.
- Mustafa N. Kaynak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel bit interleaver
- Patent number 11,362,680
- Issue date Jun 14, 2022
- Panasonic Holdings Corporation
- Mihail Petrov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error correction circuit and operating method thereof
- Patent number 11,239,865
- Issue date Feb 1, 2022
- SK hynix Inc.
- Jang Seob Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating an LDPC code with a required er...
- Patent number 11,218,168
- Issue date Jan 4, 2022
- Silicon Motion, Inc.
- Shiuan-Hao Kuo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel bit interleaver
- Patent number 10,886,946
- Issue date Jan 5, 2021
- Panasonic Corporation
- Mihail Petrov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error correction circuit and operating method thereof
- Patent number 10,790,859
- Issue date Sep 29, 2020
- SKY hynix Inc.
- Jang Seob Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refresh, run, aggregate decoder recovery
- Patent number 10,707,900
- Issue date Jul 7, 2020
- Seagate Technology LLC
- Sundararajan Sankaranarayanan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mitigation of error correction failure due to trapping sets
- Patent number 10,666,295
- Issue date May 26, 2020
- Seagate Technology LLC
- Ludovic Danjean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Priori information based post-processing in low-density parity-chec...
- Patent number 10,396,817
- Issue date Aug 27, 2019
- Seagate Technology LLC
- Zhengang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel bit interleaver
- Patent number 10,361,726
- Issue date Jul 23, 2019
- Panasonic Corporation
- Mihail Petrov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Refresh, run, aggregate decoder recovery
- Patent number 10,298,263
- Issue date May 21, 2019
- Seagate Technology LLC
- Sundararajan Sankaranarayanan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mitigation of error correction failure due to trapping sets
- Patent number 10,177,787
- Issue date Jan 8, 2019
- Seagate Technology LLC
- Ludovic Danjean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
LDPC post-processor architecture and method for low error floor con...
- Patent number 10,148,288
- Issue date Dec 4, 2018
- Texas Instruments Incorporated
- Yaoyu Tao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-density parity-check apparatus and matrix trapping set breaking...
- Patent number 10,141,953
- Issue date Nov 27, 2018
- Via Technologies, Inc.
- Ying Yu Tai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transmission device, reception device, transmission method, and rec...
- Patent number 10,097,205
- Issue date Oct 9, 2018
- SUN PATENT TRUST
- Shutai Okamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
GLDPC soft decoding with hard decision inputs
- Patent number 10,084,481
- Issue date Sep 25, 2018
- Apple Inc.
- Naftali Sommer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for enhanced data recovery in a solid state mem...
- Patent number 9,996,416
- Issue date Jun 12, 2018
- Seagate Technology LLC
- Haitao Xia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
LDPC post-processor architecture and method for low error floor con...
- Patent number 9,793,923
- Issue date Oct 17, 2017
- Texas Instruments Incorporated
- Yaoyu Tao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error correction code decoder with stochastic floor mitigation
- Patent number 9,564,922
- Issue date Feb 7, 2017
- Microsemi Storage Solutions (U.S.), Inc.
- Peter Graumann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel bit interleaver
- Patent number 9,515,681
- Issue date Dec 6, 2016
- Panasonic Corporation
- Mihail Petrov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data decoder with trapping set flip bit mapper
- Patent number 9,459,956
- Issue date Oct 4, 2016
- Seagate Technology LLC
- Alexander Hubris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for enhanced data recovery in a solid state mem...
- Patent number 9,448,882
- Issue date Sep 20, 2016
- Seagate Technology LLC
- Haitao Xia
- G11 - INFORMATION STORAGE
Information Patent Grant
Error-correction decoding with conditional limiting of check-node m...
- Patent number 9,407,290
- Issue date Aug 2, 2016
- SanDisk Technologies LLC
- Omer Fainzilber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for error recovery in memory systems employin...
- Patent number 9,397,698
- Issue date Jul 19, 2016
- Marvell International Ltd.
- Gregory Burd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel bit interleaver
- Patent number 9,319,072
- Issue date Apr 19, 2016
- Panasonic Corporation
- Mihail Petrov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Detection/erasure of random write errors using converged hard decis...
- Patent number 9,298,547
- Issue date Mar 29, 2016
- Seagate Technology LLC
- Abdel-Hakim S. Alhussien
- G11 - INFORMATION STORAGE
Information Patent Grant
Test signal generator for low-density parity-check decoder
- Patent number 9,294,128
- Issue date Mar 22, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Denis Vladimirovich Zaytsev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for skip layer data decoding
- Patent number 9,214,959
- Issue date Dec 15, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Shaohua Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive calibration of noise predictive finite impulse response fi...
- Patent number 9,202,519
- Issue date Dec 1, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Bruce A. Wilson
- G11 - INFORMATION STORAGE
Information Patent Grant
Resolving trapping sets
- Patent number 9,170,877
- Issue date Oct 27, 2015
- Micron Technology, Inc.
- Chandra C. Varanasi
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PARALLEL BIT INTERLEAVER
- Publication number 20220263523
- Publication date Aug 18, 2022
- Panasonic Holdings Corporation
- Mihail PETROV
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PARALLEL BIT INTERLEAVER
- Publication number 20210083692
- Publication date Mar 18, 2021
- PANASONIC CORPORATION
- Mihail PETROV
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ERROR CORRECTION CIRCUIT AND OPERATING METHOD THEREOF
- Publication number 20210058099
- Publication date Feb 25, 2021
- SK HYNIX INC.
- Jang Seob Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL BIT INTERLEAVER
- Publication number 20190296772
- Publication date Sep 26, 2019
- PANASONIC CORPORATION
- Mihail PETROV
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
REFRESH, RUN, AGGREGATE DECODER RECOVERY
- Publication number 20190245557
- Publication date Aug 8, 2019
- SEAGATE TECHNOLOGY LLC
- Sundarajan Sankaranarayanan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LDPC Post-Processor Architecture and Method for Low Error Floor Con...
- Publication number 20170353194
- Publication date Dec 7, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Yaoyu Tao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LDPC POST-PROCESSOR ARCHITECTURE AND METHOD FOR LOW ERROR FLOOR CON...
- Publication number 20170149446
- Publication date May 25, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Yaoyu Tao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Priori Information Based Post-Processing in Low-Density Parity-Chec...
- Publication number 20170085277
- Publication date Mar 23, 2017
- Seagate Technology LLC
- Zhengang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD
- Publication number 20150222291
- Publication date Aug 6, 2015
- KABUSHIKI KAISHA TOSHIBA
- Naoaki KOKUBUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR-CORRECTION DECODING WITH CONDITIONAL LIMITING OF CHECK-NODE M...
- Publication number 20140281785
- Publication date Sep 18, 2014
- Omer Fainzilber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Test Signal Generator for Low-Density Parity-Check Decoder
- Publication number 20140245086
- Publication date Aug 28, 2014
- LSI Corporation
- Denis Vladimirovich Zaytsev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems and Methods for Skip Layer Data Decoding
- Publication number 20140237314
- Publication date Aug 21, 2014
- LSI Corporation
- Shaohua Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods for Trapping Set Disruption
- Publication number 20140237313
- Publication date Aug 21, 2014
- LSI Corporation
- Chung-Li Wang
- G11 - INFORMATION STORAGE
Information Patent Application
RESOLVING TRAPPING SETS
- Publication number 20140201595
- Publication date Jul 17, 2014
- Micron Technology, Inc.
- Chandra C. Varanasi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Majority-Tabular Post Processing of Quasi-Cyclic Low-Density Parity...
- Publication number 20140181624
- Publication date Jun 26, 2014
- LSI Corporation
- Alexander S. Podkolzin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Density Parity Check Decoder With Miscorrection Handling
- Publication number 20140164866
- Publication date Jun 12, 2014
- LSI Corporation
- Anatoli A. Bolotov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EVALUATION OF PERFORMANCE CHARACTERISTICS OF A READ CHANNEL
- Publication number 20140129898
- Publication date May 8, 2014
- Aleksey Alexandrovich Letunovskiy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PARALLEL BIT INTERLEAVER
- Publication number 20140129895
- Publication date May 8, 2014
- PANASONIC CORPORATION
- Mihail Petrov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TRAPPING-SET DATABASE FOR A LOW-DENSITY PARITY-CHECK DECODER
- Publication number 20140122960
- Publication date May 1, 2014
- Pavel Aleksandrovich Aliseychik
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems and Methods for Enhanced Local Iteration Randomization in a...
- Publication number 20140108880
- Publication date Apr 17, 2014
- LSI Corporation
- Fan Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Efficient Way to Construct LDPC Code by Comparing Error Events Usin...
- Publication number 20140095955
- Publication date Apr 3, 2014
- LSI Corporation
- Denis Vladimirovich Zaytsev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LDPC Decoder With Dynamic Graph Modification
- Publication number 20140082448
- Publication date Mar 20, 2014
- Fan Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems and Methods for Detector Side Trapping Set Mitigation
- Publication number 20140082461
- Publication date Mar 20, 2014
- LSI CORP.
- Fan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LDPC Decoder Trapping Set Identification
- Publication number 20140068367
- Publication date Mar 6, 2014
- LSI CORPORATION
- Fan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESOLVING TRAPPING SETS
- Publication number 20140019824
- Publication date Jan 16, 2014
- Micron Technology, Inc.
- Chandra C. Varanasi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR BREAKING TRAPPING SETS
- Publication number 20130343495
- Publication date Dec 26, 2013
- LSI Corporation
- Yang Han
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Error Injection for LDPC Retry Validation
- Publication number 20130326302
- Publication date Dec 5, 2013
- LSI CORPORATION
- Yang Han
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems and Methods for Data Decoder State Preservation During Exte...
- Publication number 20130290806
- Publication date Oct 31, 2013
- LSI CORPORATION
- Fan Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods for Multi-Pass Alternate Decoding
- Publication number 20130198584
- Publication date Aug 1, 2013
- LSI CORPORATION
- Fan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Ambiguity Based Decode Algorithm Modification
- Publication number 20130111290
- Publication date May 2, 2013
- LSI CORPORATION
- Fan Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY

using trapping sets

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and systems of stall mitigation in iterative decoders

Parallel bit interleaver

Error correction circuit and operating method thereof

Method and apparatus for generating an LDPC code with a required er...

Parallel bit interleaver

Error correction circuit and operating method thereof

Refresh, run, aggregate decoder recovery

Mitigation of error correction failure due to trapping sets

Priori information based post-processing in low-density parity-chec...

Parallel bit interleaver

Refresh, run, aggregate decoder recovery

Mitigation of error correction failure due to trapping sets

LDPC post-processor architecture and method for low error floor con...

Low-density parity-check apparatus and matrix trapping set breaking...

Transmission device, reception device, transmission method, and rec...

GLDPC soft decoding with hard decision inputs

Systems and methods for enhanced data recovery in a solid state mem...

LDPC post-processor architecture and method for low error floor con...

Error correction code decoder with stochastic floor mitigation

Parallel bit interleaver

Data decoder with trapping set flip bit mapper

Systems and methods for enhanced data recovery in a solid state mem...

Error-correction decoding with conditional limiting of check-node m...

Methods and apparatus for error recovery in memory systems employin...

Parallel bit interleaver

Detection/erasure of random write errors using converged hard decis...

Test signal generator for low-density parity-check decoder

Systems and methods for skip layer data decoding

Adaptive calibration of noise predictive finite impulse response fi...

Resolving trapping sets

Patents Applicationslast 30 patents

PARALLEL BIT INTERLEAVER

PARALLEL BIT INTERLEAVER

ERROR CORRECTION CIRCUIT AND OPERATING METHOD THEREOF

PARALLEL BIT INTERLEAVER

REFRESH, RUN, AGGREGATE DECODER RECOVERY

LDPC Post-Processor Architecture and Method for Low Error Floor Con...

LDPC POST-PROCESSOR ARCHITECTURE AND METHOD FOR LOW ERROR FLOOR CON...

Priori Information Based Post-Processing in Low-Density Parity-Chec...

MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD

ERROR-CORRECTION DECODING WITH CONDITIONAL LIMITING OF CHECK-NODE M...

Test Signal Generator for Low-Density Parity-Check Decoder

Systems and Methods for Skip Layer Data Decoding

Systems and Methods for Trapping Set Disruption

RESOLVING TRAPPING SETS

Majority-Tabular Post Processing of Quasi-Cyclic Low-Density Parity...

Low Density Parity Check Decoder With Miscorrection Handling

EVALUATION OF PERFORMANCE CHARACTERISTICS OF A READ CHANNEL

PARALLEL BIT INTERLEAVER

TRAPPING-SET DATABASE FOR A LOW-DENSITY PARITY-CHECK DECODER

Systems and Methods for Enhanced Local Iteration Randomization in a...

Efficient Way to Construct LDPC Code by Comparing Error Events Usin...

LDPC Decoder With Dynamic Graph Modification

Systems and Methods for Detector Side Trapping Set Mitigation

LDPC Decoder Trapping Set Identification

RESOLVING TRAPPING SETS

APPARATUS AND METHOD FOR BREAKING TRAPPING SETS

Error Injection for LDPC Retry Validation

Systems and Methods for Data Decoder State Preservation During Exte...

Systems and Methods for Multi-Pass Alternate Decoding

Systems and Methods for Ambiguity Based Decode Algorithm Modification