Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers

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H01L21/76267

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Current Industry

H01L21/76267Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers

Industries

Patents Grantslast 30 patents

Information Patent Grant
Cut-fin isolation regions and method forming same
- Patent number 12,237,416
- Issue date Feb 25, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming an oxide volume within a fin
- Patent number 12,224,202
- Issue date Feb 11, 2025
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation structure for separating different transistor regions on...
- Patent number 12,199,102
- Issue date Jan 14, 2025
- Infineon Technologies Austria AG
- Ling Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for preparing semiconductor device structure with multiple l...
- Patent number 11,842,921
- Issue date Dec 12, 2023
- NANYA TECHNOLOGY CORPORATION
- Yu-Han Hsueh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D semiconductor device and structure
- Patent number 11,791,222
- Issue date Oct 17, 2023
- Monolithic 3D Inc.
- Zvi Or-Bach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming an oxide volume within a fin
- Patent number 11,764,104
- Issue date Sep 19, 2023
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bulk substrates with a self-aligned buried polycrystalline layer
- Patent number 11,749,559
- Issue date Sep 5, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Steven M. Shank
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device structure with multiple liners and method for...
- Patent number 11,581,216
- Issue date Feb 14, 2023
- NANYA TECHNOLOGY CORPORATION
- Yu-Han Hsueh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bulk substrates with a self-aligned buried polycrystalline layer
- Patent number 11,527,432
- Issue date Dec 13, 2022
- GLOBALFOUNDRIES U.S. INC.
- Steven M. Shank
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming the semiconductor device
- Patent number 11,515,197
- Issue date Nov 29, 2022
- Taiwan Semiconductor Manufacturing Company Ltd.
- Shih-Wei Peng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cut-fin isolation regions and method forming same
- Patent number 11,171,236
- Issue date Nov 9, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shiang-Bau Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around (GAA) transistor and method of fabricating the same
- Patent number 11,101,361
- Issue date Aug 24, 2021
- United Microelectronics Corp.
- Zhaoyao Zhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and fabricating method of the same
- Patent number 11,075,233
- Issue date Jul 27, 2021
- Samsung Electronics Co., Ltd.
- Hoon Sung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bulk substrates with a self-aligned buried polycrystalline layer
- Patent number 10,832,940
- Issue date Nov 10, 2020
- GLOBALFOUNDRIES Inc.
- Steven M. Shank
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing a buried cavity structure
- Patent number 10,784,147
- Issue date Sep 22, 2020
- Infineon Technologies AG
- Ines Uhlig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrates with self-aligned buried dielectric and polycrystalline...
- Patent number 10,651,281
- Issue date May 12, 2020
- GLOBALFOUNDRIES Inc.
- Siva P. Adusumilli
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Device isolation
- Patent number 10,615,252
- Issue date Apr 7, 2020
- NXP USA, INC.
- Radu Mircea Secareanu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI device structures with doped regions providing charge sinking
- Patent number 10,593,754
- Issue date Mar 17, 2020
- GLOBALFOUNDRIES Inc.
- Jagar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation of semiconductor device with buried cavity
- Patent number 10,553,675
- Issue date Feb 4, 2020
- Infineon Technologies AG
- Sebastian Schmidt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical transistor with eDRAM
- Patent number 10,541,242
- Issue date Jan 21, 2020
- International Business Machines Corporation
- Alexander Reznicek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon island structure and method of fabricating same
- Patent number 10,490,441
- Issue date Nov 26, 2019
- NEXCHIP SEMICONDUCTOR CORPORATION
- Tiansong Pu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High speed waveguide integrated Ge-based photodiode design for sili...
- Patent number 10,418,274
- Issue date Sep 17, 2019
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sandeep Seema Saseendran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Engineering of ferroelectric materials in semiconductor devices by...
- Patent number 10,388,514
- Issue date Aug 20, 2019
- GLOBALFOUNDRIES Inc.
- Lars Mueller-Meskamp
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bulk substrates with a self-aligned buried polycrystalline layer
- Patent number 10,192,779
- Issue date Jan 29, 2019
- GLOBALFOUNDRIES Inc.
- Steven M. Shank
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Saucer-shaped isolation structures for semiconductor devices
- Patent number 10,074,716
- Issue date Sep 11, 2018
- SKYWORKS SOLUTIONS (HONG KONG) LIMITED
- Wai Tien Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation structures for semiconductor devices including trenches c...
- Patent number 9,905,640
- Issue date Feb 27, 2018
- SKYWORKS SOLUTIONS (HONG KONG) LIMITED
- Wai Tien Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrates with buried isolation layers and methods of formation th...
- Patent number 9,875,926
- Issue date Jan 23, 2018
- Infineon Technologies AG
- Iris Moder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact self-aligned implantation transistor edge resistor for SRAM...
- Patent number 9,773,808
- Issue date Sep 26, 2017
- Honeywell International Inc.
- Paul S. Fechner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Aspect ratio for semiconductor on insulator
- Patent number 9,716,030
- Issue date Jul 25, 2017
- International Business Machines Corporation
- Effendi Leobandung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for integrated circuits with cylindrical gate str...
- Patent number 9,673,060
- Issue date Jun 6, 2017
- Semiconductor Manufacturing International (Shanghai) Corporation
- De Yuan Xiao
- B82 - NANO-TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
Contact Structures for Dual-Thickness Active Area SOI FETS
- Publication number 20250063822
- Publication date Feb 20, 2025
- pSemi Corporation
- Jagar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON-ON-INSULATOR (SOI) STRUCTURES FOR CHARGE DAMAGE PROTECTION
- Publication number 20250063828
- Publication date Feb 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Te Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACK-GATE EFFECT CONTROL VIA DOPING
- Publication number 20250048691
- Publication date Feb 6, 2025
- Murata Manufacturing Co., Ltd.
- Kouassi Sebastien KOUASSI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL DIE SINGULATION USING BURIED SACRIFICIAL STRUCTURE
- Publication number 20250048714
- Publication date Feb 6, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Te Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED STRUCTURE WITH TRAP RICH REGIONS AND LOW RESISTIVITY REG...
- Publication number 20240162232
- Publication date May 16, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Vibhor JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL OXIDE SEMICONDUCTOR DEVICES AND INTEGRATION METHODS
- Publication number 20240128374
- Publication date Apr 18, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Shesh Mani Pandey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE WITH LATERALLY GRADED CHANNEL REGION
- Publication number 20240128322
- Publication date Apr 18, 2024
- GLOBALFOUNDRIES U.S. Inc.
- George R. MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
- Publication number 20240047460
- Publication date Feb 8, 2024
- Vanguard International Semiconductor Corporation
- Chih-Cherng Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING AN OXIDE VOLUME WITHIN A FIN
- Publication number 20230377947
- Publication date Nov 23, 2023
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION STRUCTURE FOR SEPARATING DIFFERENT TRANSISTOR REGIONS ON...
- Publication number 20230335560
- Publication date Oct 19, 2023
- Infineon Technologies Austria AG
- Ling Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D SEMICONDUCTOR DEVICE AND STRUCTURE
- Publication number 20230207398
- Publication date Jun 29, 2023
- Monolithic 3D Inc.
- Zvi Or-Bach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-VOLTAGE SEMICONDUCTOR DEVICE
- Publication number 20230140348
- Publication date May 4, 2023
- Infineon Technologies Austria AG
- Lars Müller-Meskamp
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-FINGER RF nFET HAVING BURIED STRESSOR LAYER AND ISOLATION TRE...
- Publication number 20230093111
- Publication date Mar 23, 2023
- Acorn Semi, LLC
- Paul A. Clifton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER
- Publication number 20230063731
- Publication date Mar 2, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Steven M. Shank
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH MULTIPLE L...
- Publication number 20220352011
- Publication date Nov 3, 2022
- NANYA TECHNOLOGY CORPORATION
- YU-HAN HSUEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE STRUCTURE WITH MULTIPLE LINERS AND METHOD FOR...
- Publication number 20220352009
- Publication date Nov 3, 2022
- NANYA TECHNOLOGY CORPORATION
- YU-HAN HSUEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING SEMICONDUCTOR DEVICE
- Publication number 20220336261
- Publication date Oct 20, 2022
- Taiwan Semiconductor Manufacturing company Ltd.
- SHIH-WEI PENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Cut-Fin Isolation Regions and Method Forming Same
- Publication number 20220059685
- Publication date Feb 24, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shiang-Bau Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER
- Publication number 20210074577
- Publication date Mar 11, 2021
- GLOBALFOUNDRIES INC.
- Steven M. Shank
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
- Publication number 20210013086
- Publication date Jan 14, 2021
- Taiwan Semiconductor Manufacturing company Ltd.
- SHIH-WEI PENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING AN OXIDE VOLUME WITHIN A FIN
- Publication number 20200411365
- Publication date Dec 31, 2020
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATES WITH SELF-ALIGNED BURIED DIELECTRIC AND POLYCRYSTALLINE...
- Publication number 20200176589
- Publication date Jun 4, 2020
- GLOBALFOUNDRIES Inc.
- Siva P. Adusumilli
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
DEVICE ISOLATION
- Publication number 20200044021
- Publication date Feb 6, 2020
- NXP USA, Inc.
- Radu Mircea Secareanu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Cut-Fin Isolation Regions and Method Forming Same
- Publication number 20200044070
- Publication date Feb 6, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shiang-Bau Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOI DEVICE STRUCTURES WITH DOPED REGIONS PROVIDING CHARGE SINKING
- Publication number 20200035785
- Publication date Jan 30, 2020
- GLOBALFOUNDRIES INC.
- Jagar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER
- Publication number 20190295881
- Publication date Sep 26, 2019
- GLOBALFOUNDRIES INC.
- Steven M. Shank
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENGINEERING OF FERROELECTRIC MATERIALS IN SEMICONDUCTOR DEVICES BY...
- Publication number 20190108998
- Publication date Apr 11, 2019
- GLOBALFOUNDRIES INC.
- Lars Mueller-Meskamp
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH SPEED WAVEGUIDE INTEGRATED GE-BASED PHOTODIODE DESIGN FOR SILI...
- Publication number 20190027398
- Publication date Jan 24, 2019
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sandeep Seema SASEENDRAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PRODUCING A BURIED CAVITY STRUCTURE
- Publication number 20190027399
- Publication date Jan 24, 2019
- INFINEON TECHNOLOGIES AG
- Ines Uhlig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Including Buried Cavity and Manufacturing Method
- Publication number 20180108675
- Publication date Apr 19, 2018
- INFINEON TECHNOLOGIES AG
- Sebastian Schmidt
- H01 - BASIC ELECTRIC ELEMENTS

Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Cut-fin isolation regions and method forming same

Forming an oxide volume within a fin

Isolation structure for separating different transistor regions on...

Method for preparing semiconductor device structure with multiple l...

3D semiconductor device and structure

Forming an oxide volume within a fin

Bulk substrates with a self-aligned buried polycrystalline layer

Semiconductor device structure with multiple liners and method for...

Bulk substrates with a self-aligned buried polycrystalline layer

Semiconductor device and method of forming the semiconductor device

Cut-fin isolation regions and method forming same

Gate-all-around (GAA) transistor and method of fabricating the same

Semiconductor device and fabricating method of the same

Bulk substrates with a self-aligned buried polycrystalline layer

Method for producing a buried cavity structure

Substrates with self-aligned buried dielectric and polycrystalline...

Device isolation

SOI device structures with doped regions providing charge sinking

Isolation of semiconductor device with buried cavity

Vertical transistor with eDRAM

Silicon island structure and method of fabricating same

High speed waveguide integrated Ge-based photodiode design for sili...

Engineering of ferroelectric materials in semiconductor devices by...

Bulk substrates with a self-aligned buried polycrystalline layer

Saucer-shaped isolation structures for semiconductor devices

Isolation structures for semiconductor devices including trenches c...

Substrates with buried isolation layers and methods of formation th...

Compact self-aligned implantation transistor edge resistor for SRAM...

Aspect ratio for semiconductor on insulator

System and method for integrated circuits with cylindrical gate str...

Patents Applicationslast 30 patents

Contact Structures for Dual-Thickness Active Area SOI FETS

SILICON-ON-INSULATOR (SOI) STRUCTURES FOR CHARGE DAMAGE PROTECTION

BACK-GATE EFFECT CONTROL VIA DOPING

WAFER-LEVEL DIE SINGULATION USING BURIED SACRIFICIAL STRUCTURE

INTEGRATED STRUCTURE WITH TRAP RICH REGIONS AND LOW RESISTIVITY REG...

METAL OXIDE SEMICONDUCTOR DEVICES AND INTEGRATION METHODS

DEVICE WITH LATERALLY GRADED CHANNEL REGION

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

FORMING AN OXIDE VOLUME WITHIN A FIN

ISOLATION STRUCTURE FOR SEPARATING DIFFERENT TRANSISTOR REGIONS ON...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

HIGH-VOLTAGE SEMICONDUCTOR DEVICE

MULTI-FINGER RF nFET HAVING BURIED STRESSOR LAYER AND ISOLATION TRE...

BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER

METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH MULTIPLE L...

SEMICONDUCTOR DEVICE STRUCTURE WITH MULTIPLE LINERS AND METHOD FOR...

METHOD OF FORMING SEMICONDUCTOR DEVICE

Cut-Fin Isolation Regions and Method Forming Same

BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

FORMING AN OXIDE VOLUME WITHIN A FIN

SUBSTRATES WITH SELF-ALIGNED BURIED DIELECTRIC AND POLYCRYSTALLINE...

DEVICE ISOLATION

Cut-Fin Isolation Regions and Method Forming Same

SOI DEVICE STRUCTURES WITH DOPED REGIONS PROVIDING CHARGE SINKING

BULK SUBSTRATES WITH A SELF-ALIGNED BURIED POLYCRYSTALLINE LAYER

ENGINEERING OF FERROELECTRIC MATERIALS IN SEMICONDUCTOR DEVICES BY...

HIGH SPEED WAVEGUIDE INTEGRATED GE-BASED PHOTODIODE DESIGN FOR SILI...

METHOD FOR PRODUCING A BURIED CAVITY STRUCTURE

Integrated Circuit Including Buried Cavity and Manufacturing Method