With bypass possibility

Industry

CPC
G06F2205/065

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2205/00Indexing scheme relating to group G06F5/00 Methods or arrangements for data conversion without changing the order or content of the data handled

Current Industry

G06F2205/065With bypass possibility

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Short duration serialization express queue
- Patent number 10,809,975
- Issue date Oct 20, 2020
- International Business Machines Corporation
- Gregg L. Liguori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bypass FIFO for multiple virtual channels
- Patent number 9,824,058
- Issue date Nov 21, 2017
- Cavium, Inc.
- Steven C. Barner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low latency first-in-first-out (FIFO) buffer
- Patent number 9,459,829
- Issue date Oct 4, 2016
- Marvell Israel (M.I.S.L) Ltd.
- Evgeny Shumsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction buffer bypass of target instruction in response to part...
- Patent number 9,354,887
- Issue date May 31, 2016
- International Business Machines Corporation
- Eric O. Mejdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency first-in-first-out (FIFO) buffer
- Patent number 8,819,312
- Issue date Aug 26, 2014
- Marvell Israel (M.I.S.L) Ltd.
- Evgeny Shumsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read-write control of a FIFO memory with packet discard
- Patent number 8,285,944
- Issue date Oct 9, 2012
- Xilinx, Inc.
- Roscoe Conkling Nelson, IV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shift register circuit
- Patent number 7,675,488
- Issue date Mar 9, 2010
- Himax Technologies Limited
- Jung-Zone Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for variable delay data transfer
- Patent number 7,600,143
- Issue date Oct 6, 2009
- Unisys Corporation
- Paul S. Neuman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer circuit
- Patent number 7,594,047
- Issue date Sep 22, 2009
- Hewlett-Packard Development Company, L.P.
- King W. Luk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry and methods for efficient FIFO memory
- Patent number 7,333,381
- Issue date Feb 19, 2008
- Marvel Semiconductor Israel Ltd.
- Eitan Rosen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Queue structure with validity vector and order array
- Patent number 7,249,230
- Issue date Jul 24, 2007
- Intel Corporation
- Lim Soon Chieh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry and methods for efficient FIFO memory
- Patent number 7,149,139
- Issue date Dec 12, 2006
- Marvell Semiconductor Israel Ltd.
- Eitan Rosen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
History FIFO with bypass wherein an order through queue is maintain...
- Patent number 7,117,287
- Issue date Oct 3, 2006
- Sun Microsystems, Inc.
- Brian Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory devices having multi-port cache memory arrays therein t...
- Patent number 7,076,610
- Issue date Jul 11, 2006
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory devices having multi-port cache and extended capacity m...
- Patent number 6,874,064
- Issue date Mar 29, 2005
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory devices and methods of operating FIFO memory devices ha...
- Patent number 6,754,777
- Issue date Jun 22, 2004
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing data in a queue
- Patent number 6,708,260
- Issue date Mar 16, 2004
- Hewlett-Packard Development Company, L.P.
- Jeanine Picraux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-port cache memory devices and FIFO memory devices having mult...
- Patent number 6,546,461
- Issue date Apr 8, 2003
- Integrated Device Technology, Inc.
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer circuit with control device to directly output input data or...
- Patent number 5,937,430
- Issue date Aug 10, 1999
- Fujitsu Limited
- Minoru Saitoh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Bypass FIFO for Multiple Virtual Channels
- Publication number 20160139880
- Publication date May 19, 2016
- Cavium, Inc.
- Steven C. Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FOLDED FIFO MEMORY GENERATOR
- Publication number 20140164655
- Publication date Jun 12, 2014
- NVIDIA Corporation
- Robert A. Alfieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROCOMPUTER
- Publication number 20120221679
- Publication date Aug 30, 2012
- DENSO CORPORATION
- Hirofumi YAMAMOTO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Latency First-In-First-Out (FIFO) Buffer
- Publication number 20120079144
- Publication date Mar 29, 2012
- Evgeny Shumsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION UNIT WITH INSTRUCTION BUFFER PIPELINE BYPASS
- Publication number 20110320771
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Eric O. Mejdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffer circuit
- Publication number 20090019193
- Publication date Jan 15, 2009
- King W. Luk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuitry and methods for efficient FIFO memory
- Publication number 20070076503
- Publication date Apr 5, 2007
- Marvell Semiconductor Isreael Ltd.
- Eitan Rosen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIFO-type one-way interfacing device between a master unit and a sl...
- Publication number 20070033306
- Publication date Feb 8, 2007
- Atmel Nantes SA
- Sylvain Garnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Shift register circuit
- Publication number 20060242358
- Publication date Oct 26, 2006
- Himax Technologies, Inc.
- Jung-Zone Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Synchronous interface and method of operation
- Publication number 20060095655
- Publication date May 4, 2006
- George S. Moore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Queue structure with validity vector and order array
- Publication number 20050289305
- Publication date Dec 29, 2005
- Lim Soon Chieh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of managing a device for memorizing data organized in a queu...
- Publication number 20050154843
- Publication date Jul 14, 2005
- Cesar Douady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
History FIFO with bypass
- Publication number 20040243743
- Publication date Dec 2, 2004
- Brian Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fifo memory devices having multi-port cache and extended capacity m...
- Publication number 20040193805
- Publication date Sep 30, 2004
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIFO memory devices having multi-port cache memory arrays therein t...
- Publication number 20040019743
- Publication date Jan 29, 2004
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing data in a queue
- Publication number 20030177318
- Publication date Sep 18, 2003
- Jeanine Picraux
- G06 - COMPUTING CALCULATING COUNTING

With bypass possibility

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Short duration serialization express queue

Bypass FIFO for multiple virtual channels

Low latency first-in-first-out (FIFO) buffer

Instruction buffer bypass of target instruction in response to part...

Low latency first-in-first-out (FIFO) buffer

Read-write control of a FIFO memory with packet discard

Shift register circuit

Method and apparatus for variable delay data transfer

Buffer circuit

Circuitry and methods for efficient FIFO memory

Queue structure with validity vector and order array

Circuitry and methods for efficient FIFO memory

History FIFO with bypass wherein an order through queue is maintain...

FIFO memory devices having multi-port cache memory arrays therein t...

FIFO memory devices having multi-port cache and extended capacity m...

FIFO memory devices and methods of operating FIFO memory devices ha...

Managing data in a queue

Multi-port cache memory devices and FIFO memory devices having mult...

Buffer circuit with control device to directly output input data or...

Patents Applicationslast 30 patents

Bypass FIFO for Multiple Virtual Channels

FOLDED FIFO MEMORY GENERATOR

MICROCOMPUTER

Low Latency First-In-First-Out (FIFO) Buffer

INSTRUCTION UNIT WITH INSTRUCTION BUFFER PIPELINE BYPASS

Buffer circuit

Circuitry and methods for efficient FIFO memory

FIFO-type one-way interfacing device between a master unit and a sl...

Shift register circuit

Synchronous interface and method of operation

Queue structure with validity vector and order array

Method of managing a device for memorizing data organized in a queu...

History FIFO with bypass

Fifo memory devices having multi-port cache and extended capacity m...

FIFO memory devices having multi-port cache memory arrays therein t...

Managing data in a queue