Patent Application
20050289305
A processing system may write data into and/or read data from a queue. For example, a processor might store instructions into and remove instructions from a queue. In some cases, the order in which data was written into and/or read from a queue may be important. For example, a processing system need to read the oldest (or newest) data from a queue. In addition, a processing system may need to manage a queue (e.g., by moving data from one location to another and/or updating pointers associated with the queue).
Some embodiments described herein are associated with a “processing system.” As used herein, the phrase “processing system” may refer to any device that processes data. A processing system may be associated with, for example, an INTEL® Architecture (IA) or IXP processor, a network processor, an Application Specific Integrated Circuit (ASIC) device, and/or an embedded processor.
In addition, some embodiments are associated with a processing “queue.” As used herein the term “queue” refers to any structure that may be used to store data. Examples of queues include a First-In, First-Out (FIFO) queue, a Last-In, First-Out (LIFO) stack, an instruction issue or dispatch stack, and a write buffer for a data cache.
The structure 100 also includes an five-bit validity vector 120 (including bit[0] through bit[4]). Each bit in the validity vector indicates whether or not an associated position in the queue 110 contains valid data. By way of example, bit[1] might equal “0” when position[1] does not contain valid data (e.g., is empty) and “1” when the position does contain valid data. The queue structure 100 is empty when all of the bits in the validity vector 120 are “0” and full when all of the bits are “1.”
The structure 100 also includes a two-dimensional order array 130. Each row in the order array 130 (row[0] through row[4]) is associated with a position in the queue 110 and each column in the array 130 (column[0] through column[4]) is associated with a position in the queue 110. The order array 130 may be, for example, an five-bit by five-bit array.
Although some embodiments are illustrated herein as having five positions, embodiments may have any number of positions (e.g., a twenty-position queue might have a twenty-bit validity vector and a twenty-bit by twenty-bit order array).
According to some embodiments, order array latches 230 associated with row[x], column[x], where x is an integer, are always set to “1” (e.g., the five latches 230 associated with row[0], column[0] through row[4], column[4]). According to other embodiments, no latches might be provided for row[x], column[x].
Each queue position has a write wordline that is coupled to the associated register 210 and to a set (S) input of the associated validity vector latch 220. The write wordline[x] associated with position[x] is also coupled to the reset (R) input of every order array latch 230 in row[x] other than then the one in column[x]. Moreover, write wordline[x] is also coupled to the set input of every order array latch 230 in column[x] other than the one in row[x]. Thus, when right wordline[3] is high: (i) the validity vector latch 220 associated with position[3] will be set to “1,” (ii) every order array latch 230 in row[3], other than the one in colunm[3], will be reset to “0,” and (iii) every order array latch 230 in column[3] will be set to “1.”
Each queue position also has a read wordline that is coupled to the associated register 210 and to the reset input of the associated validity vector latch 220. The read wordline[x] associated with position[x] is also coupled to the set input of every order array latch 230 in row[x] other than then the one in column[x]. Moreover, read wordline[x] is also coupled to the reset input of every order array latch 230 in column[x] other than the one in row[x]. Thus, when read wordline[1] is high: (i) the validity vector latch 220 associated with position[1] will be reset to “0,” (ii) every order array latch 230 in row[1] will be set to “1,” and (iii) every order array latch 230 in column[3] will be reset to “0,” other than the one in row[1].
At 302, data is written into position[x] of an n-position queue. Consider, for example, a sixteen-position queue that is able to store thirty two bits of data in each position. In this case, a processing system may determine that thirty two bits of data need to be stored in the queue and then store the data in queue position[11] (e.g., after selecting an appropriate position as described with respect to
At 304, bit[x] of an n-bit validity vector is updated to indicate that position[x] contains valid data. When data has been stored in queue position[11], for example, validity vector bit[11] might be set to “1.”
At 306, multiple bits in row[x] of a two-dimensional order array are updated. For example, multiple bits in row[x] of an order array might be updated as described with respect to
Referring again to
In addition, every bit the row of the order array 130 associated with that position (e.g., as illustrated by dashed line 432) has been reset to “0” with the exception of the bit in the column associated with that position (i.e., in row[3], column[3]. Moreover, every bit in the column of the order array 130 associated with that position (e.g., as illustrated by dashed line 434) has been set to “1.” Note that in the circuit 200 described with respect to
In
Note that the information in the validity vector 120 and order array 130 may be used to determine the order in which the data was written into the queue. For example, there will be fewer “1s” in a row of the order array 130 associated with an newer entry in the queue structure 100 as compared to an older entry. In the example described with respect to
In some cases, a processing system may need to determine the oldest entry in a queue, referred to as the “head” position of the queue. For example, in FIFO queue the head position might be used to determine which entry should next be removed from the queue.
According to some embodiments, a head position of a queue is determined based on information in a validity vector and an order array. For example, the following technique might be used to determine the head position of an N-position queue:
In this case, the first portion of the technique creates an array A that represents the order array with any row reset to all “0s” when the corresponding entry in the validity vector (valid[n]) indicates that the associated position does not currently contain valid data. The second portion of the technique then sets head[x] to “1” only when every bit in column[x], other than the bit associated with row[x], is equal to “0.” In the example illustrated in
At 804, x (representing a column in an order array) is initialized to “0.” If every bit in column[x], other than row[x], is equal to “0” at 806, head[x] is set to “1” at 808. If at least one bit in column[x], other than row[x], is equal to “1,” then head[x] is set to “0” at 810. If the last column in the order array has been evaluated at 812, the method is done at 816. Otherwise, x is incremented at 814 and the process continues. After all columns have been evaluated, the column having a head[x] value of “1” is the head position of the queue.
In addition to writing data into a queue, a processing system may need to read data from the queue.
At 1006, multiple bits in row[x] of a two-dimensional order array are updated. For example, multiple bits in row[x] might be updated as described with respect to
In addition, every bit in the row of the order array 130 associated with that position (e.g., as illustrated by dashed line 1132) has been set to “1.” Moreover, every bit in the column of the order array 130 associated with that position (e.g., as illustrated by dashed line 1134) has been set to “0” with the exception of the bit in the row associated with that position (i.e., row[4], column[4] of the order array 130). Note that in the circuit 200 described with respect to
In
In some cases, a processing system may need to determine the last position in a queue from which data was read, referred to as the “tail” position of the queue. For example, the processing system might write data into the tail position (e.g., the most recently freed entry of the queue).
According to some embodiments, a tail position of a queue is determined based on information in a validity vector and an order array. For example, the following technique might be used to determine the tail position of an N-position queue:
In this case, the technique sets tail[n] to “1” only if (i) the associated bit in the validity vector is “0” and (ii) every bit in row[n] of the order array is equal to “1.” In the example illustrated in
Note that the particular methods described herein are for illustration only, and other techniques might be used to determine a head or tail position. For example, the following is another technique that might be used to determine a tail position:
When the last row in the order array has been evaluated at 1310, the method is done at 1314. Otherwise, x is incremented at 1312 and the process continues. After all rows have been evaluated, the column having a tail[x] value of “1” is the tail position of the queue.
Thus, embodiments may provide a queue that is associated with a validity vector and/or a two-dimensional order array. In the case of sequential reads, information in the validity vector and order array may be used to determine a head position (e.g., the entry that is most likely to be read next). In the case of sequential writes, information in the validity vector and order array may be used to determine a tail position (e.g., the entry where new data should be written).
The queue may also support random or out-of-order writes and/or reads, and order information may be determined using the validity vector and order array as described herein. For example, pre-fetched instructions may be efficiently placed into and removed from an instruction issue or dispatch stack in an out-of order fashion.
In addition, when data is read from a queue position (e.g., a word is retired or discarded from the queue), the freed entry may be ready to accept new data without moving or destroying the existing information in the queue structure or re-allocating the other entries in the queue. For example, a freed entry between two occupied entries may not be wasted (e.g., the queue is inherently compressible and compact). As a result, information may be kept in a queue for longer periods of time (e.g., improving write coalescence for a write buffer).
The processor 1510 may exchange information with a memory unit, such as a Double Data Rate (DDR) Random Access Memory (RAM) unit 1520. For example, the processor 1510 may retrieve instructions from the DDR RAM unit 1520.
The following illustrates various additional embodiments. These do not constitute a definition of all possible embodiments, and those skilled in the art will understand that many other embodiments are possible. Further, although the following embodiments are briefly described for clarity, those skilled in the art will understand how to make any changes, if necessary, to the above description to accommodate these and other embodiments and applications.
Note that in some embodiments, row[x], column[x] of the order array does not contain any information (e.g., those bits are always set to “1”). Embodiments may instead set those bits to “0” or not implement those bits at all. Moreover, although examples have used “1” to indicate that a position contains valid data, embodiments could instead use “0” (e.g., and the methods and circuits described herein may be adjusted accordingly). Similarly, the meanings of “0” and “1” in the order array may be reversed.
The several embodiments described herein are solely for the purpose of illustration. Persons skilled in the art will recognize from this description other embodiments may be practiced with modifications and alterations limited only by the claims.
