with global bypass

Industry

CPC
G06F9/3828

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

Current Industry

G06F9/3828with global bypass

Industries

Patents Grantslast 30 patents

Information Patent Grant
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- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling heterogeneous computation on multithreaded processors
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Implicit program order
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- Microsoft Technology Licensing, LLC
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Instruction block allocation
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- Issue date Sep 12, 2023
- Microsoft Technology Licensing, LLC
- Jan S. Gray
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Coupling wide memory interface to wide write back paths
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- Issue date Aug 15, 2023
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
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Information Patent Grant
Generation and use of memory access instruction order encodings
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- Issue date Jun 20, 2023
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed cluster training method and apparatus
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- Jun Zhou
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Information Patent Grant
Operator registration method and apparatus for deep learning framew...
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- Issue date Apr 11, 2023
- BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
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- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessors with bypass optimization, variable grid architecture,...
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- Issue date Aug 30, 2022
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Systems and methods for implementing chained tile operations
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Exception handling
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Execution of cross-lane operations in data processing systems
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Information Patent Grant
Opportunistic consumer instruction steering based on producer instr...
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Information Patent Grant
Apparatus and method for processing an instruction matrix specifyin...
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Information Patent Grant
System, apparatus and method for dynamic pipeline stage control of...
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- Issue date Sep 28, 2021
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- Ryan Carlson
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Information Patent Grant
Block-based processor core composition register
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- Issue date Sep 21, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Advanced processor architecture
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- Issue date Jul 13, 2021
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distinct system registers for logical processors
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- Issue date May 25, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coupling wide memory interface to wide write back paths
- Patent number 10,963,379
- Issue date Mar 30, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dense read encoding for dataflow ISA
- Patent number 10,936,316
- Issue date Mar 2, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register read/write ordering
- Patent number 10,871,967
- Issue date Dec 22, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information processing apparatus, dynamic reconfiguration device, a...
- Patent number 10,782,975
- Issue date Sep 22, 2020
- Fuji Xerox Co., Ltd.
- Masahiro Ishiwata
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Information Patent Grant
Debug support for block-based processor
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- Issue date Sep 15, 2020
- Microsoft Technology Licensing, LLC
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Information Patent Grant
Block-based processor including topology and control registers to i...
- Patent number 10,768,936
- Issue date Sep 8, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetching instruction blocks
- Patent number 10,719,321
- Issue date Jul 21, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Executing processor instructions using minimal dependency queue
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- Issue date Jun 9, 2020
- International Business Machines Corporation
- Avraham Ayzenfeld
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Information Patent Grant
Systems and methods for implementing chained tile operations
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- Issue date May 26, 2020
- Intel Corporation
- Christopher J. Hughes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tightly coupled processor arrays using coarse grained reconfigurabl...
- Patent number 10,528,356
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Chia-yu Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for adjacency network delivery of operands to...
- Patent number 10,503,515
- Issue date Dec 10, 2019
- Gerald George Pechanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and task processing method therefor, and storage medium
- Patent number 10,481,957
- Issue date Nov 19, 2019
- Sanechips Technology Co., Ltd.
- Bo Wen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
OPERATOR REGISTRATION METHOD AND APPARATUS FOR DEEP LEARNING FRAMEW...
- Publication number 20220374238
- Publication date Nov 24, 2022
- BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
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- G06 - COMPUTING CALCULATING COUNTING
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Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20220358082
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- Apple Inc.
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ADVANCED PROCESSOR ARCHITECTURE
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Information Patent Application
COUPLING WIDE MEMORY INTERFACE TO WIDE WRITE BACK PATHS
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- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
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SYSTEM, APPARATUS AND METHOD FOR DYNAMIC PIPELINE STAGE CONTROL OF...
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METHOD FOR SOLVING THE PROBLEM OF CLUSTERING USING CELLULAR AUTOMAT...
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SYSTEMS AND METHODS FOR IMPLEMENTING CHAINED TILE OPERATIONS
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OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DATAPATH STEERING
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APPARATUS AND METHOD FOR PROCESSING AN INSTRUCTION MATRIX SPECIFYIN...
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Distributed Cluster Training Method and Apparatus
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SCHEDULING HETEROGENOUS COMPUTATION ON MULTITHREADED PROCESSORS
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- Imagination Technologies Limited
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APPARATUS AND METHOD FOR PROCESSING AN INSTRUCTION MATRIX SPECIFYIN...
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- Intel Corporation
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Hardware Migration between Dissimilar Cores
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PROCESSOR WITH INTER-EXECUTION UNIT INSTRUCTION ISSUE
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SINGLE-CYCLE INSTRUCTION PIPELINE SCHEDULING
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METHOD AND APPARATUS FOR FORWARDING LITERAL GENERATED DATA TO DEPEN...
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- QUALCOMM Incorporated
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APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER I...
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- Shlomo Raikin
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Information Patent Application
PROCESSOR WITH EXECUTION UNIT INTEROPERATION
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- TEXAS INSTRUMENTS INCORPORATED
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LATER STAGE READ PORT REDUCTION
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- Srikanth T. Srinivasan
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Methods and Apparatus For Attaching Application Specific Functions...
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- Altera Corporation
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LOW POWER, HIGH PERFORMANCE, HETEROGENEOUS, SCALABLE PROCESSOR ARCH...
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- ICELERO INC
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Information Patent Application
MULTI-CORE PROCESSOR SYSTEM, SYNCHRONIZATION CONTROL SYSTEM, SYNCHR...
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- Fujitsu Limited
- Koichiro YAMASHITA
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Information Patent Application
LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM...
- Publication number 20130159669
- Publication date Jun 20, 2013
- International Business Machines Corporation
- Miguel Comparan
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Information Patent Application
COMPUTER SYSTEMS AND METHODS FOR REGISTER-BASED MESSAGE PASSING
- Publication number 20130138930
- Publication date May 30, 2013
- Peter J. Wilson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR REDUCING OVERHEAD CAUSED BY COMMUNICATION...
- Publication number 20130124825
- Publication date May 16, 2013
- Min-Wook AHN
- G06 - COMPUTING CALCULATING COUNTING

with global bypass

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Coprocessors with bypass optimization, variable grid architecture,...

Scheduling heterogeneous computation on multithreaded processors

Implicit program order

Instruction block allocation

Coupling wide memory interface to wide write back paths

Generation and use of memory access instruction order encodings

Distributed cluster training method and apparatus

Operator registration method and apparatus for deep learning framew...

Coprocessors with bypass optimization, variable grid architecture,...

Systems and methods for implementing chained tile operations

Exception handling

Execution of cross-lane operations in data processing systems

Opportunistic consumer instruction steering based on producer instr...

Apparatus and method for processing an instruction matrix specifyin...

System, apparatus and method for dynamic pipeline stage control of...

Block-based processor core composition register

Advanced processor architecture

Distinct system registers for logical processors

Coupling wide memory interface to wide write back paths

Dense read encoding for dataflow ISA

Register read/write ordering

Information processing apparatus, dynamic reconfiguration device, a...

Debug support for block-based processor

Block-based processor including topology and control registers to i...

Prefetching instruction blocks

Executing processor instructions using minimal dependency queue

Systems and methods for implementing chained tile operations

Tightly coupled processor arrays using coarse grained reconfigurabl...

Methods and apparatus for adjacency network delivery of operands to...

Processor and task processing method therefor, and storage medium

Patents Applicationslast 30 patents

OPERATOR REGISTRATION METHOD AND APPARATUS FOR DEEP LEARNING FRAMEW...

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

ADVANCED PROCESSOR ARCHITECTURE

COUPLING WIDE MEMORY INTERFACE TO WIDE WRITE BACK PATHS

SYSTEM, APPARATUS AND METHOD FOR DYNAMIC PIPELINE STAGE CONTROL OF...

METHOD FOR SOLVING THE PROBLEM OF CLUSTERING USING CELLULAR AUTOMAT...

SYSTEMS AND METHODS FOR IMPLEMENTING CHAINED TILE OPERATIONS

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DATAPATH STEERING

APPARATUS AND METHOD FOR PROCESSING AN INSTRUCTION MATRIX SPECIFYIN...

Distributed Cluster Training Method and Apparatus

SCHEDULING HETEROGENOUS COMPUTATION ON MULTITHREADED PROCESSORS

APPARATUS AND METHOD FOR PROCESSING AN INSTRUCTION MATRIX SPECIFYIN...

Hardware Migration between Dissimilar Cores

PROCESSOR WITH INTER-EXECUTION UNIT INSTRUCTION ISSUE

DIGITAL SIGNAL PROCESSOR

SINGLE-CYCLE INSTRUCTION PIPELINE SCHEDULING

CHAINING BETWEEN EXPOSED VECTOR PIPELINES

CHAINING BETWEEN EXPOSED VECTOR PIPELINES

METHOD AND APPARATUS FOR FORWARDING LITERAL GENERATED DATA TO DEPEN...

APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER I...

PROCESSOR WITH EXECUTION UNIT INTEROPERATION

LATER STAGE READ PORT REDUCTION

Methods and Apparatus For Attaching Application Specific Functions...

LOW POWER, HIGH PERFORMANCE, HETEROGENEOUS, SCALABLE PROCESSOR ARCH...

MULTI-CORE PROCESSOR SYSTEM, SYNCHRONIZATION CONTROL SYSTEM, SYNCHR...

LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM...

COMPUTER SYSTEMS AND METHODS FOR REGISTER-BASED MESSAGE PASSING

APPARATUS AND METHOD FOR REDUCING OVERHEAD CAUSED BY COMMUNICATION...