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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

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Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for performing field programmable gate array p...
- Patent number 11,216,249
- Issue date Jan 4, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable-logic-directed multiplier mapping
- Patent number 11,163,530
- Issue date Nov 2, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing synthesis for field programmabl...
- Patent number 11,080,019
- Issue date Aug 3, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for accelerating matrix multiply operations as a...
- Patent number 10,902,087
- Issue date Jan 26, 2021
- Advanced Micro Devices, Inc.
- Shaizeen Aga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuits with augmented arithmetic densities
- Patent number 10,715,144
- Issue date Jul 14, 2020
- Intel Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for performing multiplication
- Patent number 9,933,998
- Issue date Apr 3, 2018
- Kuo-Tseng Tseng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pipelined multiply-scan circuit
- Patent number 9,459,832
- Issue date Oct 4, 2016
- Bank of America Corporation
- Steven A. Guccione
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for multiplying binary operands
- Patent number 9,372,665
- Issue date Jun 21, 2016
- Texas Instruments Incorporated
- Christian Wiencke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for multiplying binary operands
- Patent number 8,667,043
- Issue date Mar 4, 2014
- Texas Instruments Incorporated
- Christian Wiencke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data transfer control apparatus and data transfer control method
- Patent number 8,423,742
- Issue date Apr 16, 2013
- Fujitsu Semiconductor Limited
- Tetsuo Miyamoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically configurable processor
- Patent number 6,959,316
- Issue date Oct 25, 2005
- Nokia Mobile Phones Limited
- Jari A. Parviainen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel multiplier
- Patent number 6,263,357
- Issue date Jul 17, 2001
- Hyundai Electronics Industries Co., Ltd.
- Jeong-Ae Choe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multipliers with a shorter run time
- Patent number 5,954,791
- Issue date Sep 21, 1999
- Siemens Aktiengesellschaft
- Jorg-Michael Green
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Divider and multiplier/divider using said divider
- Patent number 5,787,031
- Issue date Jul 28, 1998
- Nippondenso Co., Ltd.
- Kohji Ichikawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed small digital multiplier
- Patent number 5,467,296
- Issue date Nov 14, 1995
- NEC Corporation
- Makoto Suzuki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for multiplying a plurality of N numbers
- Patent number 5,424,970
- Issue date Jun 13, 1995
- Advanced Micro Devices, Inc.
- Donald D. Mondul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for multiplying real-time 2's complement code in a digita...
- Patent number 5,181,184
- Issue date Jan 19, 1993
- Samsung Electronics Co., Ltd.
- Dae-Yoon Shim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS cell for logic operations with fast carry
- Patent number 4,905,179
- Issue date Feb 27, 1990
- CSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
- Luigi Licciardi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital data processor incorporating an orthogonally connected logi...
- Patent number 4,639,857
- Issue date Jan 27, 1987
- The Secretary of State for Defence in Her Britannic Majesty's Government of t...
- John V. McCanny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplying circuit
- Patent number 4,598,382
- Issue date Jul 1, 1986
- Tokyo Shibaura Denki Kabushiki Kaisha
- Tai Sato
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple processing cell digital data processor
- Patent number 4,533,993
- Issue date Aug 6, 1985
- National Research Development Corp.
- John V. McCanny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary multiplication cell circuit
- Patent number 4,363,107
- Issue date Dec 7, 1982
- Tokyo Shibaura Denki Kabushiki Kaisha
- Masahide Ohhashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3794820
- Patent number 3,794,820
- Issue date Feb 26, 1974
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3535498
- Patent number 3,535,498
- Issue date Oct 20, 1970
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3242324
- Patent number 3,242,324
- Issue date Mar 22, 1966
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3015443
- Patent number 3,015,443
- Issue date Jan 2, 1962
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLY-ACCUMULATE CIRCUIT AND METHOD FOR PERFORMING MULTIPLY-ACCU...
- Publication number 20240296012
- Publication date Sep 5, 2024
- ROBERT BOSCH GmbH
- Andre Guntoro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL MATRIX OPERATIONS IN A RECONFIGURABLE COMPUTE FABRIC
- Publication number 20230056246
- Publication date Feb 23, 2023
- Micron Technology, Inc.
- Skyler Arron Windh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FOLDING COLUMN ADDER ARCHITECTURE FOR DIGITAL COMPUTE IN MEMORY
- Publication number 20230031841
- Publication date Feb 2, 2023
- QUALCOMM Incorporated
- Mustafa BADAROGLU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE, DATA GENERATION METHODS USED FOR THE SAME, AN...
- Publication number 20220004363
- Publication date Jan 6, 2022
- RENESAS ELECTRONICS CORPORATION
- Taro FUJII
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE AND METHOD FOR ACCELERATING MATRIX MULTIPLY OPERATIONS AS A...
- Publication number 20200133993
- Publication date Apr 30, 2020
- ADVANCED MICRO DEVICES, INC.
- Shaizeen Aga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS
- Publication number 20140136588
- Publication date May 15, 2014
- Christian Wiencke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS
- Publication number 20090132630
- Publication date May 21, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Christian Wiencke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Full-Adder Modules and Multiplier Devices Using the Same
- Publication number 20080256165
- Publication date Oct 16, 2008
- NXP B.V.
- Rohini Krishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA TRANSFER CONTROL APPARATUS AND DATA TRANSFER CONTROL METHOD
- Publication number 20080244159
- Publication date Oct 2, 2008
- FUJITSU LIMITED
- Tetsuo Miyamoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asynchronous signed multiplier and algorithm thereof
- Publication number 20070100924
- Publication date May 3, 2007
- Chin-Yung Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asynchronous multiplier
- Publication number 20060242219
- Publication date Oct 26, 2006
- Chin-Yung Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Shift and recode multiplier
- Publication number 20050228845
- Publication date Oct 13, 2005
- MathStar, Inc.
- Fuk Ho Pius Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically configurable processor
- Publication number 20020103841
- Publication date Aug 1, 2002
- Jari A. Parviainen
- G06 - COMPUTING CALCULATING COUNTING

with row wise addition of partial products

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method and apparatus for performing field programmable gate array p...

Programmable-logic-directed multiplier mapping

Method and apparatus for performing synthesis for field programmabl...

Device and method for accelerating matrix multiply operations as a...

Logic circuits with augmented arithmetic densities

Methods and apparatuses for performing multiplication

Pipelined multiply-scan circuit

Method and apparatus for multiplying binary operands

Method and apparatus for multiplying binary operands

Data transfer control apparatus and data transfer control method

Dynamically configurable processor

Parallel multiplier

Multipliers with a shorter run time

Divider and multiplier/divider using said divider

High-speed small digital multiplier

Method and apparatus for multiplying a plurality of N numbers

Apparatus for multiplying real-time 2's complement code in a digita...

CMOS cell for logic operations with fast carry

Digital data processor incorporating an orthogonally connected logi...

Multiplying circuit

Multiple processing cell digital data processor

Binary multiplication cell circuit

3794820

3535498

3242324

3015443

Patents Applicationslast 30 patents

MULTIPLY-ACCUMULATE CIRCUIT AND METHOD FOR PERFORMING MULTIPLY-ACCU...

PARALLEL MATRIX OPERATIONS IN A RECONFIGURABLE COMPUTE FABRIC

FOLDING COLUMN ADDER ARCHITECTURE FOR DIGITAL COMPUTE IN MEMORY

SEMICONDUCTOR DEVICE, DATA GENERATION METHODS USED FOR THE SAME, AN...

DEVICE AND METHOD FOR ACCELERATING MATRIX MULTIPLY OPERATIONS AS A...

METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS

METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS

Full-Adder Modules and Multiplier Devices Using the Same

DATA TRANSFER CONTROL APPARATUS AND DATA TRANSFER CONTROL METHOD

Asynchronous signed multiplier and algorithm thereof

Asynchronous multiplier

Shift and recode multiplier

Dynamically configurable processor