Word-line or row circuits

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G11C13/0028

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00

Current Industry

G11C13/0028Word-line or row circuits

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Resistive random access memory device
- Patent number 12,322,441
- Issue date Jun 3, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yu-Der Chih
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory devices with different word lines
- Patent number 12,315,561
- Issue date May 27, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
One-time programmable (OTP) memory and method of operating the same
- Patent number 12,308,078
- Issue date May 20, 2025
- Taiwan Semiconductor Manufacturing Company Limited
- Kuo-Pin Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Sparse piers for three-dimensional memory arrays
- Patent number 12,302,766
- Issue date May 13, 2025
- Micron Technology, Inc.
- Stephen W. Russell
- G11 - INFORMATION STORAGE
Information Patent Grant
Data processing method based on memristor array and electronic appa...
- Patent number 12,283,320
- Issue date Apr 22, 2025
- Tsinghua University
- Huaqiang Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device and method of controlling the same
- Patent number 12,283,315
- Issue date Apr 22, 2025
- SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Haruhiko Terada
- G11 - INFORMATION STORAGE
Information Patent Grant
Compensating non-ideality of a neuromorphic memory device
- Patent number 12,277,970
- Issue date Apr 15, 2025
- International Business Machines Corporation
- Benedikt Kersting
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional structure of memories for in-memory computing
- Patent number 12,272,398
- Issue date Apr 8, 2025
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Théophile Dubreuil
- G11 - INFORMATION STORAGE
Information Patent Grant
Forming operation method of resistive random access memory
- Patent number 12,272,397
- Issue date Apr 8, 2025
- United Microelectronics Corp.
- Yi Ting Hung
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential programming of two-terminal resistive switching memory...
- Patent number 12,272,399
- Issue date Apr 8, 2025
- Crossbar, Inc.
- Hagop Nazarian
- G11 - INFORMATION STORAGE
Information Patent Grant
Spike current suppression in a memory array
- Patent number 12,260,908
- Issue date Mar 25, 2025
- Micron Technology, Inc.
- Sundaravadivel Rajarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encoding additional states in a three-dimensional crosspoint memory...
- Patent number 12,249,372
- Issue date Mar 11, 2025
- Intel Corporation
- Rouhollah Mousavi Iraei
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic inhibit voltage to reduce write power for random-access memory
- Patent number 12,230,320
- Issue date Feb 18, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Zheng-Jun Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell array circuit and method of forming the same
- Patent number 12,230,323
- Issue date Feb 18, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chin-I Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal processing apparatus and signal processing method
- Patent number 12,226,216
- Issue date Feb 18, 2025
- Tsinghua University
- Huaqiang Wu
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Systems and methods for efficient matrix multiplication
- Patent number 12,223,009
- Issue date Feb 11, 2025
- Rain Neuromorphics Inc.
- Jack David Kendall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and method of forming the same
- Patent number 12,217,817
- Issue date Feb 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jung-Piao Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dropout in neutral networks using threshold switching selectors in...
- Patent number 12,205,008
- Issue date Jan 21, 2025
- SANDISK TECHNOLOGIES LLC
- Wen Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device having physical unclonable function and memory system...
- Patent number 12,205,643
- Issue date Jan 21, 2025
- Samsung Electronics Co., Ltd.
- Jooyong Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive change element arrays
- Patent number 12,176,028
- Issue date Dec 24, 2024
- Nantero, Inc.
- Jia Luo
- G11 - INFORMATION STORAGE
Information Patent Grant
Drift aware read operations
- Patent number 12,176,029
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-referenced and regulated sensing solution for phase change mem...
- Patent number 12,176,030
- Issue date Dec 24, 2024
- Universite d'Aix-Marseille
- Jean-Michel Portal
- G11 - INFORMATION STORAGE
Information Patent Grant
Silicon-on-insulator (SOI) circuitry for low-voltage memory bit-lin...
- Patent number 12,170,110
- Issue date Dec 17, 2024
- Weebit Nano Ltd.
- Lior Dagan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with a split pillar architecture
- Patent number 12,171,105
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell array circuit and method of forming the same
- Patent number 12,165,705
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chin-I Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Duo-level word line driver
- Patent number 12,165,703
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device
- Patent number 12,159,666
- Issue date Dec 3, 2024
- Samsung Electronics Co., Ltd.
- Sungkyu Jo
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level memory programming and readout
- Patent number 12,153,823
- Issue date Nov 26, 2024
- Intel Corporation
- Davide Fugazza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ReRAM memory array that includes ReRAM memory cells having a ReRAM...
- Patent number 12,154,622
- Issue date Nov 26, 2024
- Microsemi SoC Corp.
- Victor Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential programming of two-terminal memory with program detect...
- Patent number 12,154,624
- Issue date Nov 26, 2024
- Crossbar, Inc.
- Hagop Nazarian
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
EXCLUSIVE-OR BASED NON-VOLATILE MEMORY
- Publication number 20250166702
- Publication date May 22, 2025
- Samsung Electronics Co., Ltd.
- Jaehyuk LEE
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH A SPLIT PILLAR ARCHITECTURE
- Publication number 20250159910
- Publication date May 15, 2025
- Micron Technology, Inc.
- Lorenzo Fratin
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND PROGRAMMABLE MACRO CIRCUIT
- Publication number 20250149086
- Publication date May 8, 2025
- Taiwan Semiconductor Manufacturing company Ltd.
- YU-WEI LIN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD OF FORMING THE SAME
- Publication number 20250124955
- Publication date Apr 17, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jung-Piao Chiu
- G11 - INFORMATION STORAGE
Information Patent Application
Drift Aware Read Operations
- Publication number 20250118366
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Karthik Sarpatwari
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-STEP PROGRAMMING SCHEMES FOR PROGRAMMING CROSSBAR CIRCUITS
- Publication number 20250111877
- Publication date Apr 3, 2025
- TetraMem Inc.
- Gong Lei
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND INITIALIZING METHOD THEREOF
- Publication number 20250095732
- Publication date Mar 20, 2025
- Samsung Electronics Co., Ltd.
- KYUDONG PARK
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL ARRAY CIRCUIT AND METHOD OF FORMING THE SAME
- Publication number 20250095734
- Publication date Mar 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chin-I SU
- G11 - INFORMATION STORAGE
Information Patent Application
CHALCOGENIDE-BASED MEMORY MATERIAL, AND MEMORY DEVICE AND ELECTRONI...
- Publication number 20250098558
- Publication date Mar 20, 2025
- Samsung Electronics Co., Ltd.
- Hajun SUNG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL ARRAY UNIT
- Publication number 20250087267
- Publication date Mar 13, 2025
- Sony Semiconductor Solutions Corporation
- NOBUKAZU MURATA
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION SYSTEM USING A SEGMENTED MEMORY ARCHITECTURE...
- Publication number 20250078922
- Publication date Mar 6, 2025
- STMicroelectronics International N.V.
- Marcella CARISSIMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A CONFIGURATION MEMORY CELL
- Publication number 20250078923
- Publication date Mar 6, 2025
- Microsemi SoC Corp.
- Victor Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
DUO-LEVEL WORD LINE DRIVER
- Publication number 20250078921
- Publication date Mar 6, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Hao Lee
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY, RELATED INTEGRATED CIRCUIT, ELECTRONIC SYSTEM...
- Publication number 20250078926
- Publication date Mar 6, 2025
- STMicroelectronics International N.V.
- Davide Manfré
- G11 - INFORMATION STORAGE
Information Patent Application
DATA PROCESSING METHOD BASED ON MEMRISTOR ARRAY, AND ELECTRONIC APP...
- Publication number 20250078924
- Publication date Mar 6, 2025
- TSINGHUA UNIVERSITY
- Huaqiang WU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT-SERIAL INPUT SCHEMES FOR CROSSBAR CIRCUITS
- Publication number 20250069655
- Publication date Feb 27, 2025
- TetraMem Inc.
- Hengfang Zhu
- G11 - INFORMATION STORAGE
Information Patent Application
RESISTIVE RANDOM ACCESS MEMORY AND MEMORY MINI-ARRAY THEREOF WITH I...
- Publication number 20250046372
- Publication date Feb 6, 2025
- UNITED MICROELECTRONICS CORP.
- Shu-Hung Yu
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION DEVICE WITH AT LEAST AN IMPROVED DIGITAL DETE...
- Publication number 20250046371
- Publication date Feb 6, 2025
- STMicroelectronics International N.V.
- Marco PASOTTI
- G11 - INFORMATION STORAGE
Information Patent Application
ReRAM MEMORY ARRAY THAT INCLUDES ReRAM MEMORY CELLS HAVING A ReRAM...
- Publication number 20250037764
- Publication date Jan 30, 2025
- Microsemi SoC Corp.
- Victor Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
DECODER ARCHITECTURE FOR MEMORY DEVICE
- Publication number 20250014640
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Ferdinando Bedeschi
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE, OPERATING METHOD OF THE SEMICONDUCTOR DEVICE,...
- Publication number 20250006259
- Publication date Jan 2, 2025
- SK HYNIX INC.
- Jae Yeon Lee
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTATION CIRCUIT UNIT, NEURAL NETWORK COMPUTATION CIRCUIT, AND M...
- Publication number 20240428061
- Publication date Dec 26, 2024
- NUVOTON TECHNOLOGY CORPORATION JAPAN
- Satoshi AWAMURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPENSATING NON-IDEALITY OF A NEUROMORPHIC MEMORY DEVICE
- Publication number 20240420762
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Benedikt Kersting
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT COMPRISING ELECTRONIC CELLS AND A CONTROL CIRCUIT
- Publication number 20240422992
- Publication date Dec 19, 2024
- STMicroelectronics International N.V.
- Andrea REDAELLI
- G11 - INFORMATION STORAGE
Information Patent Application
VERTICAL MEMORY DEVICE INCLUDING SELECTOR WITH VARIABLE RESISTIVE M...
- Publication number 20240422991
- Publication date Dec 19, 2024
- Samsung Electronics Co., Ltd.
- Youngsun Song
- G11 - INFORMATION STORAGE
Information Patent Application
NEURAL NETWORK COMPUTATION CIRCUIT, CONTROL CIRCUIT THEREFOR, AND C...
- Publication number 20240411520
- Publication date Dec 12, 2024
- NUVOTON TECHNOLOGY CORPORATION JAPAN
- Masayoshi NAKAYAMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-MEMORY COMPUTATION DEVICE FOR IMPLEMENTING AT LEAST A MULTILAYER...
- Publication number 20240404569
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Marcella CARISSIMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-MEMORY COMPUTATION DEVICE FOR PERFORMING A SIGNED MAC OPERATION
- Publication number 20240404594
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Marcella CARISSIMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY AND OPERATION METHOD THEREOF
- Publication number 20240386953
- Publication date Nov 21, 2024
- SK HYNIX INC.
- Kyu Sung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY AND READING, WRITING AND ERASING METHODS THEREOF
- Publication number 20240379158
- Publication date Nov 14, 2024
- Shanghai IC R&D Center Co., Ltd.
- Lingyi GUO
- G11 - INFORMATION STORAGE

Word-line or row circuits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Resistive random access memory device

Semiconductor memory devices with different word lines

One-time programmable (OTP) memory and method of operating the same

Sparse piers for three-dimensional memory arrays

Data processing method based on memristor array and electronic appa...

Semiconductor device and method of controlling the same

Compensating non-ideality of a neuromorphic memory device

Three-dimensional structure of memories for in-memory computing

Forming operation method of resistive random access memory

Differential programming of two-terminal resistive switching memory...

Spike current suppression in a memory array

Encoding additional states in a three-dimensional crosspoint memory...

Dynamic inhibit voltage to reduce write power for random-access memory

Memory cell array circuit and method of forming the same

Signal processing apparatus and signal processing method

Systems and methods for efficient matrix multiplication

Memory device and method of forming the same

Dropout in neutral networks using threshold switching selectors in...

Memory device having physical unclonable function and memory system...

Resistive change element arrays

Drift aware read operations

Self-referenced and regulated sensing solution for phase change mem...

Silicon-on-insulator (SOI) circuitry for low-voltage memory bit-lin...

Memory device with a split pillar architecture

Memory cell array circuit and method of forming the same

Duo-level word line driver

Memory device

Multi-level memory programming and readout

ReRAM memory array that includes ReRAM memory cells having a ReRAM...

Differential programming of two-terminal memory with program detect...

Patents Applicationslast 30 patents

EXCLUSIVE-OR BASED NON-VOLATILE MEMORY

MEMORY DEVICE WITH A SPLIT PILLAR ARCHITECTURE

SEMICONDUCTOR DEVICE AND PROGRAMMABLE MACRO CIRCUIT

MEMORY DEVICE AND METHOD OF FORMING THE SAME

Drift Aware Read Operations

MULTI-STEP PROGRAMMING SCHEMES FOR PROGRAMMING CROSSBAR CIRCUITS

MEMORY DEVICE AND INITIALIZING METHOD THEREOF

MEMORY CELL ARRAY CIRCUIT AND METHOD OF FORMING THE SAME

CHALCOGENIDE-BASED MEMORY MATERIAL, AND MEMORY DEVICE AND ELECTRONI...

MEMORY CELL ARRAY UNIT

IN-MEMORY COMPUTATION SYSTEM USING A SEGMENTED MEMORY ARCHITECTURE...

A CONFIGURATION MEMORY CELL

DUO-LEVEL WORD LINE DRIVER

NON-VOLATILE MEMORY, RELATED INTEGRATED CIRCUIT, ELECTRONIC SYSTEM...

DATA PROCESSING METHOD BASED ON MEMRISTOR ARRAY, AND ELECTRONIC APP...

BIT-SERIAL INPUT SCHEMES FOR CROSSBAR CIRCUITS

RESISTIVE RANDOM ACCESS MEMORY AND MEMORY MINI-ARRAY THEREOF WITH I...

IN-MEMORY COMPUTATION DEVICE WITH AT LEAST AN IMPROVED DIGITAL DETE...

ReRAM MEMORY ARRAY THAT INCLUDES ReRAM MEMORY CELLS HAVING A ReRAM...

DECODER ARCHITECTURE FOR MEMORY DEVICE

SEMICONDUCTOR DEVICE, OPERATING METHOD OF THE SEMICONDUCTOR DEVICE,...

COMPUTATION CIRCUIT UNIT, NEURAL NETWORK COMPUTATION CIRCUIT, AND M...

COMPENSATING NON-IDEALITY OF A NEUROMORPHIC MEMORY DEVICE

MEMORY CIRCUIT COMPRISING ELECTRONIC CELLS AND A CONTROL CIRCUIT

VERTICAL MEMORY DEVICE INCLUDING SELECTOR WITH VARIABLE RESISTIVE M...

NEURAL NETWORK COMPUTATION CIRCUIT, CONTROL CIRCUIT THEREFOR, AND C...

IN-MEMORY COMPUTATION DEVICE FOR IMPLEMENTING AT LEAST A MULTILAYER...

IN-MEMORY COMPUTATION DEVICE FOR PERFORMING A SIGNED MAC OPERATION

MEMORY AND OPERATION METHOD THEREOF

MEMORY AND READING, WRITING AND ERASING METHODS THEREOF