Claims
- 1. A voltage regulator for a dynamic random access memory, said voltage regulator comprising:a voltage reference circuit for producing a reference voltage; a plurality of power amplifiers for developing a supply voltage for supplying power to the dynamic random access memory, said power amplifiers being responsive to said reference voltage and having a gain greater than one; and a control circuit for producing control signals for controlling said plurality of power amplifiers.
- 2. The voltage regulator of claim 1 wherein said plurality of power amplifiers is divided into a plurality of groups for one of independent and concurrent operation among said groups.
- 3. The voltage regulator of claim 1 wherein each of said plurality of power amplifiers comprises an amplifier portion and a boost circuit that is operable to increase the slew rate of said amplifier portion in response to said control signals.
- 4. The voltage regulator of claim 1 additionally comprising a booster amplifier for supplying additional power to the dynamic random access memory in response to said control signals reflecting a predetermined operating condition.
- 5. The voltage regulator of claim 4 wherein said booster amplifier has an output connected through an impedance with an output of said power amplifiers.
- 6. The voltage regulator of claim 4 additionally comprising a standby amplifier for supplying power in response to said control signals reflecting periods in which said plurality of power amplifiers and said booster amplifier are not operating.
- 7. The voltage regulator of claim 4 wherein said booster amplifier is designed to operate on a bias current less than a bias current required for each of said plurality of power amplifiers.
- 8. The voltage regulator of claim 7 wherein said standby amplifier is designed to operate on a bias current less than said bias currents required for each of said plurality of power amplifiers and said booster amplifier.
- 9. A voltage regulator for a dynamic random access memory having an array divided into array blocks, said voltage regulator comprising:a voltage reference circuit for producing a reference voltage; multiple power amplifiers for developing a supply voltage, said power amplifiers arranged such that certain of said power amplifiers supply power to certain of the array blocks; and control circuitry for disabling a power amplifier when the array block associated therewith is disabled.
- 10. The voltage regulator of claim 9 wherein each array block has a capacitance associated therewith, and wherein said control circuitry disables power amplifiers in response to array blocks being disabled so as to maintain a predetermined ratio of the total remaining capacitance to the number of operational power amplifiers.
- 11. The voltage regulator of claim 9 wherein said predetermined ratio is approximately 0.25 nanofarads per operational power amplifier.
- 12. fame voltage regulator of claim 9 wherein said multiple power amplifiers include twelve amplifiers, and wherein eight of said power amplifiers are each associated with one of eight array blocks.
- 13. An amplifier portion of a voltage regulator for a dynamic random access memory, said amplifier portion comprising:a plurality of power amplifiers divided into a plurality of groups for operation in one of separate or concurrent operation to achieve predetermined levels of power output to the dynamic random access memory.
- 14. The amplifier portion of claim 13 additionally comprising a booster amplifier for supplying additional power in response to a predetermined operating condition.
- 15. The amplifier portion of claim 14 additionally comprising a standby amplifier for maintaining a nominal level of power output to the dynamic random access memory when said plurality of power amplifiers and said booster amplifier are not operating.
- 16. The amplifier portion of claim 13 wherein each of said plurality of power amplifiers has gain greater than one.
- 17. The amplifier portion of claim 13 wherein each of said plurality of power amplifiers comprises an amplifier portion and a boost circuit that is operable to increase the slew rate of said amplifier portion in response to a predetermined operating condition.
- 18. A voltage regulator for a dynamic random access memory, comprising:a circuit for generating a reference voltage from an externally supplied voltage; an amplifier for amplifying said reference voltage with a gain greater than unity to generate an internal supply voltage available on first and second buses providing voltages to an array of memory cells; and control logic for generating control signals for controlling said amplifier.
- 19. The voltage regulator of claim 18 wherein said amplifier comprises a plurality of individual amplifiers arranged substantially in parallel between said circuit for generating a reference voltage and said first bus.
- 20. The voltage regulator of claim 19 wherein said first bus carries an array voltage.
- 21. The voltage regulator of claim 20 wherein said first bus is connected to said second bus through an impedance.
- 22. The voltage regulator of claim 21 wherein said second bus carries a peripheral voltage.
- 23. The voltage regulator of claim 18 wherein said amplifier comprises at least one power amplifier, at least one booster amplifier, and at least one standby amplifier, wherein said voltage regulator has reduced operating current requirements by allowing selective operation of the individual amplifiers in one of individual and predetermined combinations.
- 24. A method of operating an amplifier portion of a voltage regulator for a dynamic random access memory, said method comprising the steps of:operating at least one power amplifier during periods of memory array operations; operating, independently of the operating of the at least one power amplifier, at least one booster amplifier during periods of voltage pump operations; and operating a standby amplifier at a low maintenance current level regardless of the state of operation of the power amplifier and booster amplifier.
- 25. The method of claim 24 wherein said step of operating the standby amplifier includes operating the standby amplifier at a current level that is less than that required for operating the at least one power amplifier.
- 26. The method of claim 24 wherein said step of operating the at least one power amplifier comprises the step of operating a plurality of power amplifiers in groups to match the power produced to the power required by the memory.
- 27. The method of claim 26 wherein said step of operating a plurality of power amplifiers in groups includes operating a plurality of power amplifiers in groups to perform refresh operations at various rates.
- 28. The method of claim 24 wherein said steps of operating at least one power amplifier and operating at least one booster amplifier are carried out while maintaining an impedance between the respective outputs of the at least one power amplifier and the at least one booster amplifier to avoid transfer of transients.
- 29. voltage regulator for a dynamic random access memory for supplying an output voltage in response to an external voltage, and wherein the output voltage has a first characteristic when the external voltage is in a powerup range, has a second characteristic when the external voltage is in an operating range, and has a third characteristic when the external voltage is in a burn-in range, said regulator comprising:a circuit for supplying the external voltage as the output voltage when the external voltage is below a first predetermined value defining the powerup range; an active reference circuit for receiving the external voltage and for producing a reference signal having a desired relationship with the external voltage; a unity gain amplifier responsive to said reference signal for producing a reference voltage when the external voltage is above said first predetermined value; a power amplifier stage for amplifying the reference voltage by a factor greater than unity to provide the output voltage when said circuit for supplying is not supplying the external voltage as the output voltage; and a pullup stage for pulling up the reference voltage so as to substantially track the external voltage when the external voltage exceeds said second predetermined value defining the burn-in range.
- 30. The voltage regulator of claim 29 wherein said active reference circuit comprises a current source for presenting a current at a circuit node and a circuit for providing an impedance between said node and a reference potential, said reference signal being available at said node.
- 31. The voltage regulator of claim 30 wherein said circuit for providing an impedance includes a circuit for adjusting the impedance to modify said reference signal available at said node.
- 32. The voltage regulator of claim 31 wherein said circuit for providing an impedance includes a plurality of transistors connected in series, with each transistor's gate connected to a common potential, and a plurality of switches each for selectively shunting one of said transistors.
- 33. The voltage regulator of claim 32 wherein said switches are controlled by fuses, and wherein opening certain of said fuses turns its associated switch on, and wherein opening certain other of said fuses turns its associated switch off.
- 34. The voltage regulator of claim 33 wherein said plurality of transistors includes a first plurality of field effect transistors and wherein said plurality of switches includes a second plurality of field effect transistors.
- 35. The voltage regulator of claim 29 wherein said pullup stage includes a plurality of diodes connected between the external voltage and the reference voltage.
- 36. The voltage regulator of claim 35 wherein the reference voltage is the external voltage less a voltage drop across said plurality of diodes.
- 37. The voltage regulator of claim 29 wherein said circuit for supplying includes a switch for shorting a bus carrying the external voltage with a bus carrying the output voltage.
- 38. A method of operating an amplifier portion of a voltage regulator for a dynamic random access memory divided into array blocks, said amplifier portion having a number of individual power amplifiers, said method comprising the steps of:operating at least one power amplifier for each array block during periods when operations are performed by the memory; determining when an array block has become disabled; and disabling at least one power amplifier for each disabled array block.
- 39. The method of claim 38 wherein each array block has a capacitance associated therewith, and wherein said step of disabling at least one power amplifier includes the step of maintaining a predetermined ratio of the total remaining capacitance to non-disabled power amplifiers.
- 40. The method of claim 39 wherein said predetermined ratio is approximately 0.25 nanofarads per non-disabled power amplifier.
- 41. A method of operating an amplifier portion of a voltage regulator for a dynamic random access memory divided into eight array blocks, said amplifier portion having a number of individual power amplifiers, said method comprising the steps of:operating at least one power amplifier for each of the eight array blocks during periods when operations are performed on the memory; operating the remaining power amplifiers in one of individual and group modes depending on the power requirements of the memory; determining when an array block has become disabled; and disabling the power amplifier associated with the disabled array block.
- 42. A memory device, comprising:an array of memory cells; a plurality of peripheral devices for writing information into and reading information out of said array of memory cells; a plurality of voltage supplies for generating a plurality of supply voltages, at least one of said voltage supplies being a voltage regulator comprising: a voltage reference circuit for producing a reference voltage; a plurality of power amplifiers for developing a supply voltage, said power amplifiers being responsive to said reference voltage and having a gain greater than one; and a control circuit for producing control signals for controlling said plurality of power amplifiers; and a power distribution bus for delivering said plurality of supply voltages to said array and said plurality of peripheral devices.
- 43. A memory device, comprising:an array of memory cells divided into a plurality of array blocks; a plurality of peripheral devices for writing information into and reading information out of said plurality of array blocks; a plurality of voltage supplies for generating a plurality of supply voltages, at least one of said voltage supplies being a voltage regulator comprising: a voltage reference circuit for producing a reference voltage; multiple power amplifiers for developing a supply voltage, said power amplifiers arranged such that certain of said power amplifiers supply power to certain of said plurality of array blocks; and control circuitry for disabling a power amplifier when the array block associated therewith is disabled; and a power distribution bus for delivering said plurality of supply voltages to said array and said plurality of peripheral devices.
- 44. The memory device of claim 43 wherein said multiple power amplifiers are divided into a plurality of groups for operation in one of separate or concurrent operation to achieve predetermined levels of power output to said plurality of array blocks.
- 45. A memory device, comprising:an array of memory cells; a plurality of peripheral devices for writing information into and reading information out of said array of memory cells; a plurality of voltage supplies for generating a plurality of supply voltages, at least one of said voltage supplies being a voltage regulator comprising: a circuit for generating a reference voltage from an externally supplied voltage; an amplifier for amplifying said reference voltage with a gain greater than unity to generate an internal supply voltage; and control logic for generating control signals for controlling said amplifier; and a power distribution bus for delivering said plurality of supply voltages to said array and said plurality of peripheral devices.
- 46. A memory device, comprising:an array of memory cells; a plurality of peripheral devices for writing information into and reading information out of said array of memory cells; a plurality of voltage supplies for generating a plurality of supply voltages, at least one of said voltage supplies being a voltage regulator for supplying an output voltage in response to an external voltage, said regulator comprising: a circuit for supplying the external voltage as the output voltage when the external voltage is below a first predetermined value defining a powerup range; an active reference circuit for receiving the external voltage and for producing a reference signal having a desired relationship with the external voltage; a unity gain amplifier responsive to said reference signal for producing a reference voltage when the external voltage is above said first predetermined value; a power amplifier stage for amplifying the reference voltage by a factor greater than unity to provide the output voltage when said circuit for supplying is not supplying the external voltage as the output voltage; and a pullup stage for pulling up the reference voltage so as to substantially track the external voltage when the external voltage exceeds a second predetermined value defining a burn-in range; and a power distribution bus for delivering said plurality of supply voltages and said output voltage to said array and said plurality of peripheral devices.
- 47. A system, comprising:a control unit for performing a series of instructions; and a dynamic random access memory responsive to said control unit, said memory comprising: an array of memory cells; a plurality of peripheral devices for writing information into and reading information out of said array of memory cells; a plurality of voltage supplies for generating a plurality of supply voltages, at least one of said voltage supplies being a voltage regulator comprising: a voltage reference circuit for producing a reference voltage; a plurality of power amplifiers for developing a supply voltage, said power amplifiers being responsive to said reference voltage and having a gain greater than one; and a control circuit for producing control signals for controlling said plurality of power amplifiers; and a power distribution bus for delivering said plurality of supply voltages to said array and said plurality of peripheral devices.
- 48. A system comprising:a control unit for performing a series of instructions; and a dynamic random access memory responsive to said control unit, said memory comprising: an array of memory cells divided into a plurality of array blocks; a plurality of peripheral devices for writing information into and reading information out of said plurality of array blocks; a plurality of voltage supplies for generating a plurality of supply voltages, at least one of said voltage supplies being a voltage regulator comprising: a voltage reference circuit for producing a reference voltage; multiple power amplifiers for developing a supply voltage, said power amplifiers arranged such that certain of said power amplifiers supply power to certain of said plurality of array blocks; and control circuitry for disabling a power amplifier when the array block associated therewith is disabled; and a power distribution bus for delivering said plurality of supply voltages to said array and said plurality of peripheral devices.
- 49. The system of claim 48 wherein said multiple power amplifiers are divided into a plurality of groups for operation in one of separate or concurrent operation to achieve predetermined levels of power output to said plurality of array blocks.
- 50. A system, comprising:a control unit for performing a series of instructions; and a dynamic random access memory responsive to said control unit, said memory comprising: an array of memory cells; a plurality of peripheral devices for writing information into and reading information out of said array of memory cells; a plurality of voltage supplies for generating a plurality of supply voltages, at least one of said voltage supplies being a voltage regulator comprising: a circuit for generating a reference voltage from an externally supplied voltage; an amplifier for amplifying said reference voltage with a gain greater than unity to generate an internal supply voltage; and control logic for generating control signals for controlling said amplifier; and a power distribution bus for delivering said plurality of supply voltages to said array and said plurality of peripheral devices.
- 51. A system, comprising:a control unit for performing a series of instructions; and a dynamic random access memory responsive to said control unit, said memory comprising: an array of memory cells; a plurality of peripheral devices for writing information into and reading information out of said array of memory cells; a plurality of voltage supplies for generating a plurality of supply voltages, at least one of said voltage supplies being a voltage regulator for supplying an output voltage in response to an external voltage, said regulator comprising: a circuit for supplying the external voltage as the output voltage when the external voltage is below a first predetermined value defining a powerup range; an active reference circuit for receiving the external voltage and for producing a reference signal having a desired relationship with the external voltage; a unity gain amplifier responsive to said reference signal for producing a reference voltage when the external voltage is above said first predetermined value; a power amplifier stage for amplifying the reference voltage by a factor greater than unity to provide the output voltage when said circuit for supplying is not supplying the external voltage as the output voltage; and a pullup stage for pulling up the reference voltage so as to substantially track the external voltage when the external voltage exceeds a second predetermined value defining a burn-in range; and a power distribution bus for delivering said plurality of supply voltages and said output voltage to said array and said plurality of peripheral devices.
Parent Case Info
This Application is a divisional application of U.S. application Ser. No. 09/620,606 filed Jul. 20, 2000, which is a divisional application of U.S. application Ser. No. 08/916,692 filed Aug. 22, 1997 which claims the benefit of provisional application Ser. No. 60/050,929.
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|
Number |
Date |
Country |
|
60/050924 |
May 1997 |
US |