Referring to
Thus a dual read-write-ports memory-array is achieved with the limitation that read and write has to be done in different sections Exclusive gating of the high-order read- and write-addresses can disable double addressing of a connector C and avoids data destruction. The fully decoded addresses for read and write are combined in a logical OR function and drive two word lines, Address range of a cache is typical 128 or 256, a subsection, i.e. a group of cells assigned to a section of a bit line, typically comprises 16 addresses, Likelihood to hit same address group is small and therefore performance hit is small whereas area saving compared to the use of a so-called 8T eight-transistor cell is large.
gbl=NOT{{NOT{wr1}AND NOT{blt1))OR {NOT(wr0}AND NOT(blt0}}.
The AND OR invert function is achieved with transistor N0, N1, N2, N3, N4 and P1, P2, P3, P4. As in unselected connectors C0, C1 “blt” stays precharged at ‘1’, only a connector C0, C1 selected by read can switch the global bit line “gbl”.
Active wr0 or wr1 also connect global write-lines wt and “wc” to “blc0” or “blc1” and “blt0” or “blt1”. Write-lines “wt” and “wc” are global and common to all connectors C0, C1 and carry the write information: for write ‘0’ wt=0, wc=1, for write ‘1’ wt=1, wc=0.
Taking ‘1’ as up level and ‘0’ as down level blt0 or blt1 is pulled down with wc=1 via N6 and N11 or N21. Wt=0 turns on P5 and down going blt0 or blt1 turns on transistors P12 or P22 thus pulling up blc0 or blc1 respectively. The forced bit lines switch the selected cell. P6 is kept off. Transistors in series P13 or P23 could be turned on by an “early” read ‘1’ which might occur before the selected cell is switched and which tends to pull down blc0 or blc1, But closed P6 prohibits weakening of pull down action on blt0 or blt1.
Write ‘1’ is the exact compliment operation to write ‘0’. Wc=O and wt=0 cause a half select condition where selected bit lines are operated like during a read but cannot propagate any signal to the global bit line. Cross-coupled transistors P12, P13 or P22, P23 are working as cross-coupled keepers on the bit lines.
In a read-operation the selected cell pulls down either blc or blt and the activated connector propagates the read information to the global bit line gbl according to the logical function above. For connectors C0, C1 in read condition cross-coupled keepers P12, P13 or P22, P23 may be disabled partially depending on global signals wc, wt. As bit lines always start from a precharged up level and an active cell can compensate sufficiently leakage on the local bit line, keepers are not necessary for read.
As it can be seen in
While the present invention has been described in detail, in conjunction with specific preferred embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art, in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.
Number | Date | Country | Kind |
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06121618.0 | Oct 2006 | EP | regional |