Bit line control circuits

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G11C7/12

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GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/12Bit line control circuits

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Circuit topology for high performance memory with secondary pre-cha...
- Patent number 12,367,914
- Issue date Jul 22, 2025
- Intel Corporation
- Arindrajit Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
Split array architecture for analog neural memory in a deep learnin...
- Patent number 12,367,386
- Issue date Jul 22, 2025
- Silicon Storage Technology, Inc.
- Hieu Van Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile storage of secure data in 6T SRAM cells using hot carr...
- Patent number 12,361,987
- Issue date Jul 15, 2025
- BTQ Technologies Corp.
- Zachary Irving Belateche
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with external clock synchronized operation
- Patent number 12,361,990
- Issue date Jul 15, 2025
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Noise reduction in sense amplifiers for non-volatile memory
- Patent number 12,361,984
- Issue date Jul 15, 2025
- SanDisk Technologies, Inc.
- Iris Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Using embedded switches for reducing capacitive loading on a memory...
- Patent number 12,361,981
- Issue date Jul 15, 2025
- Taiwan Semiconductor Manufacturing Company Limited
- Chia-Ta Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture supporting both conventional memory access mode...
- Patent number 12,361,982
- Issue date Jul 15, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing precharge current surge in digital compute in memory
- Patent number 12,354,657
- Issue date Jul 8, 2025
- Mediatek Inc.
- Chetan Deshpande
- G11 - INFORMATION STORAGE
Information Patent Grant
Test circuit using clock signals having mutually different frequency
- Patent number 12,354,686
- Issue date Jul 8, 2025
- Micron Technology, Inc.
- Yutaka Uemura
- G11 - INFORMATION STORAGE
Information Patent Grant
Active current consumption save mode for non-volatile memory using...
- Patent number 12,354,704
- Issue date Jul 8, 2025
- SanDisk Technologies, Inc.
- Ke Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for reading data from a storage buffer including delaying a...
- Patent number 12,347,519
- Issue date Jul 1, 2025
- Micron Technology, Inc.
- Parthasarathy Gajapathy
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory and sense-amplifying compensation circuit thereof
- Patent number 12,347,516
- Issue date Jul 1, 2025
- GigaDevice Semiconductor Inc.
- Miao Xie
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for tracking access occurrences
- Patent number 12,347,515
- Issue date Jul 1, 2025
- Micron Technology, Inc.
- Yuan He
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry borrowing for memory arrays
- Patent number 12,340,832
- Issue date Jun 24, 2025
- Micron Technology, Inc.
- Andrea Martinelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Page buffer, memory device, and method for programming thereof
- Patent number 12,334,182
- Issue date Jun 17, 2025
- Yangtze Memory Technologies Co., Ltd.
- Zhichao Du
- G11 - INFORMATION STORAGE
Information Patent Grant
Wrong way read-before write solutions in SRAM
- Patent number 12,327,608
- Issue date Jun 10, 2025
- Advanced Micro Devices, Inc.
- Russell Schreiber
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses including multiple read modes and methods for same
- Patent number 12,327,609
- Issue date Jun 10, 2025
- Micron Technology, Inc.
- Theodore T. Pekny
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit line pre-charge circuit for power management modes in multi ban...
- Patent number 12,327,586
- Issue date Jun 10, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, read clock generation circuit, and method for contro...
- Patent number 12,322,474
- Issue date Jun 3, 2025
- Taiwan Semiconductor Manufacturing Company Ltd.
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-2-port memory with dual pre-charge circuits
- Patent number 12,308,091
- Issue date May 20, 2025
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory package having stacked array dies and reduced driver load
- Patent number 12,308,087
- Issue date May 20, 2025
- Netlist, Inc.
- Hyun Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory devices
- Patent number 12,300,302
- Issue date May 13, 2025
- Samsung Electronics Co., Ltd.
- Hee-Woong Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-charging bit lines through charge-sharing
- Patent number 12,300,312
- Issue date May 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahmut Sinangil
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory device including selective bit line and source l...
- Patent number 12,293,088
- Issue date May 6, 2025
- SK hynix Inc.
- Chan Hui Jeong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static random-access memory (SRAM) apparatus and method for reducin...
- Patent number 12,293,806
- Issue date May 6, 2025
- Samsung Electronics Co., Ltd.
- Lava Kumar Pulluru
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with reduced voltage offset
- Patent number 12,283,337
- Issue date Apr 22, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yorinobu Fujino
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power static random access memory
- Patent number 12,283,313
- Issue date Apr 22, 2025
- UNTETHER AI CORPORATION
- Katsuyuki Sato
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory sense amplifier with precharge
- Patent number 12,283,317
- Issue date Apr 22, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Zheng-Jun Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Global data line of multi-array synchronous random access memory (S...
- Patent number 12,283,338
- Issue date Apr 22, 2025
- Samsung Electronics Co., Ltd.
- Hee Choul Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Page buffer circuit and memory device including the same
- Patent number 12,277,995
- Issue date Apr 15, 2025
- Samsung Electronics Co., Ltd.
- Jin-Young Chun
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE AND METHOD OF CONTROLLING EQUIVALENT RESISTANCE OF BI...
- Publication number 20250239279
- Publication date Jul 24, 2025
- United Microelectronics Corp.
- Chin-Hsun Yeh
- G11 - INFORMATION STORAGE
Information Patent Application
Pre-Charging Bit Lines Through Charge-Sharing
- Publication number 20250239299
- Publication date Jul 24, 2025
- Taiwan Semiconductor Manufacturing Company, Limited
- Mahmut Sinangil
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD FOR OPERATING MEMORY DEVICE
- Publication number 20250239281
- Publication date Jul 24, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Haruki MORI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND OPERATING METHOD THEREOF
- Publication number 20250231694
- Publication date Jul 17, 2025
- SK HYNIX INC.
- Chan Hui JEONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME MULTIPLEXING OF CLEANUP AND WRITE FOR SERIAL READ WRITE MEMORY
- Publication number 20250218506
- Publication date Jul 3, 2025
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE AND METHOD WITH MULTI-BIT OPERATION
- Publication number 20250218479
- Publication date Jul 3, 2025
- Samsung Electronics Co., Ltd.
- Sungmeen MYUNG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH RESET VOLTAGE CONTROL
- Publication number 20250218477
- Publication date Jul 3, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ali Taghvaei
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER INTERMEDIATE PRE-CHARGE OPERATIONS IN MEMORY
- Publication number 20250218481
- Publication date Jul 3, 2025
- Taiwan Semiconductor Manufacturing company Ltd.
- Yorinobu Fujino
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE THAT DETECTS CONNECTION DEFECTS BETWEEN WORD L...
- Publication number 20250218522
- Publication date Jul 3, 2025
- SK HYNIX INC.
- Tae Sik Yun
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER WITH REDUCED VOLTAGE OFFSET
- Publication number 20250218473
- Publication date Jul 3, 2025
- Taiwan Semiconductor Manufacturing company Ltd.
- Yorinobu Fujino
- G11 - INFORMATION STORAGE
Information Patent Application
BITLINE SENSING AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME
- Publication number 20250210072
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- MIJI JANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES WITH BACKSIDE BOOST CAPACITOR AND METHODS FOR FORMIN...
- Publication number 20250201281
- Publication date Jun 19, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Nail Etkin Can Akkaya
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH ADDITIONAL WRITE BIT LINES
- Publication number 20250191652
- Publication date Jun 12, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
PAGE BUFFER CIRCUIT AND OPERATING METHOD THEREOF ADAPTED FOR PAGE R...
- Publication number 20250191621
- Publication date Jun 12, 2025
- Macronix International Co., Ltd.
- Bo-Rong Lin
- G11 - INFORMATION STORAGE
Information Patent Application
RRAM PROCESS INTEGRATION SCHEME AND CELL STRUCTURE WITH REDUCED MAS...
- Publication number 20250194108
- Publication date Jun 12, 2025
- Hefei Reliance Memory Limited
- Zhichao LU
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE USING MULTIPLE MEMORY CELLS GROUPED TO JOINTLY STORE...
- Publication number 20250182834
- Publication date Jun 5, 2025
- MEDIATEK INC.
- Tzu-Hsien Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device
- Publication number 20250182797
- Publication date Jun 5, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chien-Chen Lin
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION MEMORY CELL
- Publication number 20250174256
- Publication date May 29, 2025
- Microsemi SoC Corp.
- Victor Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH SOURCE LINE CONTROL
- Publication number 20250174257
- Publication date May 29, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Perng-Fei Yuh
- G11 - INFORMATION STORAGE
Information Patent Application
PAGE BUFFERS AND OPERATION METHODS THEREOF, MEMORY DEVICES, AND MEM...
- Publication number 20250174255
- Publication date May 29, 2025
- Yangtze Memory Technologies Co., Ltd.
- Weiwei He
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE ENDED SENSE AMPLIFIER WITH CURRENT PULSE CIRCUIT
- Publication number 20250166671
- Publication date May 22, 2025
- GLOBALFOUNDRIES U.S. Inc.
- Siva Kumar Chinthu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE INCLUDING PAGE BUFFER, MEMORY SYSTEM INCLUDING PAGE B...
- Publication number 20250166674
- Publication date May 22, 2025
- Yangtze Memory Technologies Co., Ltd.
- Yan WANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND COMPUTATION METHOD THEREOF
- Publication number 20250157508
- Publication date May 15, 2025
- Macronix International Co., Ltd.
- Huai-Mu Wang
- G11 - INFORMATION STORAGE
Information Patent Application
LOW-POWER STATIC RANDOM ACCESS MEMORY
- Publication number 20250157530
- Publication date May 15, 2025
- UNTETHER AI CORPORATION
- Saijagan SAIJAGAN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION
- Publication number 20250157503
- Publication date May 15, 2025
- Rambus Inc.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT AND METHOD OF OPERATING THE SAME
- Publication number 20250157512
- Publication date May 15, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Tzu CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
LEVEL SHIFTING CIRCUIT
- Publication number 20250141451
- Publication date May 1, 2025
- STMicroelectronics International N.V.
- Thomas Pierre Georges Jouanneau
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM POWER-UP RANDOM NUMBER GENERATOR
- Publication number 20250140311
- Publication date May 1, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Che Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING DEVICE, MEMORY CONTROLLER, AND METHOD FOR PERFORMING AN I...
- Publication number 20250124958
- Publication date Apr 17, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- YU-DER CHIH
- G11 - INFORMATION STORAGE
Information Patent Application
BANKED SENSE AMPLIFIER CIRCUIT FOR A MEMORY CORE AND A MEMORY CORE...
- Publication number 20250118362
- Publication date Apr 10, 2025
- International Business Machines Corporation
- Wolfgang Penth
- G11 - INFORMATION STORAGE

Bit line control circuits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Circuit topology for high performance memory with secondary pre-cha...

Split array architecture for analog neural memory in a deep learnin...

Non-volatile storage of secure data in 6T SRAM cells using hot carr...

Memory with external clock synchronized operation

Noise reduction in sense amplifiers for non-volatile memory

Using embedded switches for reducing capacitive loading on a memory...

Memory architecture supporting both conventional memory access mode...

Reducing precharge current surge in digital compute in memory

Test circuit using clock signals having mutually different frequency

Active current consumption save mode for non-volatile memory using...

Methods for reading data from a storage buffer including delaying a...

Random access memory and sense-amplifying compensation circuit thereof

Circuit for tracking access occurrences

Circuitry borrowing for memory arrays

Page buffer, memory device, and method for programming thereof

Wrong way read-before write solutions in SRAM

Apparatuses including multiple read modes and methods for same

Bit line pre-charge circuit for power management modes in multi ban...

Memory device, read clock generation circuit, and method for contro...

Pseudo-2-port memory with dual pre-charge circuits

Memory package having stacked array dies and reduced driver load

Nonvolatile memory devices

Pre-charging bit lines through charge-sharing

Nonvolatile memory device including selective bit line and source l...

Static random-access memory (SRAM) apparatus and method for reducin...

Sense amplifier with reduced voltage offset

Low-power static random access memory

Memory sense amplifier with precharge

Global data line of multi-array synchronous random access memory (S...

Page buffer circuit and memory device including the same

Patents Applicationslast 30 patents

MEMORY DEVICE AND METHOD OF CONTROLLING EQUIVALENT RESISTANCE OF BI...

Pre-Charging Bit Lines Through Charge-Sharing

MEMORY DEVICE AND METHOD FOR OPERATING MEMORY DEVICE

MEMORY DEVICE AND OPERATING METHOD THEREOF

TIME MULTIPLEXING OF CLEANUP AND WRITE FOR SERIAL READ WRITE MEMORY

DEVICE AND METHOD WITH MULTI-BIT OPERATION

MEMORY DEVICE WITH RESET VOLTAGE CONTROL

LOW POWER INTERMEDIATE PRE-CHARGE OPERATIONS IN MEMORY

SEMICONDUCTOR DEVICE THAT DETECTS CONNECTION DEFECTS BETWEEN WORD L...

SENSE AMPLIFIER WITH REDUCED VOLTAGE OFFSET

BITLINE SENSING AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME

MEMORY DEVICES WITH BACKSIDE BOOST CAPACITOR AND METHODS FOR FORMIN...

MEMORY DEVICE WITH ADDITIONAL WRITE BIT LINES

PAGE BUFFER CIRCUIT AND OPERATING METHOD THEREOF ADAPTED FOR PAGE R...

RRAM PROCESS INTEGRATION SCHEME AND CELL STRUCTURE WITH REDUCED MAS...

MEMORY DEVICE USING MULTIPLE MEMORY CELLS GROUPED TO JOINTLY STORE...

Memory Device

CONFIGURATION MEMORY CELL

MEMORY DEVICE WITH SOURCE LINE CONTROL

PAGE BUFFERS AND OPERATION METHODS THEREOF, MEMORY DEVICES, AND MEM...

SINGLE ENDED SENSE AMPLIFIER WITH CURRENT PULSE CIRCUIT

MEMORY DEVICE INCLUDING PAGE BUFFER, MEMORY SYSTEM INCLUDING PAGE B...

MEMORY DEVICE AND COMPUTATION METHOD THEREOF

LOW-POWER STATIC RANDOM ACCESS MEMORY

MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION

MEMORY CIRCUIT AND METHOD OF OPERATING THE SAME

LEVEL SHIFTING CIRCUIT

SRAM POWER-UP RANDOM NUMBER GENERATOR

COMPUTING DEVICE, MEMORY CONTROLLER, AND METHOD FOR PERFORMING AN I...

BANKED SENSE AMPLIFIER CIRCUIT FOR A MEMORY CORE AND A MEMORY CORE...