Accelerating programming of a flash memory module

Abstract

According to an embodiment of the invention there is provided a method for accelerating programming of data, the method may include receiving multiple input data units that were sent from a host computer; wherein the input data units may include first and second input data units; first level programming the first input data units to cache memory pages and first level programming the second input data units to first level target memory pages; and applying a copy back operation that comprises retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages differs from a cache memory page; and wherein the first level programming is faster than the second level programming.

Description

BACKGROUND OF THE INVENTION

Multi level cells (MLC) flash memory cells may store multiple bits per cell. These multiple bits per cell may include a least significant bit (LSB), a most significant bit (MSB) and zero or more central significant bits (CSBs).

Bits of different order (also referred to as bits of different significance) are stored by programmings of different significance. MSB bits are programmed by MSB programming, LSB bits are programmed by LSB programming and each CSB bit is programmed by the appropriate CSB programming. Higher significance bit programming is faster than lower significance bit programming.

When performing MSB programming a host interface of a memory controller can slow down the programming process (form a bottleneck) while when performing LSB programming (which is slower than MSB programming) the flash memory module can slow down the programming process (form a bottleneck).

FIG. 1 is a prior art timing diagram 100 that shows (a) data being written 10 by a host computer to a host interface of a memory controller, (b) data being written to a flash memory module from a flash memory module interface of a memory controller, (c) a first idle event 31 in which a flash memory module waits for data from a host computer and (d) a second idle event 32 in which the host computer is barred from sending more information—as the programming of data to a flash memory module did not end.

There is a growing need to increase the programming speed especially in devices where an internal volatile memory of a memory controller is not big enough to smooth (by buffering) the incoming data.

SUMMARY

According to an embodiment of the invention there may be provided a method, a non-transitory computer readable medium and a memory controller for acceleration of programming.

According to an embodiment of the invention there may be provided a method for accelerating programming of data, the method may include receiving multiple input data units that were sent from a host computer; wherein the input data units comprise first and second input data units; first level programming the first input data units to cache memory pages and first level programming the second input data units to first level target memory pages; and applying a copy back operation that retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages differs from a cache memory page; and wherein the first level programming may be faster than the second level programming.

The first level programming may be a most significant bit (MSB) programming.

The second level programming may be a least significant bit (LSB) programming.

The first level programming of the first and second input data units occur in parallel to each other.

The first level programming of the first and second input data units occur in a partially overlapping manner.

The method may include preventing programming of any input data unit after the input data unit is programmed to a target page.

The ratio between an overall number of dies performing Copy Back and an overall number of dies caching may exceed one.

The ratio between an overall number of dies performing Caching an overall size of dies performing Copy Back and may be a fraction of a ratio between programming speeds of the first level and second level programming.

The fraction may be one half.

The input data units may include third input data units; and the method may include first level programming the third input data units to additional cache memory pages; wherein the applying of the copy back operation may include retrieving the third input data units from the additional cache memory pages and third level programming the third input data units to third level target memory pages; and wherein the third level programming differs by speed from the first and second level programming.

According to an embodiment of the invention there may be provided method for accelerating programming of data, the method receiving multiple input data units by a memory controller and from a host computer; wherein the input data units first and second input data units; instructing a programming circuit of a flash memory module to perform first level programming the first input data units to cache memory pages of the flash memory module and to perform first level programming the second input data units to first level target memory pages of the flash memory module; and instructing a copy back circuit of the flash memory module to apply a copy back operation that retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages differs from a cache memory page; and wherein the first level programming may be faster than the second level programming. The method may include allocating cache memory pages and target pages.

The allocating may include responsive to programming speeds of the first level and second level programming.

The input data units may include third input data units; wherein the method may include first level programming the third input data units to additional cache memory pages; wherein the applying of the copy back operation may include retrieving the third input data units from the additional cache memory pages and third level programming the third input data units to third level target memory pages; and wherein the third level programming may differ by speed from the first and second level programming.

According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer causes the computer to execute the stages of receiving multiple input data units that were sent from a host computer; wherein the input data units may include first and second input data units; first level programming the first input data units to cache memory pages and first level programming the second input data units to first level target memory pages; and applying a copy back operation that retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages may differ from a cache memory page; and wherein the first level programming may include faster than the second level programming.

According to an embodiment of the invention there may be provided a memory controller that may include a control unit and an interface; wherein the interface may be arranged to receive multiple input data units from a host computer; wherein the input data units may include first and second input data units; wherein the control unit may be arranged to instruct a programming circuit of a flash memory module to perform first level programming the first input data units to cache memory pages of the flash memory module and to perform first level programming of the second input data units to first level target memory pages of the flash memory module; and instruct a copy back circuit of the flash memory module to apply a copy back operation that retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages differs from a cache memory page; and wherein the first level programming may be faster than the second level programming.

According to an embodiment of the invention there may be provided a flash memory module that may include an interface, a copy back circuit, a programming circuit and a flash memory pages; wherein the interface may be arranged to receive multiple input data units from a memory controller; wherein the input data units may include first and second input data units; wherein the programming circuit may be arranged to perform first level programming the first input data units to cache memory pages of the flash memory module and to perform first level programming of the second input data units to first level target memory pages of the flash memory module; and wherein the copy back circuit may be arranged to apply a copy back operation that may include retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages may differ from a cache memory page; and wherein the first level programming may include faster than the second level programming.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

FIG. 1 is a prior art timing diagram;

FIG. 2 illustrates a method according to an embodiment of the invention;

FIG. 3 illustrates a method according to an embodiment of the invention;

FIG. 4 illustrates a system according to an embodiment of the invention; and

FIG. 5 is a timing diagram according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method and should be applied mutatis mutandis to a non-transitory computer readable medium that stores instructions that once executed by a computer result in the execution of the method.

Any reference in the specification to a system should be applied mutatis mutandis to a method that may be executed by the system and should be applied mutatis mutandis to a non-transitory computer readable medium that stores instructions that may be executed by the system.

Any reference in the specification to a non-transitory computer readable medium should be applied mutatis mutandis to a system capable of executing the instructions stored in the non-transitory computer readable medium and should be applied mutatis mutandis to method that may be executed by a computer that reads the instructions stored in the non-transitory computer readable medium.

FIG. 2 illustrates method 200 according to an embodiment of the invention.

Method 200 is executed by a flash memory module that may be coupled to a memory controller that in turn is coupled to a host computer.

Method 200 may start by stage 210 of receiving multiple input data units that were sent from a host computer. The input data units comprise first and second input data units. The first input data units are to be cached while the second data units are to be written to their target memory pages.

Stage 210 may be followed by stages 220 and 230.

Stage 220 may include first level programming the first input data units to cache memory pages and first level programming the second input data units to first level target memory pages.

Stage 230 may include applying a copy back operation that comprises retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages.

Any target page out of the first level target pages and the second level target pages differ from a cache memory page. The first level programming is faster than the second level programming. Cache memory pages may be SLC mode pages within MSB device.

The first level programming may be a most significant bit (MSB) programming. The second level programming may be a least significant bit (LSB) programming.

It is noted that the first and second level programming may be selected from a group of different bit significance programming that may include MSB programming, LSB programming and at least one CSB programming.

The first level programming of the first and second input data units may occur in parallel to each other, in a partially of fully overlapping manner.

Programming data to a target page may mean that the data is not further programming to another page. Thus, the method may include preventing further programming of any input data unit after the input data unit is programmed to a target page. Alternatively, further programming of the data may be performed during memory management operations such as cleaning or merging.

The ratio between an overall size (or overall number) of caching dies and an overall size (or overall number) of target dies may exceed one, may equal one or may be lower than one.

The ratio between an overall size (or overall number) of target dies an overall size (or overall number) of caching dies may be related to (for example may be a fraction of) a ratio between programming speeds of the first level and second level programming. The optimal ratio shall equalize the performance of caching process and copy-back process.

The fraction may be equal to the ratio between programming speeds of caching and copy-back. Meaning faster process will need less dies for operation and wise versa. In case part of the pages are programmed directly without caching first, ration would be one half, one third and the like, according to directly programmed fraction of the overall pages

The method may be applied mutatis mutandis to more than two programming levels. For example, the input data units further comprise third input data units; and the method may include first level programming the third input data units to additional cache memory pages. The applying of the copy back operation may also include retrieving the third input data units from the additional cache memory pages and third level programming the third input data units to third level target memory pages. The third level programming differs by speed from the first and second level programming.

FIG. 3 illustrates method 300 according to an embodiment of the invention.

Method 300 is executed by a memory controller that is coupled to a host computer and to a flash memory module.

Method 300 may start by stage 310 of receiving multiple input data units by a memory controller and from a host computer; wherein the input data units comprises first and second input data units.

Stage 310 may be followed by stages 320 and 330.

Stage 320 may include instructing a programming circuit of a flash memory module to perform first level programming the first input data units to cache memory pages of the flash memory module and to perform first level programming the second input data units to first level target memory pages of the flash memory module.

Stage 330 may include instructing a copy back circuit of the flash memory module to apply a copy back operation that comprises retrieving the first input data units from the cache memory pages and second level programming the first input data units to the second level target memory pages. Any target page out of the first level target pages and the second level target pages differ from a cache memory page. The first level programming is faster than the second level programming.

Method 300 may also include stage 305 of allocating cache memory pages and target pages, and may include allocating dies for caching process and for copy-back process.

The allocating of dies may be responsive to programming speeds of the first level and second level programming.

The allocating can include allocating memory dies for caching process and dies for copy back process so that the ratio between an overall size (or overall number) of cache memory dies and an overall size (or overall number) of copy back dies may exceed one, may equal one or may be lower than one.

The allocating can include allocating cache memory dies and dies for copy back so that the ratio between an overall size (or overall number) of copy back dies an overall size (or overall number) of caching memory dies may be a fraction of a ratio between programming speeds of the first level and second level programming.

If first level programming is done directly, while second level is done via copy back process, the fraction may be one half, one third, and the like.

The method may be applied mutatis mutandis to more than two programming levels. For example, the input data units may include third input data units. The method may include instructing the programming circuit of the flash memory module to perform third level programming the third input data units to additional cache memory pages. The applying of the copy back operation further comprises retrieving the third input data units from the additional cache memory pages and third level programming the third input data units to third level target memory pages. The third level programming differs by speed from the first and second level programming.

In order to balance and optimize Caching and Copy Back stages need to get near the same performance.

Using ratio between MSB and LSB page program bandwidth (or speed) BW (single die):

$\frac{{\mathrm{MSB}}_{\mathrm{BW}}}{{\mathrm{LSB}}_{\mathrm{BW}}}=\rho$

Assuming that caching and MSB programming have similar performance, and assuming that caching group of dies perform both caching of data designated to second level and first level direct programming. Thus caching process process twice more data than Cony Back process. Caching to Copy Back ratio then (single die):

$\frac{{\mathrm{MSB}}_{\mathrm{BW}}}{\left(2·{\mathrm{LSB}}_{\mathrm{BW}}\right)}=1/2\rho$

Optimal balancing would be L/M≈½ρ, where L-number of dies performing Copy-Back (toward LSB), and M-number of dies performing Caching (toward MSB).

Other ratios (other than ½) can be applied.

Average write BW is given by:

$\mathrm{Absolute}\mathrm{Average}\mathrm{Write}\mathrm{BW}=\frac{\mathrm{Total}\mathrm{data}\mathrm{written}}{\mathrm{Total}\mathrm{time}\mathrm{it}\mathrm{took}}=\frac{\mathrm{Data}\mathrm{Written}\mathrm{to}\mathrm{MSB}+\mathrm{Data}\mathrm{Written}\mathrm{to}\mathrm{LSB}}{\mathrm{Time}\mathrm{took}\mathrm{to}\mathrm{write}\mathrm{MSB}+\mathrm{Time}\mathrm{took}\mathrm{to}\mathrm{write}\mathrm{LSB}}=\frac{\mathrm{Data}\mathrm{Written}\mathrm{to}\mathrm{MSB}+\mathrm{Data}\mathrm{Written}\mathrm{to}\mathrm{LSB}}{\frac{\mathrm{Data}\mathrm{Written}\mathrm{to}\mathrm{MSB}}{\mathrm{Write}\mathrm{BW}\mathrm{MSB}}+\frac{\mathrm{Data}\mathrm{Written}\mathrm{to}\mathrm{LSB}}{\mathrm{Write}\mathrm{BW}\mathrm{LSB}}}\underset{\begin{array}{c}\mathrm{Assuming}\mathrm{same}\mathrm{amount}\\ \mathrm{of}\mathrm{data}\mathrm{we}\mathrm{get}\end{array}}{\to }\frac{2}{\frac{1}{\mathrm{Write}\mathrm{BW}\mathrm{MSB}}+\frac{1}{\mathrm{Write}\mathrm{BW}\mathrm{LSB}}}=2{\left({\left(\mathrm{Write}\mathrm{BW}\mathrm{MSB}\right)}^{-1}+{\left(\mathrm{Write}\mathrm{BW}\mathrm{LSB}\right)}^{-1}\right)}^{-1}$

Performance of prior art device: Average Write BW=2((Effective Write BW MSB)⁻¹+(Effective Write BW LSB)⁻¹)⁻¹

Where Effective Write BW=Max (Write BW, Host Interface BW)=Max (Write BW, α) due to Host interface as bottleneck.

Total MSB pages write BW is higher than LSB→Write BW MSB>Write BW LSB

Total MSB pages write BW is higher than Host interface speed→Write BW MSB>α→Effective Write BW MSB=α

Total LSB pages write BW is lower than Host interface speed→Write BW LSB<α→Effective Write BW LSB=Write BW LSB

Thus: Average Write BW=2((α)⁻¹+(Write BW LSB)⁻¹)⁻¹

Performance when practicing a method according to an embodiment of the invention:

The flash memory module is virtually divided to two groups:

a. N—number of dies performing Caching to SLC and MSB;

b. M—number of dies performing Copy-back operations.

Data in and Caching BW given by Effective Cache In BW=2((Effective Write BW MSB(N dies))¹+(Effective Write BW SLC(N dies))⁻¹)⁻¹

Assuming that the number N was chosen in such manner that Caching performance is near Host interface we can assume that Effective equal to caching: Effective Cache In BW=2((N·Write BW MSB)⁻¹+(N·Write BW SLC)⁻¹)⁻¹

Copy Back BW is given by M·Copy Back BW LSB

Total performance is given by the bottleneck of those two processes: Write BW=Min(Effective Cache In BW,M·Copy Back BW LSB)

Example:

	Variable	Symbol	Value	Units
	Host I/F BW	HBW	100	[MB/s]
	NAND I/F BW	NBW	300	[MB/s]
	Program Speed	SLC	γ	50	[us]
		MSB	α	50	[us]
		LSB	β	8⅓	[us]
	Number of dies	Total		8
		Caching	N	2
		Copy-Back	M	6

Host Interface BW=100 MB/s

Average NAND die Write BW=2(α⁻¹+β⁻¹)⁻¹=2(50⁻¹+8⅓⁻¹)⁻¹=14.3 MB/s

If there will be no Host Interface bottleneck:

Average Array Write BW=(N+M)·Average NAND die Write BW=114.3 MB/s

Host Interface bottleneck cause

$\mathrm{Actual}\mathrm{Write}\mathrm{BW}=2{\left({\left(\mathrm{MIN}\left(\mathrm{HBW},\left(N+M\right)\alpha \right)\right)}^{-1}+{\left(\mathrm{MIN}\left(\mathrm{HBW},\left(N+M\right)\beta \right)\right)}^{-1}\right)}^{-1}=2{\left({100}^{-1}+662/3^{-1}\right)}^{-1}=80\mathrm{MB}/s$

Invention Write BW=MIN (Caching, Copy_Back)=MIN (MIN (HBW, N·α),2·M·β)=MIN (MIN (100,2·50), 2·6·8⅓)=100 MB/s

Accordingly—the appliance of methods 200 and/or 300 resulted in a full Host Interface BW utilization and a gain of 25% in comparison to the prior art performance.

FIG. 4 illustrates a flash memory module 410, a memory controller 420 and a host computer 430 according to an embodiment of the invention.

The memory controller 420 includes a control unit 422 and an interface 424. The interface may include a host interface 424(1) and a flash memory module interface 424(2).

The interface 424 is arranged to receive multiple input data units from a host computer. The input data units comprises first and second input data units.

The control unit 422 is arranged to (a) instruct a programming circuit of a flash memory module to perform first level programming the first input data units to cache memory pages of the flash memory module and to perform first level programming of the second input data units to first level target memory pages of the flash memory module; and (b) instruct a copy back circuit of the flash memory module to apply a copy back operation that comprises retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages. Any target page (out of the first level target pages and the second level target pages) differs from a cache memory page. The first level programming is faster than the second level programming.

Flash memory module 410 includes interface 412, a copy back circuit 414, a programming circuit 416, and flash memory pages 418.

The flash memory pages 418 may include flash memory pages that at a certain point in time are cache memory pages (such as 418(1)) and may include flash memory pages that at the certain point in time are non-cache memory pages and may be target memory pages (such as 418(2)). The allocation may be fixed or change over time.

The interface 412 is arranged to receive multiple input data units from a memory controller; wherein the input data units comprises first and second input data units.

The programming circuit 416 is arranged to perform first level programming the first input data units to cache memory pages of the flash memory module and to perform first level programming of the second input data units to first level target memory pages of the flash memory module.

The copy back circuit 414 is arranged to apply a copy back operation that comprises retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages. Any target page out of the first level target pages and the second level target pages may differ from a cache memory page. The first level programming is faster than the second level programming.

FIG. 5 is a timing diagram 500 according to an embodiment of the invention. The timing diagram 500 shows (a) data being written 10 by a host computer to a host interface of a memory controller, (b) first data units being written 12 to cache memory pages, and (c) data being copied back 14 to second level target pages.

The invention may also be implemented in a computer program for running on a computer system, at least including code portions for performing steps of a method according to the invention when run on a programmable apparatus, such as a computer system or enabling a programmable apparatus to perform functions of a device or system according to the invention. The computer program may cause the storage system to allocate disk drives to disk drive groups.

A computer program is a list of instructions such as a particular application program and/or an operating system. The computer program may for instance include one or more of a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system.

The computer program may be stored internally on a non-transitory computer readable medium. All or some of the computer program may be provided on computer readable media permanently, removably or remotely coupled to an information processing system. The computer readable media may include, for example and without limitation, any number of the following magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc.

A computer process typically includes an executing (running) program or portion of a program, current program values and state information, and the resources used by the operating system to manage the execution of the process. An operating system (OS) is the software that manages the sharing of the resources of a computer and provides programmers with an interface used to access those resources. An operating system processes system data and user input, and responds by allocating and managing tasks and internal system resources as a service to users and programs of the system.

The computer system may for instance include at least one processing unit, associated memory and a number of input/output (I/O) devices. When executing the computer program, the computer system processes information according to the computer program and produces resultant output information via I/O devices.

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

The connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa. Also, plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. Likewise, single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals.

Although specific conductivity types or polarity of potentials have been described in the examples, it will be appreciated that conductivity types and polarities of potentials may be reversed.

Each signal described herein may be designed as positive or negative logic. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein may be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

Furthermore, the terms “assert” or “set” and “negate” (or “deassert” or “clear”) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.

Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.

Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Also for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.

Also for example, the examples, or portions thereof, may implemented as soft or code representations of physical circuitry or of logical representations convertible into physical circuitry, such as in a hardware description language of any appropriate type.

Also, the invention is not limited to physical devices or units implemented in non-programmable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code, such as mainframes, minicomputers, servers, workstations, personal computers, notepads, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices, commonly denoted in this application as ‘computer systems’.

However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims

1. A method for accelerating programming of data, comprising: receiving multiple input data units that were sent from a host computer; wherein the input data units comprise first and second input data units;most significant bit (MSB) programming the first input data units to cache memory pages and MSB programming the second input data units to first level target memory pages; andapplying a copy back operation that comprises retrieving the first input data units from the cache memory pages and least significant bit (LSB) programming the retrieved first input data units to second level target memory pages;wherein any target page out of the first level target memory pages and the second level target memory pages differs from a cache memory page;wherein the MSB programming is faster than the LSB programming;wherein the input data units further comprise third input data units;wherein the method further comprises MSB programming the third input data units to additional cache memory pages;wherein the applying of the copy back operation further comprises retrieving the third input data units from the additional cache memory pages and third level programming the third input data units to third level target memory pages; andwherein the third level programming differs by speed from the MSB and LSB programming.

2. The method according to claim 1, wherein the MSB programming of the first and second input data units occur in parallel to each other.

3. The method according to claim 1, wherein the MSB programming of the first and second input data units occur in a partially overlapping manner.

4. The method according to claim 1, further comprising preventing further programming of any input data unit after the input data unit is programmed to a target page.

5. The method according to claim 1, wherein a ratio between an overall number of dies performing Copy Back and an overall number of dies caching exceeds one.

6. The method according to claim 1, wherein a ratio between an overall number of dies performing Caching and an overall size of dies performing Copy Back is a fraction of a ratio between programming speeds of the MSB and the LSB programming.

7. The method according to claim 6, wherein the fraction is one half.

8. The method according to claim 1, wherein the cache memory pages and the first level target pages are MSB pages.

9. The method according to claim 8, wherein the second level target pages are LSB pages.

10. The method according to claim 9, wherein the MSB programming of the first and second input data units occur in parallel to each other.

11. The method according to claim 9, wherein the MSB programming of the second input data units and the first input data units occur in a partially overlapping manner.

12. The method according to claim 1, wherein the receiving the multiple input data units from the host computer includes continuously receiving additional ones of the multiple input data units while MSB programming the first input data units.

13. A method for accelerating programming of data, comprising: receiving multiple input data units by a memory controller and from a host computer;

14. The method according to claim 13, further comprising allocating cache memory pages and target pages.

15. The method according to claim 14, wherein the allocating is responsive to programming speeds of the MSB and LSB programming.

16. The method according to claim 13, wherein the cache memory pages and the first level target pages are MSB pages, and wherein the second level target pages are LSB pages.

17. A non-transitory computer readable medium that stores instructions that once executed by a computer causes the computer to execute the stages of: receiving multiple input data units that were sent from a host computer; wherein the input data units comprises first and second input data units;most significant bit (MSB) programming the first input data units to cache memory MSB pages and MSB programming the second input data units to MSB target memory pages; andapplying a copy back operation that comprises retrieving the first input data units from the cache memory MSB pages and least significant bit (LSB) programming the retrieved first input data units to LSB target memory pages;wherein any target page out of the MSB target memory pages and the LSB target memory pages differs from a cache memory MSB page;wherein the MSB programming is faster than the LSB programming; andwherein a ratio between an overall number of dies performing the caching and an overall size of dies performing the copy back operation is a fraction of a ratio between programming speeds of the MSB and the LSB programming.

18. A memory controller, comprising; a control unit; andan interface;wherein the interface is arranged to receive multiple input data units from a host computer;wherein the input data units comprises first and second input data units; wherein the control unit is arranged to: instruct a programming circuit of a flash memory module to perform most significant bit (MSB) programming the first input data units to cache memory pages of the flash memory module and to perform MSB programming of the second input data units to first level target memory pages of the flash memory module; andinstruct a copy back circuit of the flash memory module to apply a copy back operation that comprises retrieving the first input data units from the cache memory pages and least significant bit (LSB) programming the retrieved first input data units to second level target memory pages;wherein any target page out of the first level target memory pages and the second level target memory pages differs from a cache memory page;wherein the MSB programming is faster than the LSB programming; andwherein a ratio between an overall number of dies performing the copy back operation and an overall number of dies caching exceeds one.

19. The memory controller according to claim 18, wherein the cache memory pages and the first level target pages are MSB pages, and wherein the second level target pages are LSB pages.

20. A flash memory module, comprising: an interface;a copy back circuit;a programming circuit; andflash memory pages; wherein the interface is arranged to receive multiple input data units from a memory controller; wherein the input data units comprise first and second input data units;wherein the programming circuit is arranged to perform most significant bit (MSB) programming the first input data units to cache memory pages of the flash memory module and to perform MSB programming of the second input data units to first level target memory pages of the flash memory module; andwherein the copy back circuit is arranged to apply a copy back operation that comprises retrieving the first input data units from the cache memory pages and least significant bit (LSB) programming the retrieved first input data units to second level target memory pages;wherein any target page out of the first level target memory pages and the second level target memory pages differs from a cache memory page;wherein the MSB programming is faster than the LSB programming; andwherein a ratio between an overall number of dies performing the copy back operation and an overall number of dies caching exceeds one.