with multilevel cache hierarchies

Industry

CPC
G06F12/0811

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0811with multilevel cache hierarchies

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for managing data bias in a graphics processin...
- Patent number 12,260,470
- Issue date Mar 25, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disk caching and/or tiering with device internal busy information
- Patent number 12,253,945
- Issue date Mar 18, 2025
- Intel Corporation
- Sanjeev Trika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for cache management in a network device
- Patent number 12,253,946
- Issue date Mar 18, 2025
- Telefonaktiebolaget LM Ericsson (publ)
- Anju Thomas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-block cache fetch techniques
- Patent number 12,248,399
- Issue date Mar 11, 2025
- Apple Inc.
- Winnie W. Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for memory bandwidth allocation
- Patent number 12,248,400
- Issue date Mar 11, 2025
- Alibaba (China) Co., Ltd.
- Lide Duan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for image exploration using areas of interest
- Patent number 12,249,070
- Issue date Mar 11, 2025
- Dell Products L.P.
- Ofir Ezrielev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-up table initialize
- Patent number 12,242,852
- Issue date Mar 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache locality when using repurposed cache memory
- Patent number 12,235,765
- Issue date Feb 25, 2025
- NVIDIA Corporation
- Ariel Szapiro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management device for performing DMA operations between a ma...
- Patent number 12,229,051
- Issue date Feb 18, 2025
- Intel Germany GmbH & Co. KG
- Ritesh Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for addressing memory caches
- Patent number 12,222,871
- Issue date Feb 11, 2025
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and method designating an in-core cache of a hierarchical...
- Patent number 12,222,860
- Issue date Feb 11, 2025
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Weilin Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore, multibank, fully concurrent coherence controller
- Patent number 12,223,165
- Issue date Feb 11, 2025
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intermediate cache management for non-uniform memory architecture
- Patent number 12,216,590
- Issue date Feb 4, 2025
- Advanced Micro Devices, Inc.
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive remote atomics
- Patent number 12,216,579
- Issue date Feb 4, 2025
- Intel Corporation
- Carl J. Beckmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor data cache with shared mid-level cache and low-level cache
- Patent number 12,210,457
- Issue date Jan 28, 2025
- Marvell Asia Pte, Ltd.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inter-cluster shared data management in sub-NUMA cluster
- Patent number 12,210,446
- Issue date Jan 28, 2025
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System probe aware last level cache insertion bypassing
- Patent number 12,204,454
- Issue date Jan 21, 2025
- Advanced Micro Devices, Inc.
- Paul James Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory tiering techniques in computing systems
- Patent number 12,204,408
- Issue date Jan 21, 2025
- Microsoft Technology Licensing, LLC
- Ishwar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic cache resource allocation for quality of service and system...
- Patent number 12,204,450
- Issue date Jan 21, 2025
- Mediatek Inc.
- Yu-Pin Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilevel memory system with copied error detection bits
- Patent number 12,204,407
- Issue date Jan 21, 2025
- Texas Instruments Incorporated
- Ruchi Shankar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for storage virtualization
- Patent number 12,204,451
- Issue date Jan 21, 2025
- Dynavisor, Inc.
- Sreekumar Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory pipeline control in a hierarchical memory system
- Patent number 12,197,332
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY TIERING TECHNIQUES IN COMPUTING SYSTEMS
- Publication number 20250110829
- Publication date Apr 3, 2025
- Microsoft Technology Licensing, LLC
- Ishwar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NAMESPACE CHANGE PROPAGATION IN NON-VOLATILE MEMORY DEVICES
- Publication number 20250110868
- Publication date Apr 3, 2025
- Micron Technology, Inc.
- Alex Frolikov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REMOTE ACCELERATION FOR DATA DEPENDENT ADDRESS CALCULATION
- Publication number 20250110877
- Publication date Apr 3, 2025
- ADVANCED MICRO DEVICES, INC.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TEC...
- Publication number 20250112204
- Publication date Apr 3, 2025
- Intel Corporation
- Adel Elsherbini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CACHE FILL PRIORIZATION
- Publication number 20250110876
- Publication date Apr 3, 2025
- Intel Corporation
- Ashmita Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAST LEVEL CACHE HIERARCHY IN CHIPLET BASED PROCESSORS
- Publication number 20250110875
- Publication date Apr 3, 2025
- Srikanth Reddy Gruddanti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
- Publication number 20250103502
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20250103503
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scoreboard for Register Data Cache
- Publication number 20250103493
- Publication date Mar 27, 2025
- Apple Inc.
- Winnie W. Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT FILL AND BYTE MERGE
- Publication number 20250103494
- Publication date Mar 27, 2025
- International Business Machines Corporation
- Scot RIDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Control to Preserve Register Data
- Publication number 20250094357
- Publication date Mar 20, 2025
- Apple Inc.
- Jonathan M. Redshaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20250094044
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR MANAGING STORAGE OPERATIONS FOR MULTIPLE HOSTS COUPLED...
- Publication number 20250086109
- Publication date Mar 13, 2025
- NetApp, Inc.
- ABHIJEET GOLE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE RING CACHE ARCHITECTURE
- Publication number 20250077428
- Publication date Mar 6, 2025
- ARKOSE LABS HOLDINGS, INC.
- Du Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Graphics Processor Cache for Data from Multiple Memory Spaces
- Publication number 20250068564
- Publication date Feb 27, 2025
- Apple Inc.
- Dimitri Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ADJUSTMENT OF DATA STORAGE FOR ENHANCED DATA RETENTION
- Publication number 20250060909
- Publication date Feb 20, 2025
- Micron Technology, Inc.
- Roy Leonard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE CACHE FOR COHERENT SYSTEM
- Publication number 20250060873
- Publication date Feb 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...
- Publication number 20250061060
- Publication date Feb 20, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECTORY-LESS SNOOP OFFLOAD OF A HIGHER LEVEL CACHE MANAGEMENT AGE...
- Publication number 20250053514
- Publication date Feb 13, 2025
- International Business Machines Corporation
- Scot RIDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20250036411
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZED SCRUBBING TRANSACTIONS
- Publication number 20250036522
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY POOLING BANDWIDTH MULTIPLIER USING FINAL LEVEL CACHE SYSTEM
- Publication number 20250028643
- Publication date Jan 23, 2025
- FLC Technology Group, Inc.
- Sehat Sutardja
- G06 - COMPUTING CALCULATING COUNTING

with multilevel cache hierarchies

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for multi-banked victim cache with dual datapath

Apparatus and method for managing data bias in a graphics processin...

Disk caching and/or tiering with device internal busy information

Method and system for cache management in a network device

Multi-block cache fetch techniques

Systems and methods for memory bandwidth allocation

System and method for image exploration using areas of interest

Data initialization techniques

Look-up table initialize

Cache locality when using repurposed cache memory

Memory management device for performing DMA operations between a ma...

Methods and apparatuses for addressing memory caches

Processor and method designating an in-core cache of a hierarchical...

Multicore, multibank, fully concurrent coherence controller

Intermediate cache management for non-uniform memory architecture

Adaptive remote atomics

Atomic compare and swap in a coherent cache system

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Processor data cache with shared mid-level cache and low-level cache

Inter-cluster shared data management in sub-NUMA cluster

System probe aware last level cache insertion bypassing

Graphics processor data access and sharing

Memory tiering techniques in computing systems

Dynamic cache resource allocation for quality of service and system...

Multilevel memory system with copied error detection bits

Method and system for storage virtualization

Memory pipeline control in a hierarchical memory system

Methods and apparatus to reduce bank pressure using aggressive writ...

Patents Applicationslast 30 patents

MEMORY TIERING TECHNIQUES IN COMPUTING SYSTEMS

NAMESPACE CHANGE PROPAGATION IN NON-VOLATILE MEMORY DEVICES

REMOTE ACCELERATION FOR DATA DEPENDENT ADDRESS CALCULATION

DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TEC...

DYNAMIC CACHE FILL PRIORIZATION

LAST LEVEL CACHE HIERARCHY IN CHIPLET BASED PROCESSORS

MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

ZERO LATENCY PREFETCHING IN CACHES

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

Scoreboard for Register Data Cache

CONCURRENT FILL AND BYTE MERGE

Cache Control to Preserve Register Data

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

MULTICORE SHARED CACHE OPERATION ENGINE

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

METHODS FOR MANAGING STORAGE OPERATIONS FOR MULTIPLE HOSTS COUPLED...

DOUBLE RING CACHE ARCHITECTURE

Graphics Processor Cache for Data from Multiple Memory Spaces

DYNAMIC ADJUSTMENT OF DATA STORAGE FOR ENHANCED DATA RETENTION

CONFIGURABLE CACHE FOR COHERENT SYSTEM

METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...

DIRECTORY-LESS SNOOP OFFLOAD OF A HIGHER LEVEL CACHE MANAGEMENT AGE...

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

PADDING IN A STREAM OF MATRIX ELEMENTS

PARALLELIZED SCRUBBING TRANSACTIONS

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

MEMORY POOLING BANDWIDTH MULTIPLIER USING FINAL LEVEL CACHE SYSTEM