with multilevel cache hierarchies

Industry

CPC
G06F12/0811

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0811with multilevel cache hierarchies

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Prefetch management in a hierarchical cache system
- Patent number 12,321,277
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implicit fence for write messages
- Patent number 12,321,310
- Issue date Jun 3, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence for memory controller
- Patent number 12,321,270
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed system level cache
- Patent number 12,321,271
- Issue date Jun 3, 2025
- Imagination Technologies Limited
- Mark Landers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascading execution of atomic operations
- Patent number 12,321,273
- Issue date Jun 3, 2025
- Advanced Micro Devices, Inc.
- Jimshed Mirza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slot/sub-slot prefetch architecture for multiple memory requestors
- Patent number 12,321,282
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Updating related data in multi-cache systems
- Patent number 12,314,182
- Issue date May 27, 2025
- ARM Limited
- Olof Henrik Uhrenholt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques using a unified cache for storing and accessing translat...
- Patent number 12,314,186
- Issue date May 27, 2025
- Dell Products L.P.
- Christopher Seibel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-up table write
- Patent number 12,314,720
- Issue date May 27, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-cache based digital output generation
- Patent number 12,306,756
- Issue date May 20, 2025
- AUX MODE INC.
- Adam Rumanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bulk memory initialization
- Patent number 12,298,906
- Issue date May 13, 2025
- Huawei Technologies Co., Ltd.
- Yuejian Xie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for altering the path of data movement for larg...
- Patent number 12,299,301
- Issue date May 13, 2025
- QUALCOMM Incorporated
- Hithesh Hassan Lepaksha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory allocation in a hierarchical memory system
- Patent number 12,293,227
- Issue date May 6, 2025
- Telefonaktiebolaget LM Ericsson (publ)
- Amir Roozbeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced data reliability in multi-level memory cells
- Patent number 12,292,831
- Issue date May 6, 2025
- Micron Technology, Inc.
- Deping He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for managing a cache memory
- Patent number 12,292,830
- Issue date May 6, 2025
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Olivier Savry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor core simulator including trace-based coherent cache drive...
- Patent number 12,293,137
- Issue date May 6, 2025
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage device for collecting optimal debugging data and system inc...
- Patent number 12,287,736
- Issue date Apr 29, 2025
- SK Hynix Inc.
- Seon Ju Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level caching for dynamic deep learning models
- Patent number 12,288,141
- Issue date Apr 29, 2025
- Intel Corporation
- Yamini Nimmagadda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cryptographic computing using encrypted base addresses and used in...
- Patent number 12,282,567
- Issue date Apr 22, 2025
- Intel Corporation
- David M. Durham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for adaptive hybrid hardware pre-fetch
- Patent number 12,282,429
- Issue date Apr 22, 2025
- Huawei Technologies Co., Ltd.
- Elnaz Ebrahimi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective speculative prefetch requests for a last-level cache
- Patent number 12,282,428
- Issue date Apr 22, 2025
- Advanced Micro Devices, Inc.
- Tarun Nakra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application mapping on hardened network-on-chip (NoC) of field-prog...
- Patent number 12,277,060
- Issue date Apr 15, 2025
- Intel Corporation
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory address compression within an execution trace
- Patent number 12,277,069
- Issue date Apr 15, 2025
- Microsoft Technology Licensing, LLC
- Jordi Mola
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing mirror data transmission amount b...
- Patent number 12,277,059
- Issue date Apr 15, 2025
- SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.
- Xiangfei Kong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive configuration of address translation cache
- Patent number 12,277,068
- Issue date Apr 15, 2025
- Mellanox Technologies, Ltd.
- Gal Shalom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache replacement policy optimization for producer-consumer flows
- Patent number 12,277,071
- Issue date Apr 15, 2025
- Microsoft Technology Licensing, LLC
- Ramakrishna Huggahalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache size change
- Patent number 12,271,314
- Issue date Apr 8, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
- Publication number 20250181238
- Publication date Jun 5, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR HANDLING PREFETCHING
- Publication number 20250181508
- Publication date Jun 5, 2025
- ARM Limited
- Natalya BONDARENKO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR STORAGE VIRTUALIZATION
- Publication number 20250173266
- Publication date May 29, 2025
- Dynavisor, Inc.
- Sreekumar Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20250173308
- Publication date May 29, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGEMENT OF PROGRAMMING MODE TRANSITIONS TO ACCOMMODATE A CONSTAN...
- Publication number 20250165403
- Publication date May 22, 2025
- Micron Technology, Inc.
- Sanjay Subbarao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY MEMORY ACCESS FOR CPUS IN AUTONOMOUS VEHICLES
- Publication number 20250156327
- Publication date May 15, 2025
- Apollo Autonomous Driving USA LLC
- ZHENWEI YU
- B60 - VEHICLES IN GENERAL
Information Patent Application
DATA INITIALIZATION TECHNIQUES
- Publication number 20250156371
- Publication date May 15, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING A SYSTEM LEVEL CACHE
- Publication number 20250156326
- Publication date May 15, 2025
- NVIDIA Corporation
- Ashutosh PANDEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TIERED CACHE SYSTEM
- Publication number 20250147887
- Publication date May 8, 2025
- PAYPAL, INC.
- Sharmili Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE COHERENCE SIGNALING PROTOCOL
- Publication number 20250147888
- Publication date May 8, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O CACHE PARTITIONING
- Publication number 20250147886
- Publication date May 8, 2025
- Intel Corporation
- Zhan Xue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DEVICE SUPPORTING WRITEBACK SKIPPING AND METHOD OF OPERA...
- Publication number 20250147885
- Publication date May 8, 2025
- Samsung Electronics Co., Ltd.
- Moongyung KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Level Caching of User Level Thread Stacks for User Level T...
- Publication number 20250130942
- Publication date Apr 24, 2025
- International Business Machines Corporation
- Oluwatobi Ajila
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REDUCING MIRROR DATA TRANSMISSION AMOUNT B...
- Publication number 20250123967
- Publication date Apr 17, 2025
- Suzhou MetaBrain Intelligent Technology Co., Ltd
- Xiangfei KONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION PROGRAMMING INTERFACE TO INVALIDATE INFORMATION
- Publication number 20250123969
- Publication date Apr 17, 2025
- NVIDIA Corporation
- Harold Carter Edwards
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION PROGRAMMING INTERFACE TO UPDATE INFORMATION
- Publication number 20250123966
- Publication date Apr 17, 2025
- NVIDIA Corporation
- Harold Carter Edwards
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Micro-Architecture Support for Decompression on Core
- Publication number 20250117329
- Publication date Apr 10, 2025
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING SPARSE COMPUTATION MECHANISM
- Publication number 20250117873
- Publication date Apr 10, 2025
- Intel Corporation
- Eriko Nurvitadhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY TIERING TECHNIQUES IN COMPUTING SYSTEMS
- Publication number 20250110829
- Publication date Apr 3, 2025
- Microsoft Technology Licensing, LLC
- Ishwar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NAMESPACE CHANGE PROPAGATION IN NON-VOLATILE MEMORY DEVICES
- Publication number 20250110868
- Publication date Apr 3, 2025
- Micron Technology, Inc.
- Alex Frolikov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REMOTE ACCELERATION FOR DATA DEPENDENT ADDRESS CALCULATION
- Publication number 20250110877
- Publication date Apr 3, 2025
- ADVANCED MICRO DEVICES, INC.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CACHE FILL PRIORIZATION
- Publication number 20250110876
- Publication date Apr 3, 2025
- Intel Corporation
- Ashmita Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAST LEVEL CACHE HIERARCHY IN CHIPLET BASED PROCESSORS
- Publication number 20250110875
- Publication date Apr 3, 2025
- Srikanth Reddy Gruddanti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TEC...
- Publication number 20250112204
- Publication date Apr 3, 2025
- Intel Corporation
- Adel Elsherbini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
- Publication number 20250103502
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING

with multilevel cache hierarchies

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Prefetch management in a hierarchical cache system

Methods and apparatus to facilitate atomic operations in victim cache

Implicit fence for write messages

Hardware coherence for memory controller

Distributed system level cache

Cascading execution of atomic operations

Slot/sub-slot prefetch architecture for multiple memory requestors

Victim cache with write miss merging

Updating related data in multi-cache systems

Techniques using a unified cache for storing and accessing translat...

Look-up table write

Multi-cache based digital output generation

Bulk memory initialization

Methods and systems for altering the path of data movement for larg...

Memory allocation in a hierarchical memory system

Enhanced data reliability in multi-level memory cells

Method for managing a cache memory

Write merging on stores with different privilege levels

Processor core simulator including trace-based coherent cache drive...

Storage device for collecting optimal debugging data and system inc...

Multi-level caching for dynamic deep learning models

Cryptographic computing using encrypted base addresses and used in...

Systems and methods for adaptive hybrid hardware pre-fetch

Selective speculative prefetch requests for a last-level cache

Application mapping on hardened network-on-chip (NoC) of field-prog...

Memory address compression within an execution trace

Method and apparatus for reducing mirror data transmission amount b...

Adaptive configuration of address translation cache

Cache replacement policy optimization for producer-consumer flows

Cache size change

Patents Applicationslast 30 patents

MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER

TECHNIQUE FOR HANDLING PREFETCHING

METHOD AND SYSTEM FOR STORAGE VIRTUALIZATION

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

MANAGEMENT OF PROGRAMMING MODE TRANSITIONS TO ACCOMMODATE A CONSTAN...

LOW LATENCY MEMORY ACCESS FOR CPUS IN AUTONOMOUS VEHICLES

DATA INITIALIZATION TECHNIQUES

MANAGING A SYSTEM LEVEL CACHE

MULTI-TIERED CACHE SYSTEM

HARDWARE COHERENCE SIGNALING PROTOCOL

I/O CACHE PARTITIONING

ELECTRONIC DEVICE SUPPORTING WRITEBACK SKIPPING AND METHOD OF OPERA...

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

Multiple Level Caching of User Level Thread Stacks for User Level T...

METHOD AND APPARATUS FOR REDUCING MIRROR DATA TRANSMISSION AMOUNT B...

APPLICATION PROGRAMMING INTERFACE TO INVALIDATE INFORMATION

APPLICATION PROGRAMMING INTERFACE TO UPDATE INFORMATION

Instruction and Micro-Architecture Support for Decompression on Core

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

MULTI-TILE MEMORY MANAGEMENT

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

MACHINE LEARNING SPARSE COMPUTATION MECHANISM

MEMORY TIERING TECHNIQUES IN COMPUTING SYSTEMS

NAMESPACE CHANGE PROPAGATION IN NON-VOLATILE MEMORY DEVICES

REMOTE ACCELERATION FOR DATA DEPENDENT ADDRESS CALCULATION

DYNAMIC CACHE FILL PRIORIZATION

LAST LEVEL CACHE HIERARCHY IN CHIPLET BASED PROCESSORS

DISAGGREGATED PROCESSOR ARCHITECTURES USING SELECTIVE TRANSFER TEC...

MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION