BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic view of a conventional thin film transistor array substrate.
FIG. 2 is a partially schematic cross-sectional view of a scan line in a conventional peripheral area.
FIG. 3 is a schematic view of an active device array substrate according to a first embodiment of the present invention.
FIG. 4 is a partially schematic cross-sectional view of a peripheral area for the active device array substrate according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view of a first filler according to the first embodiment of the present invention.
FIG. 6 is a partially schematic cross-sectional view of the peripheral area for another active device array substrate according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view of a second filler according to the first embodiment of the present invention.
FIG. 8 is a partially schematic cross-sectional view of a peripheral area of an active device array substrate according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view of the filler according to the second embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
First Embodiment
FIG. 3 is a schematic view of an active device array substrate according to a first embodiment of the present invention, and FIG. 4 is a partially schematic cross-sectional view of a peripheral area for the active device array substrate according to the first embodiment of the present invention. Referring to FIGS. 3 and 4, the active device array substrate 200 of the present invention has a display area A and a peripheral area B outside the display area A. The active device array substrate 200 comprises a substrate 210, a plurality of pixel units 212, a plurality of first lead wires 220, an insulating layer 230, a plurality of second lead wires 240, a plurality of pads 245 and a passivation layer 250. The pixel units 212 are arranged into an array in the display area A of the substrate 210, and the first lead wires 220 and the second lines 240 are disposed in the peripheral area B and electrically connected to the pads 245. The first lead wires 220 and the second lead wires 240 are electrically connected to the pixel units 212 in the display area A respectively. Moreover, the first lead wires 220 are covered by the insulating layer 230, and the second lead wires 240 are located between the insulating layer 230 and the passivation layer 250.
Particularly, the first lead wires 220 may be the scan lines, and the second lead wires 240 may be the data lines. In practice, the voltage signal is transmitted into the pixel units 212 through the first lead wires 220 and the second lead wires 240. It should be noted that, the pixel unit 212 is illustrated by taking the pixel unit 212 of the liquid crystal display panel as an example. Of course, the pixel unit 212 may also be the pixel unit 212 of the organic electro-luminescence display (OELD), which thus is not limited herein.
As known from FIG. 4 that, the first lead wire 220 in the peripheral area B of the substrate 210 has two opposite first tips 220a, and the first tips 220a are separated apart from each other for a first interval L1. It should be noted that, the first tips 220 of the present invention has the electrostatic discharge function. In practice, the pads 245 are electrically connected to the shorting ring (not shown), and the first tips 220 may be located between the shorting ring and the pads 245, or between the pads 245 and the display area A. Of course, the position of the first tips 220a may be adjusted appropriately depending on the requirements, which thus is not limited herein.
It should be noted that, the first lead wires 220 are covered by the insulating layer 230. The insulating layer 230 has at least a first opening C1 being larger than the first interval L1, so as to expose the two opposite first tips 220a. In practice, the first opening C1 may be formed by etching the insulating layer 230.
It should be mentioned that, the two opposite first tip 220a may form a capacitor, according to:
V=Q/C
V: voltage difference
Q: charge quantity
C: capacitance value,
if the charge quantity Q is the same, the smaller the capacitance value C is, the bigger the voltage difference V for the two opposite first tips 220a is. The capacitance value C is in direct proportion to the dielectric constant of the dielectric material in the capacitor. The two opposite first tips 220 are exposed to the air through the first opening C1, and the dielectric constant of the conventional insulating layer silicon nitride (SiNx) 130 is about seven times of the dielectric constant of the air. Therefore, the voltage difference V between the two opposite first tips 220a of the present invention is relatively large, such that the electrostatic charges are accumulated at the first tips 220a, and thereby being effectively discharged. Therefore, the elements on the active device array substrate 200 are protected from being damaged by the electrostatic discharge (ESD).
Moreover, the active device array substrate 200 of the present invention further comprises a first filler 260 (as shown in FIG. 5). The first filler 260 may be selectively filled into the first opening C1, and the material of the first filler 260 may be an organic insulating material, benzocyclobutene (BCB) or silicon oxide (SiO2), as long as the dielectric constant of the first filler 260 is smaller than that of the insulating layer 230, which is not limited herein.
In order to further protect the active device array substrate 200 of the present invention from being damaged by the electrostatic discharge, the second lead wire 240 has two opposite second tips 240a (as shown in FIG. 6), and the two opposite second tips 240a are separated apart from each other for a second interval L2. Moreover, the second lead wires 240 are covered by the passivation layer 250 having at least a second opening C2 with the covering scope being larger than that of the second interval L2, so as to expose the two opposite second tips 240a. As a result, the electrostatic charges are also accumulated at the first tips 220a, and thereby being effectively discharged, so as to protect the active device array substrate 200 from being damaged by the electrostatic discharge.
Moreover, the active device array substrate 200 of the present invention further comprises a second filler 270 (as shown in FIG. 7). The second filler 270 may be selectively filled into the second opening C2, and the material of the second filler 270 may be an organic insulating material, benzocyclobutene (BCB) or silicon oxide (SiO2), as long as the dielectric constant of the second filler 270 is smaller than that of the passivation layer 250, which is not limited herein.
Second Embodiment
FIG. 8 is a partially schematic cross-sectional view of a peripheral area of an active device array substrate according to a second embodiment of the present invention. Referring to FIG. 8, the second embodiment is similar to the first embodiment, the main difference therein is that: the active device array substrate 200 of the present invention only forms two opposite electrostatic discharge tips 240b on the second lead wires 240, and the passivation layer 250 has at least one opening C3 for exposing the two opposite electrostatic discharge tips 240b. Particularly, the two opposite electrostatic discharge tips 240b are separated apart from each other for an interval L3, and the covering scope of the opening C3 is larger than the interval L3 between the electrostatic discharge tips 240b.
The active device array substrate 200 of the present invention further comprises a filler 280 (as shown in FIG. 9). The filler 280 may be selectively filled into the opening C3, and the material of the filler 280 may be an organic insulating material, benzocyclobutene (BCB) or silicon oxide (SiO2), as long as the dielectric constant of the filler 280 is smaller than that of the passivation layer 250, which is not limited herein.
In summary, in the active device array substrate of the present invention, the insulating layer has the first opening for exposing the two opposite first tips. Because the dielectric constant of the air is relatively low, when the charge quantity is the same, the voltage difference for the two opposite first tips is relatively high. In this manner, the electrostatic charges accumulated at the first tip are effectively discharged at the first opening, so as to effectively protect the active device array substrate from being damaged by the electrostatic discharge. The active device array substrate of the present invention may only form the opening in the passivation layer for exposing the electrostatic discharge tips, and may also form both the first opening in the insulation layer and the second opening in the passivation layer, so as to further protect the active device array substrate from being damaged by the electrostatic discharge.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Patent Application
20070272983
