BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram showing a conventional ESD protection circuit of an active matrix display device;
FIG. 2 is a schematic diagram showing an active matrix device having an ESD protection circuit according to a preferred embodiment of the present invention;
FIG. 3 is a schematic diagram showing an active matrix device having an ESD protection circuit according to another preferred embodiment of the present invention;
FIG. 4 is a schematic diagram showing an active matrix device having an ESD protection circuit according to another preferred embodiment of the present invention; and
FIG. 5 is a schematic diagram showing an active matrix device having an ESD protection circuit according to another preferred embodiment of the present invention.
DESCRIPTION OF THE EMBODIMENTS
Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIG. 2 is a schematic diagram showing an active matrix device having an ESD protection circuit according to a preferred embodiment of the present invention. Referring to FIG. 2, an active matrix device 200 comprises an active region 210 and an ESD protection circuit 220. The active region 210 comprises a plurality of scan lines SL and a plurality of data lines DL. A third voltage V3 and a fourth voltage V4 are the average voltages applied to the scan lines SL and the data lines DL respectively, to control the display status of each pixel. Generally speaking, the third voltage V3 is −15V, and the fourth voltage V4 is 2.5V. The ESD protection circuit 220 comprises a first power line 221, a second power line 222, a plurality of first diodes 223 and a plurality of second diodes 224. In this preferred embodiment of the present invention, the first power line 221 comprises a ring type wire 221a and a first voltage V1 is applied to the first power line 221; and the second power line 222 also comprises a ring type wire 222a and a second voltage V2 is applied to the second power line 222, wherein the first voltage V1 is not equal to the second voltage V2. In one example of the present invention, the first voltage V1 is a positive voltage and the second voltage V2 is a negative voltage. For example, the positive voltage is 10V and the negative voltage is −20V. Each of the first diodes 223 has a positive terminal and a negative terminal. The positive terminals of the first diodes 223 are electrically connected to the scan lines SL or the data lines DL, and the negative terminals of the first diodes 223 are electrically connected to the first power line 221. Similarly, each of the second diodes 224 has a positive terminal and a negative terminal. The positive terminals of the second diodes 224 are electrically connected to the second power line 222, and the negative terminals of the second diodes 224 are electrically connected to the scan lines SL or the data lines DL.
When a positive ESD voltage is applied to the scan line SL suddenly, the ESD current is conducted to the first power line 221 through the first diode 223. Similarly, when a negative ESD voltage is suddenly applied to the scan line SL, the ESD current is conducted to the second power line 222 through the second diode 224. Furthermore, the second power line 222 can be connected to ground voltage. Besides, when a positive ESD voltage is applied to the data line DL, the ESD current is conducted to the first power line 221 through the first diode 223. Similarly, when a negative ESD voltage is applied to the data line DL, the ESD current is conducted to the second power line 222 through the second diode 224. The present invention utilizes the arrangement in which the first diodes 223 are connected between the scan lines SL/data lines DL and the first power line 221; and the second diodes 224 are connected between the second power line 222 and the scan lines SL/data lines DL, for protecting the devices and circuits of the active matrix device 200 from being damaged by the ESD zap. Although there is very small leakage current flowing through the first diode 223 or the second diode 224 when a reverse voltage exists across the first diode 223 or the second diode 224, yet the leakage current flowing through the first diode 223 or the second diode 224 is comparatively smaller than the leakage current occurring in the conventional ESD protection circuit, and thus the extra power consumption can be decreased.
In this embodiment, the ESD protection circuit 220 comprises a plurality of first diodes 223 and a plurality of second diodes 224. However, even if the ESD protection circuit 220 only comprises one first diode 223 and one second diode 224, it still can provide the ESD protection function, so that the number of the first diodes 223 and that of the second diodes 224 are not limited thereto in the present invention.
Besides the ring type wire 221a of the first power line 221 and the type wire 222a of the second power line 222 as shown in FIG. 2, the first power line 221 may comprise a plurality of discrete wires (not shown) to which the first voltage V1 is applied, wherein the negative terminals of the first diodes 223 are electrically connected to one of the discrete wires, and the positive terminals of the first diodes 223 are still electrically connected to the scan lines SL or the data lines DL. Similarly, the second power line 222 may comprise a plurality of discrete wires (not shown) to which the second voltage V2 is applied, wherein the positive terminals of the second diodes 224 are electrically connected to one of the discrete wires, and the negative terminals of the second diodes 224 are still electrically connected to the scan lines SL or data lines DL. Because the discrete wires are electrically connected to the same power line, this design also has the ESD protection function.
In one embodiment of the present invention, different voltages are applied to the scan lines SL, the data lines DL, the first power line 221 and the second power line 222, and satisfy the following formula: V1≧V4>V3≧V2.
Referring to FIG. 3, FIG. 3 is a schematic diagram showing an active matrix device having an ESD protection circuit according to another preferred embodiment of the present invention. Such as shown in FIG. 3, the active matrix device 200′ is similar to the active matrix device 200 as shown in FIG. 2, but the ESD protection circuit 220′ of the active matrix device 200′ further comprises a plurality of third diodes 225, wherein a positive terminal of each of the third diodes 225 is electrically connected to the first power line 221, and a negative terminal of each of the third diodes 225 is electrically connected to the second power line 222, and there is a bias current flowing through the third diode 225 between the first power line 221 and the second power line 222. Therefore, when a positive ESD voltage is applied to the scan line SL or data line DL suddenly, a portion of the ESD current is conducted to the first power line 221 through the first diodes 223, and the other portion of the ESD current is conducted to the second power line 222 through the third diodes 225, thereby further preventing the devices and circuit of the active matrix device 200′ from being damaged by the ESD zap. Similarly, the number of the third diodes 225 is not limited thereto in the present invention.
Referring to FIG. 4, FIG. 4 is a schematic diagram showing an active matrix device having an ESD protection circuit according to another preferred embodiment of the present invention. Such as shown in FIG. 4, the active matrix device 200″ is similar to the active matrix device 200 as shown in FIG. 2, wherein the first diodes 223 and the second diodes 224 shown in FIG. 2 are replaced by first transistor devices 226 and second transistor devices 227, respectively. Each of the first transistor devices 226 comprises a first gate, a first drain and a first source. The first gate and the first drain are electrically connected to the scan line SL or the data line DL, and the first source is electrically connected to the first power line 221. The first gate is coupled with the first drain to form a pseudo-diode, such that the first diode 223 shown in FIG. 2 can be replaced by the first transistor device 226. Similarly, each of the second transistor devices 227 comprises a second gate, a second drain and a second source. The second gate and the second drain are electrically connected to the second power line 222, and the second source is electrically connected to the scan line SL or the data line DL. The second gate is coupled with the second drain to form a pseudo-diode, such that the second diode 224 shown in FIG. 2 can be replaced by the second transistor device 227.
When a positive ESD voltage is applied to the scan line SL suddenly, the ESD current is conducted to the first power line 221 through the first transistor device 226. Similarly, when a negative ESD voltage is suddenly applied to the scan line SL, the ESD current is conducted to the second power line 222 through the second transistor device 227. Furthermore, the second power line 222 can be connected to ground voltage. Besides, when a positive ESD voltage is applied to the data line DL, the ESD current is conducted to the first power line 221 through the first transistor device 226. Similarly, when a negative ESD voltage is applied to the data line DL, the ESD current is conducted to the second power line 222 through the second transistor device 227. The present invention utilizes the arrangement in which the first transistor devices 226 are connected between the scan lines SL/data lines DL and the first power line 221; and the second transistor devices 227 are connected between the second power line 222 and the scan lines SL/data lines DL, for protecting the devices and circuits of the active matrix device 200″ from being damaged by the ESD zap. Although there is very small leakage current flowing through the first transistor device 226 or the second transistor device 227 when a reverse voltage exists across the first transistor device 226 or the second transistor device 227, the leakage current flowing through the first transistor device 226 or the second transistor device 227 is comparatively smaller than the leakage current occurring in the conventional ESD protection circuit, and thus the extra power consumption can be decreased.
Referring FIG. 5, FIG. 5 is a schematic diagram showing an active matrix device having an ESD protection circuit according to another preferred embodiment of the present invention. Such as shown in FIG. 5, the active matrix device 200′″ is similar to the active matrix device 200″ shown in FIG. 4, but the ESD protection circuit 220′″ of the active matrix device 200′″ further comprises a plurality of third transistor devices 228. Each of the third transistor devices 228 comprises a third gate, a third source and a third drain. The third gate and the third drain of the third transistor device 228 are electrically connected to the first power line 221, and the third source of the third transistor device 228 is electrically connected to the second power line 222, and a bias current flows through the third transistor device 228 between the first power line 221 and the second power line 222. Therefore, when a positive ESD voltage is applied to the scan line SL or data line DL suddenly, a portion of the ESD current is conducted to the first power line 221 through the first transistor devices 226, and the other portion of the ESD current is conducted to the second power line 222 through the third transistor devices 228, so as to further prevent the devices and circuit of the active matrix device 200′″ from being damaged by the ESD zap. Similarly, the number of the third transistor devices 228 is not limited thereto in the present invention.
The above-mentioned active matrix device having the ESD protection function can be a display device, such as a LCD, an OLED display or an E-ink display, or a sensor, such as a photo sensor or an X-ray sensor, but the application of the active matrix device is not limited thereto in the present invention.
In summary, the ESD protection circuit comprises the first power line, the second power line, the first diodes electrically connected between the scan lines/data lines and the first power line, and the second diodes electrically connected between the second power line and the scan lines/data lines. When a positive or negative ESD voltage is applied to the scan lines or the data lines, the ESD current is conducted to the first power line or the second power line through the first diodes or the second diodes, so as to protect the devices and circuits of the active matrix device from being damaged by the ESD zap. Although there is very small leakage current flowing through the first diode or the second diode when a reverse voltage exists across the first diode or the second diode, the leakage current flowing through the first diode or the second diode is comparatively smaller than the leakage current existing in the conventional ESD protection circuit, and thus the extra power consumption can be decreased. Besides, the present invention may utilize the arrangement of the third diodes to share the ESD current applied to the first power line, so as to further prevent the active matrix device from being damaged by the ESD zap. Furthermore, the first diodes, the second diodes and the third diodes of the ESD protection circuit can be replaced by the first transistor devices, the second transistor devices and the third transistor devices, respectively, for protecting the devices and circuits of the active matrix device from being damaged by the ESD zap.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Patent Application
20070268637
