Patent Application
20110084992
The present invention relates to a display apparatus including active elements for driving light-emitting elements such as EL (electroluminescent) elements or LEDs (light-emitting diodes) and particularly to a display apparatus including thin film transistors (TFTs) as active elements.
TFTs are widely used as active elements for driving an active matrix display such as an organic EL display or a liquid crystal display.
Referring to
When a selecting pulse is applied to the scan line Ws, the selecting transistor 101 as a switch is turned on so as to render it conductive between its source and drain. At this time, a data voltage is supplied from the data line Wd through the selecting transistor 101 between the source and the drain and is stored in the capacitor 104. Because the data voltage stored in the capacitor 104 is applied between the gate and source of the drive transistor 102, a drain current Id corresponding to the gate-to-source voltage Vgs of the drive transistor 102 flows and is supplied to the OEL 100 to emit light.
In the active matrix display, by supplying a data signal corresponding to input video data to each pixel PLi,j via the data line while the selecting pulse (scan pulse) being applied sequentially to the scan lines, an image is displayed.
For the active matrix display, for example, Reference 1 discloses imparting a peak luminance characteristic to suppress white luminance to a low level to video of which the entire screen is bright. Specifically, it is disclosed that using the fact that the potential difference between the input end potential and the terminal end potential of the power supply line in a display apparatus varies according to the screen luminance, the potential on the other end of the data-holding capacitor, one end of which is connected to the gate of the drive transistor, is controlled according to the potential difference (i.e., image luminance), thereby imparting the above-mentioned peak luminance characteristic.
As such, for the active matrix display, it is becoming a very important capability to reduce power consumption from the viewpoint of saving energy, suppressing heat generation, making the apparatus thinner, and so on. Hence, providing a display apparatus of low power consumption is strongly desired.
One example of the problems to be solved by the present invention is the above defect in the conventional art. An object of the present invention is to provide a display apparatus of low power consumption that imparts a peak luminance characteristic to suppress white luminance to a low level to video whose entire screen is bright.
According to the present invention, there is provided a display apparatus which has an active matrix type of display panel comprising a plurality of pixel units each having a light-emitting element and a drive transistor driving the light-emitting element, a scan drive unit for sequentially scanning scan lines of the display panel, and a data drive unit for supplying a data signal based on a video signal to a control electrode of each of the drive transistors in association with scanning by the scan drive unit, the display apparatus comprises a capacitor provided in each of the plurality of pixel units to hold the data signal, a first terminal of the capacitor being connected to the control electrode of the drive transistor; a capacitor voltage generating unit which generates a capacitor voltage to be applied to a second terminal of each of the capacitors; an average luminance calculating unit which calculates average luminance of a display screen based on the video signal; and a drive voltage adjuster which adjusts a drive voltage of the drive transistors according to the average luminance.
Embodiments of the present invention will be described below in detail with reference to the drawings. The same reference numerals are used to denote substantially equivalent parts throughout the figures cited below.
The display panel 11 is an active matrix type of display panel comprising “n” rows and “m” columns of pixels, where “m” and “n” are integers greater than or equal to two, and has a plurality of data lines X1 to Xm (Xi; i=1 to m) arranged parallel, a plurality of scan lines Y1 to Yn (Yj; j=1 to n) arranged parallel, and a plurality of pixel units PL1,1 to PLn,m. The pixel units PL1,1 to PLn,m are arranged at the intersections of the data lines X1 to Xm and the scan lines Y1 to Yn and all have the same configuration.
Further, as described in detail later, the pixel units (or pixel circuits) PL1,1 to PLm,n are connected to a light-emitting element drive voltage line (hereinafter simply referred to as a drive voltage line) Z and a capacitor voltage line W.
Note that in this embodiment, description will be made taking as an example the case where the display panel 11 is a monochrome display panel and where each of the pixel units constitutes one pixel.
The gate of the selecting transistor (Tr1) 21 is connected to the scan line Yj, and its source is connected to the data line Xi. The drain of the selecting transistor 21 is connected to the control electrode (i.e., gate) of the drive transistor (Tr2) 22. The source of the drive transistor (Tr2) 22 is connected to the drive voltage line Z so that a drive voltage VD (a variable voltage) is supplied thereto from the drive voltage source (PS) 16. The drain of the drive transistor (Tr2) 22 is connected to the anode of the EL element 25. The cathode of the EL element 25 is connected to a potential Vcom common to the plurality of pixel units (pixel circuits) PL1,1 to PLm,n, for example, ground potential (Vcom=0).
In the present embodiment, one end of the capacitor (Cs) 24 (a first terminal; electrode E1) is connected to the gate, that is the control electrode, of the drive transistor 22 (and to the drain of the selecting transistor 21), and the other end thereof (a second terminal; electrode E2) is connected to the capacitor voltage source (PC) 14 via the capacitor voltage line W. The connection is made such that a capacitor voltage Vcap (a fixed voltage) is applied to the capacitor (Cs) 24 associated with the scan line Yj from the capacitor voltage source (PC) 14 via the capacitor voltage line W.
The scan lines Y1 to Yn of the display panel 11 are connected to the scan driver 12, and the data lines X1 to Xm are connected to the data driver 13. The controller 15 generates a scan control signal SC and a data control signal DD to gradation-drive control the display panel 11 according to an input video signal. The scan control signal is supplied to the scan driver 12, and the data control signal is supplied to the data driver 13.
The scan driver 12 supplies scan pulses for display on the scan lines Y1 to Yn at predetermined timings according to the scan control signal sent from the controller 15 to perform line sequential scanning.
The data driver 13 supplies respective pixel data signals for the pixel units located on the scan line onto which the scan pulse is being supplied, to the pixel units (i.e., selected pixel units) via the data lines X1 to Xm according to the data control signal sent from the controller 15. For non-light-emitting pixel units, the pixel data signal of a level which does not make their EL element emit light is supplied. In other words, the data signals indicating emission luminance respectively for the pixels are applied via the data lines X1 to Xm in association with the line sequential scanning so as to control the image display of the display panel 11.
The controller 15 controls the entire display apparatus 10, that is, the scan driver 12, the data driver 13, the capacitor voltage source (PC) 14, the light-emitting element drive voltage source (PS) 16, and the APL calculating unit 17.
Next, the circuit operation of the pixel unit PLj,i will be described.
When the scan pulse SP is applied to the j-th scan line Yj to select the scan line Yj, the selecting transistor 21 becomes conductive (i.e., turned on), and a data signal DP (data voltage Vdata) corresponding to the luminance of the pixel unit PLj,i from the data driver 13 is supplied to the gate (i.e., the first terminal; electrode E1) of the capacitor voltage 22 via the selecting transistor 21. Then, the data voltage Vdata is stored in the data-holding capacitor (Cs) 24, and the voltage is held.
Meanwhile, the capacitor voltage Vcap (a fixed voltage) is applied to the second terminal (i.e., electrode E2) of the capacitor 24 via the capacitor voltage line W. Thus, even when the selecting transistor 21 is turned off due to the line sequential scanning, the gate potential of the drive transistor 22 is fixed at the Vdata.
As described above, the variable voltage VD is applied to the source of the drive transistor 22, and the drain thereof is connected to the anode of the organic EL element 25. The cathode of the EL element 25 is connected to the common electrode Vcom. Thus, the current Id flowing through the drive transistor 22 is proportional to VD-Vdata, and the EL element 25 emits light with luminance corresponding to the data signal voltage DP and the source voltage VD of the drive transistor 22.
Next, the operation of adjusting peak luminance (white luminance) according to the brightness of the entire screen of video data will be described.
The average luminance calculating unit (APL calculating unit) 17 calculates an average luminance of the screen, i.e., APL (Average Picture Level) that is the brightness of the entire screen from the input video data (display data). The method of calculating the average luminance (APL) may be to add together the data to take the average of them where the input video data is digital data, or to integrate it where the input video data is an analog signal. Then, the calculated APL is supplied to the drive voltage source (PS) 16.
That is, as described above, because a current (drive current Id) proportional to VD-Vdata flows through the drive transistor 22, the adjustment of the drive voltage VD can impart a peak luminance characteristic where white luminance is made low when video whose entire screen is bright is displayed and becomes higher for video whose background is darker.
Next, the fact that reduction in electric power consumed in the drive transistor 22 together with the peak luminance characteristic can be achieved by adjusting the drive voltage VD according to the brightness (APL) of the entire screen of video data to impart the peak luminance characteristic, will be described specifically with reference to the drawings.
An EL element such as the organic EL element 25 exhibits a diode characteristic as well known. That is, the higher the emission luminance is (or the larger the drive current is), the higher the forward voltage (Vf) is (see
In contrast, as described above, in the present embodiment the drive voltage (source voltage) VD of the drive transistor 22 is adjusted according to the APL. Specifically, when video whose entire screen is bright is displayed, i.e., when the APL is large, the drive voltage VD is decreased, and thus power consumed corresponding to the drain-source voltage Vds of the drive transistor 22 can be suppressed to a low level.
More specifically, three pixel units of red, green, blue (R, G, B) are arranged sequentially in a repeated pattern in a row direction. That is, the three pixel units of red, green, blue (R, G, B) form one pixel, and a plurality of the pixels are arranged in a row direction. More specifically, pixels (PRj,1, PGj,1, PBj,1), (PRj,2, PGj,2, PBj,2), . . . , (PRj,m, PGj,m, PBj,m) are sequentially arranged in the j-th row of the display panel 11.
The circuit configurations of the pixel units of red, green, blue (R, G, B) are the same as in the above first embodiment (see
In each row, the red pixel units PRj,k (k=1 to n) are connected to a common connection line ZR, and the green pixel units PGj,k (k=1 to n) are connected to a common connection line ZG, and the blue pixel units PBj,k (k=1 to n) are connected to a common connection line ZB. More specifically, the connection lines ZR, ZG, ZB are connected to the source of the drive transistor (Tr2) 22 in respective pixel units. Drive voltages VD(R), VD(G), VD(B) are supplied respectively onto these connection lines (light-emitting element drive voltage lines) ZR, ZG, ZB from the light-emitting element drive voltage source (PS) 16. Of course, the light-emitting element drive voltage source (PS) 16 may be formed of individual variable voltage sources PS16(R), PS16(G), PS16(B) for the respective colors.
In the present embodiment, the light-emitting element drive voltage source (PS) 16 adjusts each of the drive voltages VD(R), VD(G), VD(B) according to the brightness (APL) of the entire screen of video data. That is, also where the forward voltage is different for each emission color, power consumed by the drive transistor can be reduced. Further, where the forward voltage of the EL element is different for each emission color, by adjusting the drive voltage of the drive transistor for each emission color, the EL element can be driven with a minimum power supply voltage required, and hence the effect of reducing power consumption is larger.
An embodiment which uses a current program scheme will be described below.
The configuration of the display apparatus 10 is the same as that in the first embodiment (
The display panel 11 has a circuit configuration adapted for the current program scheme as shown in
As in the first embodiment, the source of the drive transistor (Tr2) 22 is connected to the data line Xi, and the second terminal (i.e., electrode E2) of the capacitor (Cs) 24 is connected to a capacitor voltage line W. That is, a capacitor voltage Vcap (a fixed voltage) is applied to the capacitor (Cs) 24 from a capacitor voltage source 14 via the capacitor voltage line W. Although during the period of a write mode of the current program operation, the drive voltage (source voltage) VD of the transistor (Tr2) 22 is made to be a constant (or fixed) voltage as described later, the fixed voltage VD may be the same in value as the capacitor voltage Vcap applied to one end of the data-holding capacitor, or may be different from it.
The switches SW1 to SW3 are made open and closed according to a scan pulse signal from the scan driver 12 and/or a control signal from the controller 15. More specifically, their ON/OFF is controlled depending on the write mode of writing data to the capacitor (Cs) 24 or the light-emission mode of making the light-emitting element (OEL) 25 emit light.
Then, the pixel circuit switches to the light-emission mode, where the switches SW1, SW2 are made open (OFF) with the switch SW3 being closed (ON), and during the light-emission mode period, the drive voltage (source voltage) is set at an adjusted voltage value VD. Namely, the drive voltage source (PS) 16 sets the drive voltage (source voltage) VD to correspond to the APL value calculated by the APL calculating unit 17 and outputs this voltage.
That is, as in the previously-described embodiment, the variable voltage VD is adjusted such that the VD is increased when the entire screen is dark, i.e., when the APL is small, and that the VD is decreased when the entire screen is bright and the APL is large.
Namely, because a current (drive current Id) proportional to VD-Vdata flows through the drive transistor 22 as described above, the adjustment of the drive voltage VD can impart the peak luminance characteristic where white luminance is made low when video whose entire screen is bright is displayed and becomes higher for video whose background is darker.
Thus, as described above, the adjustment drive of the drive voltage VD can be applied to the display apparatus of the current program scheme as well, and the same peak luminance characteristic as in the voltage write type of display apparatus described in the above embodiments can be imparted.
Although in the above embodiments description has been made taking as an example the case where the selecting transistor (Tr1) 21 and the drive transistor (Tr2) 22 are P-channel TFTs, the adjustment drive of the drive voltage VD can also be applied to cases where either or both of the two transistors are N-channel TFTs. For example, it can also be applied to cases where the drive transistor (Tr2) 22 is an N-channel TFT.
The gate of the selecting transistor (Tr1) 21 is connected to the scan line Yj, and its source is connected to the data line Xi. The drain of the selecting transistor 21 is connected to the control electrode (gate) of the drive transistor (Tr2) 22. The drive transistor (Tr2) 22 is an N-channel TFT, and the source of the drive transistor (Tr2) 22 is connected to a drive voltage line Z so that a drive voltage VD is supplied thereto from the drive voltage source (PS) 16. The drain of the drive transistor (Tr2) 22 is connected to the cathode of the EL element 25. The anode of the EL element 25 is connected to a potential Vcom common to the plurality of pixel units (pixel circuits) PL1,1 to PLm,n.
In the present embodiment, one end of the capacitor (Cs) 24 (a first terminal; electrode E1) is connected to the gate, that is the control electrode, of the drive transistor 22 (and to the drain of the selecting transistor 21), and the other end thereof (a second terminal; electrode E2) is connected to the capacitor voltage source (PC) 14 via the capacitor voltage line W. The connection is made such that a capacitor voltage Vcap (a fixed voltage) is applied to the capacitor (Cs) 24 associated with the scan line Yj from the capacitor voltage source (PC) 14 via the capacitor voltage line W.
In the present embodiment, as shown in
In the present embodiment, as shown in
It is more effective to vary video data according to the APL with adjusting the drive voltage VD according to the brightness (APL) of the entire screen of the video data as described in the first embodiment.
The APL value calculated by the APL calculating unit is supplied to the black-level adjusting circuit 31. The black-level adjusting circuit 31 adjusts the black level BL of the input video signal according to the calculated APL value to generate an adjusted data control signal DDA, which is supplied to the data driver 13.
The black-level adjusting circuit 31 may adjust, for example, the gain of an amplifier (not shown) amplifying the input video data when the input video data is an analog signal to generate the adjusted data control signal DDA, and may adjust the gain of a multiplier (not shown) multiplying the input video data by a multiplier factor when the input video data is digital data to generate the adjusted data control signal DDA.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/059550 | 5/23/2008 | WO | 00 | 11/22/2010 |
