Patent Application
20070285358
The above and other objects and features of the present invention will become apparent from the following description of embodiments, given in conjunction with the accompanying drawings, in which:
Hereinafter, a display apparatus using an active matrix vacuum fluorescent display (AMVFD) in accordance with an embodiment of the present invention will be described with reference to
The AMVFD includes a glass vessel 39 that is a sealed vessel having a glass substrate 10 as a bottom part, an active matrix IC 30 that is an IC chip formed on the glass substrate 10 in the glass vessel 30 and a filament 38. The AMVFD is connected to a CPU 40, a power supply Vct and a filament power supply 35 via leads (not shown).
The active matrix IC 30 includes a display section 32 having a display element and a display circuit for driving the display element and a non-display section 33. A control unit 31 is formed in the non-display section 33.
As illustrated in
The CPU 40 is connected to input terminals of the control unit 31, such as a latch input terminal LAT, a shift register clock terminal CLK, a serial data input terminal SI, a serial output terminal SO and a test terminal TEST. Further, the CPU 40 is connected to a write enable terminal WE and a blank terminal BKD for adjusting brightness of the display section 32.
A data signal from the CPU 40 is outputted serially to the control unit 31. The control unit 31 applies serial/parallel conversion to the data signal through a CLK signal and a LAT signal, to thereby output the data signal to the display section 32 through a WE signal and a BKD signal (and also the LAT signal, if desired).
An active matrix drive circuit of
An input signal includes a row address select signal, a logic control signal and a display data signal. In response to the row address select signal, one row of the address signal line 15 is selected by a decoder. The display data signal inputs data to each column.
In response to the row address select signal and display data signal, data for each pixel arranged in a matrix pattern are held in the holding unit 13 of the selected row, which is data for one row, and sequential increment of the row address select signal is repeated until data for all the rows are written.
Data outputted by a logical product of the held data and a blank signal are inputted to the drive output circuit 20 at the final stage of the display pixel unit 21 via the drive circuits 18 and 19 to be display data.
The drive circuits 18 and 19 are respectively formed of a depletion mode P channel MOSFET 18 and an enhancement mode P channel MOSFET 19. The drive output circuit 20 at the final stage is formed of a P channel MOSFET 20. Further, the P channel MOSFET 20 is a high withstand voltage P channel MOSFET. Further, the depletion mode MOSFET 18 may be replaced with an enhancement mode N channel MOSFET.
The drive output circuit 20 at the final stage is formed of the P channel MOSFET and, in driving the anode electrode, a signal level voltage superposed to a filament center tap voltage is applied to the anode electrode, so that the signal level voltage from the drive output circuit becomes low. Therefore, no transistor for high withstand voltage is required, except for the transistor at the final stage.
Since the configuration includes the P channel MOSFET structures only, a low voltage power supply and a GND are sufficient for each display pixel.
From the above, since it is sufficient that only one high withstand voltage transistor, whose design rule is strict, is disposed in each pixel, consumption current can be suppressed to be small. The size of the pixel can also be reduced, since it is sufficient to provide only two power supply lines, a low voltage line and a GND line. Accordingly, the holding circuit, drive circuit and drive output circuit can be arranged under an anode electrode forming a pixel of the drive output unit. Further, the pitch between pixels can be narrowed, which makes it possible to obtain a high resolution display.
As described above, the control unit 31 of the VFD of the present invention includes a shift register circuit for performing the serial/parallel conversion by taking a conventional serial driver input manner for CIG (chip in glass).
Serial data are inputted in synchronization with a CLK signal from the CPU 40. LAT is a signal for transferring data to the display section.
A WE signal and a BKD signal are inputted directly to the display section 32. The WE signal is a data write control signal and the BKD signal is a signal for adjusting brightness of the display section.
In this embodiment, as illustrated in
Difference “d” in width between the AMVFDs shown in
Further, in accordance with the present invention, the TEST terminal and the SO terminal are provided as input and output terminals of the active matrix IC 30, respectively, so that the AMVFD can be tested.
When the TEST terminal becomes ‘H’ in response to a signal from the CPU 40, a test mode is set. In response to a row address select signal inputted from the SI terminal, latch data written to the selected row of the display section are outputted from the SO terminal, so that the active matrix IC 30 can be tested.
In accordance with the present invention, compared with a conventional case where a control IC and a separate display IC are mounted on a substrate and the control signals of the control IC are transmitted to column/row signal lines of the display IC in parallel by wire bonding, the display section and the control unit are provided on a single IC, so that the IC test can be carried out and the wire bonding of parallel connections can be omitted. Accordingly, as for the IC of the display section 32 of the active matrix IC 30, yield of products is considerably increased, thereby achieving an enhanced reliability, an area reduction and a low cost.
The test of the active matrix IC by using the SO terminal can make the tests of AMVFD products easy, to thereby improve accuracy thereof.
The SO terminal makes cascade connections of data possible in a normal mode, and makes it possible to read latched data written to each pixel in a test mode. Therefore, the SO terminal can be used for data cascade.
The AMVFD of the present invention, configured as described above, includes the active matrix substrate including the display section 32 and the control unit 31 together. Then, a data signal from the CPU 40 to the active matrix IC 30 is outputted serially through the SI terminal, thereby making it possible to reduce the number of input and output terminals considerably.
In accordance with the present invention, by integrating the control unit 31 and the display section 32 in the active matrix IC 30, a BK terminal which is adapted to control an output of the control unit 131 by the CPU 140 in the conventional example is not required and can be omitted.
While the invention has been shown and described with respect to the embodiments, it will be understood by those skilled in the art that various changes and modifications may be without departing from the scope of the invention as defined in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-160943 | Jun 2006 | JP | national |
