Patent Application
20080080232
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:
In one embodiment of the invention, a method of programming a magneto resistive memory cell is provided, comprising applying a first write current to the magneto resistive memory cell and determining whether the magneto resistive memory cell meets a programming criterion. In case that the magneto resistive memory cell does not meet the programming criterion, applying a second write current to the magneto resistive memory cell that is higher or lower than the first write current. Determining whether the magneto resistive memory cell meets a programming criterion and the increase or decrease of the write current in case that the magneto resistive memory cell does not meet the programming criterion is repeated until the magneto resistive memory cell meets the programming criterion.
The programming may be performed using a Stoner Wohlfarth switching mechanism.
In another embodiment of the invention, the programming may be performed using rotational type switching mechanism.
In another embodiment of the invention, a method of programming magneto resistive memory cells is provided, comprising applying a first write current to a first magneto resistive memory cell to write a first programming value into the first magneto resistive memory cell, applying a second write current to a second magneto resistive memory cell to write a second programming value into the second magneto resistive memory cell, the second programming value being different from the first programming value, and determining whether the magneto resistive memory cells meet a programming criterion. In case that the first magneto resistive memory cell or the second magneto resistive memory cell does not meet the programming criterion, applying a third write current to the respective magneto resistive memory cell that is higher or lower than the first magnetic field or the second magnetic field, respectively, the third write current being applied via a first cell control line corresponding to the write direction of the failing magneto resistive memory cell. In case that the first magneto resistive memory cell and the second magneto resistive memory cell do not meet the programming criterion, applying a fourth write current to the respective magneto resistive memory cell that is higher or lower than the first magnetic field or the second magnetic field, respectively, the fourth write current being applied via a second cell control line.
The first cell control line may be the bit line of the respective magneto resistive memory cell. The second cell control line may be the word line of the respective magneto resistive memory cell.
In one embodiment of this aspect of the invention, the programming is performed using Stoner Wohlfarth switching mechanism.
In accordance with yet another embodiment of the invention, a method of programming magneto resistive memory cells is provided, comprising applying a first write current to a first magneto resistive memory cell to write a first programming value into the first magneto resistive memory cell, applying a second write current to a second magneto resistive memory cell to write a second programming value into the second magneto resistive memory cell, the second programming value being different from the first programming value, and determining whether the magneto resistive memory cells meet a programming criterion. In case that the first magneto resistive memory cell or the second magneto resistive memory cell or both magneto resistive memory cells do not meet the programming criterion, applying a third write current to the respective magneto resistive memory cell that is higher or lower than the first magnetic field or the second magnetic field, respectively, the third write current being applied via a first cell control line, and applying a fourth write current to the respective magneto resistive memory cell that is higher or lower than the first magnetic field or the second magnetic field, respectively, the fourth write current being applied via a second cell control line.
The first cell control line may be the bit line of the respective magneto resistive memory cell. The second cell control line may be the word line of the respective magneto resistive memory cell.
In one embodiment of this aspect of the invention, the programming may be performed using rotational type switching mechanism.
In accordance with still another embodiment of the invention, a magneto resistive memory cell arrangement is provided, comprising at least one magneto resistive memory cell, a programming control unit, and a first magnetic field applied to the magneto resistive memory cell. It is determined whether the magneto resistive memory cell meets a programming criterion. In case that the magneto resistive memory cell does not meet the programming criterion, a second magnetic field is applied to the magneto resistive memory cell that is higher or lower than the first magnetic field. Determining whether the magneto resistive memory cell meets a programming criterion and the increase or decrease of the magnetic field in case that the magneto resistive memory cell does not meet the programming criterion is repeated until the magneto resistive memory cell meets the programming criterion.
In accordance with an embodiment of the invention, a magneto resistive memory cell arrangement is provided, comprising an array of a plurality of magneto resistive memory cells, each magneto resistive memory cell being connected to a respective first cell control line and a respective second control line. A programming control unit is connected to the first cell control lines and the second control lines. A first write current is applied to a first magneto resistive memory cell to write a first programming value into the first magneto resistive memory cell. A second write current is applied to a second magneto resistive memory cell to write a second programming value into the second magneto resistive memory cell, the second programming value being different from the first programming value. It is determined whether the magneto resistive memory cells meet a programming criterion. In case that the first magneto resistive memory cell or the second magneto resistive memory cell does not meet the programming criterion, applying a third write current to the respective magneto resistive memory cell that is higher or lower than the first magnetic field or the second magnetic field, respectively, the third write current is applied via a first cell control line corresponding to the write direction of the failing magneto resistive memory cell. In case that the first magneto resistive memory cell and the second magneto resistive memory cell do not meet the programming criterion, applying a fourth write current to the respective magneto resistive memory cell that is higher or lower than the first magnetic field or the second magnetic field, respectively, the fourth write current is applied via a second cell control line.
The first cell control line may be the bit line of the respective magneto resistive memory cell and the second cell control line may be the word line of the respective magneto resistive memory cell.
Furthermore, computer program products of programming a magneto resistive memory cell or of programming magneto resistive memory cells are provided, which, when being executed by a computer, comprise the respective features of the methods as described above and as will described in more detail below.
The fixed layer 112 is e.g. magnetized in a fixed direction, while the direction of magnetization of the free layer 108 may be switched, changing the resistance of the magnetic memory stack 106. One bit of digital information may be stored in a magnetic memory stack 106 by running a current through the bit line 102 and the word line 104 that intersect at the magnetic memory stack 106, creating a sufficient magnetic field to set the direction of magnetization of the free layer 108. Information may be read from a magnetic memory stack 106 by applying a voltage across the magnetic memory stack, and measuring the resistance. If the direction of magnetization of the free layer 108 is parallel to the direction of magnetization of the fixed layer 112, then the measured resistance will be low, representing a value of “0” for the bit. If the direction of magnetization of the free layer 108 is anti-parallel to the direction of magnetization of the fixed layer 112, then the resistance will be high, representing a value of “1.”
Depending on the type of switching that is being used, the method used for writing may be varied. If Stoner-Wohlfahrt switching is being used, then the direction of the current on the bit line 102 will determine the value that is written. If rotational mode switching (also referred to as toggle mode switching) is being used, then the value already stored in a magnetic memory stack 106 needs first to be read. If the value is already the same as the value to be written, then no action is taken. Otherwise, if the value needs to be changed, then current is applied, in a fixed direction, on the word line 104 and bit line 102 to toggle the value stored in the magnetic memory stack 106.
It will be understood that the view shown in
As shown in
Then, a first write current that is normally provided for writing a logic “0” into the first MRAM cell is applied to the first MRAM cell in 304. The application of the first write current includes the application of a word line current and a first bit line current to the first MRAM cell, in other words, to the first word line and the first bit line, which are connected to the first MRAM cell.
Then, a second write current that is normally provided for writing a logic “1” into the second MRAM cell is applied to the second MRAM cell in 306. The application of the second write current includes the application of the word line current and a second bit line current to the second MRAM cell, in other words, to the second word line and the second bit line, which are connected to the second MRAM cell.
In an alternative embodiment of the invention, 304 and 306 are executed simultaneously. In other words, a plurality of bit lines are activated simultaneously. In this way, a plurality of memory cells may be programmed at the same time. In one embodiment of the invention, the first bit line current is used to program a logic “0” (the first bit line runs in a first direction) into a first memory cell and the second bit line current is used to program a logic “1” (the second bit line runs in a second direction, wherein the second direction is opposite to the first direction) into a second memory cell. In other words, in one embodiment of the invention, 304 and 306 are performed simultaneously using the same word line current.
Next, according to this embodiment of the invention, it is determined, using the read circuit 206 and the comparator 208, whether the programming (i.e., the write operation) of a logic “0” of the first MRAM cell has failed or has been successful (operation 308). This operation is carried out in that the actual resistance value of the first MRAM cell representing the logic value being stored in the first MRAM cell is compared with the resistance value that would represent the logic value that should be stored in the first MRAM cell during the write operation.
In case the programming of the logic “0” of the first MRAM cell has failed (“Yes” in 308), it is determined, again using the comparator 208, whether the programming (i.e. the write operation) of a logic “1” of the second MRAM cell has been failed or has been successful (operation 310). This operation is carried out in that the actual resistance value of the second MRAM cell representing the logic value being stored in the second MRAM cell is compared with the resistance value that would represent the logic value that should be stored in the second MRAM cell during the write operation.
In case the programming of the logic “1” of the second MRAM cell has also been failed (“Yes” in 310), the first word line current is increased by a predetermined amount (operation 312).
In a subsequent operation (operation 316), an increased first write current is applied to the first MRAM cell to program a logic “0.” The application of the increased first write current includes the application of the increased word line current and the first bit line current to the first MRAM cell, in other words, to the first word line and the first bit line, which are connected to the first MRAM cell. In other words, a further write attempt to program a logic “0” is carried out using an increased word line current in order to program the first MRAM cell.
Then, in 318, an increased second write current is applied to the second MRAM cell to program a logic “1”. The application of the increased second write current includes the application of the increased word line current and the initial second bit line current to the second MRAM cell, in other words, to the second word line and the second bit line, which are connected to the second MRAM cell. In other words, a further write attempt to program a logic “1” is carried out using an increased word line current in order to program the second MRAM cell.
The method then returns to 308.
Now referring back to 310, in case the programming of a logic “1” of the second MRAM cell has not failed (“No” in step 310), in other words, in case that only the programming of a logic “0” of the first MRAM cell has failed, the first bit line current is increased by a predetermined amount (operation 320) (see
In a subsequent operation (operation 322), an increased first write current is applied to the first MRAM cell to program a logic “0.” The application of the increased first write current in this case includes the application of the word line current and the increased first bit line current to the first MRAM cell to program a logic “0.” In other words, a further write attempt to program a logic “0” is carried out using an increased bit line current in order to program the first MRAM cell.
The method then returns to 308.
Now referring back to 308, in case the programming of a logic “0” of the first MRAM cell has not failed (“No” in 308), in other words, in case that the programming of a logic “0” of the first MRAM cell has been successful, it is determined, again using the read circuit 206 and the comparator 208, whether the programming (i.e., the write operation) of a logic “1” of the second MRAM cell has failed or has been successful (operation 324). This operation is carried out in that the actual resistance value of the second MRAM cell representing the logic value being stored in the second MRAM cell is compared with the resistance value that would represent the logic value that should be stored in the second MRAM cell during the write operation.
In case the programming of a logic “1” of the second MRAM cell has failed (“Yes” in 324), in other words, in case that only the programming of a logic “1” of the second MRAM cell has failed, the second bit line current is increased by a predetermined amount (operation 326) (see
In a subsequent operation (operation 328), an increased second write current is applied to the second MRAM cell. The application of the increased second write current in this case includes the application of the word line current and the increased second bit line current to the second MRAM cell to program a logic “1”. In other words, a further write attempt to program a logic “1” is carried out using an increased bit line current in order to program the second MRAM cell with a logic “1.”
The method then returns to 308.
In case the programming of a logic “1” of the second MRAM cell has not failed (“No” in 324), in other words, in case that the programming of a logic “1” of the second MRAM cell has also been successful, the programming method is completed in an end operation 330.
In other words, in a Stoner-Wohlfahrt type of switching of an MRAM cell, if the writing of a logic “0” and the writing of a logic “1” both fail during a write operation, the word line current of the word line the respective MRAM cells are connected to, will be increased. If only the writing of a logic “0” or the writing of a logic “1” fails during a write operation, the bit line current of the bit line the respective MRAM cell is connected to, will be increased corresponding to the write direction of the failing logic “0” or logic “1,” respectively.
As shown in
Then, a write current that is normally provided for writing a logic “0” or a logic “1,” respectively, into the selected MRAM cell is applied to the MRAM cell (step 404). The application of the write current includes the application of a word line current and a bit line current to the MRAM cell, in other words, to the word line and the bit line, which are connected to the MRAM cell.
Next, according to this embodiment of the invention, it is determined, using the read circuit 206 and the comparator 208, whether the programming (i.e. the write operation) of the MRAM cell has failed or has been successful (step 406). This step is carried out in that the actual resistance value of the MRAM cell representing the logic value being stored in the MRAM cell is compared with the resistance value that would represent the logic value that should be stored in the MRAM cell during the write operation.
In case the programming of the first MRAM cell has failed (“Yes” in step 406), the word line current is increased by a predetermined amount (step 408). Furthermore, the bit line current is also increased by a predetermined amount, which may be the same amount or a different amount than the amount by which the word line current is increased (step 410).
In a subsequent step (step 412), an increased write current is applied to the respective MRAM cell. The application of the increased write current includes the application of the increased word line current and the increased bit line current to the MRAM cell, in other words, to the word line and the bit line, which are connected to the MRAM cell. In other words, a further write attempt is carried out using an increased word line current and an increased bit line current in order to program the MRAM cell.
In case the programming of the first MRAM cell has not failed (“No” in step 406), in other words, in case that the programming of the MRAM cell has been successful, the programming method is completed in an end step 414.
In other words, in a rotational type of switching of an MRAM cell, if the writing of a logic “0” or of a logic “1” fails during a write operation, both the word line current of the word line and the bit line current of the bit line the respective MRAM cell is connected to, will be increased.
The methods described above are iterative methods that step-by-step increase the respective currents (and thereby the respectively applied magnetic fields) until the programming of the respective MRAM cell(s) has been successful. In other words, in case of an error, the write circuitry will adjust the programming write current and data will be written, read and compared again, until data are correctly programmed into the respective MRAM cell. In an embodiment of the invention, incoming data to be written into the storage area (i.e., the MRAM cell array 202) are, after the completion of the first write operation, immediately read again and compared in the comparator 208 with the value to be written. For the presented adjustment technique, it is provided that the storage area is written with a logic “0” bit and a logic “1” bit during a write cycle.
In addition to compensating an externally applied disturb field, the presented methods will also improve array yield by automatically correcting imperfect cells suffering by an offset shift occurring during fabrication.
Referring now back to
For a given magnetic programming field generated by the currents flowing through the word line and bit line, the memory cells may be programmed erroneously with a too small external magnetic field as well as with an external magnetic field being too high. Based on the output of the magnetic field sensor 214 or the magnetic field sensors, the current flowing through the word line and the bit lines, respectively may be increased as well as decreased (in other words, the word line current and the bit line currents may be increased as well as decreased). The decrease may be provided, e.g., in case that during the operation of the MRAM device 200, an increase of the external magnetic field strength is detected compared to an initial external magnetic field strength that may be measured in an initialization phase of the MRAM device 200 or after a predetermined re-calibration time period. The process in reducing the currents (word line current and bit line currents) is analogous compared with the embodiments, in which an increasing of the currents (word line current and bit line currents) is provided, only with opposite sign.
In one embodiment of the invention, a method for active write adjustment in an MRAM is provided, e.g., a method for active write adjustment in a Stoner-Wohlfahrt switching type MRAM or a method for active write adjustment in a rotational switching type MRAM.
While the invention has been shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced.
