Claims
- 1. A method for designing a coherent shared-memory system comprising:
accepting an input specification for the shared-memory system that includes a specification of a plurality of state transition rules for the shared-memory system, including accepting a precondition and an action associated with each of the state transition rules, wherein the plurality of state transition rules includes a first subset of rules and a second subset of rules such that correct operation of the memory system is provided by application of all of the rules in the first subset of rules and any selective application of rules in the second subset of rules; accepting a specification of a policy, including accepting preconditions for application of rules in the second subset of state transition rules; and combining the specification of the policy and the input specification of the state transitions rules to form an output specification of a plurality of state transition rules, including combining preconditions associated with rules in the second subset of rules and the policy to determine preconditions for application of actions associated with the second subset of rules.
- 2. The method of claim 1 further comprising:
verifying that correct operation of the memory system is provided by application of all of the rules in the first subset of rules and any selective application of rules in the second subset of rules.
- 3. The method of claim 2 wherein verifying that correct operation is provided includes proving a logical property related to the correct operation of the memory system.
- 4. The method of claim 3 wherein proving a logical property includes proving that state sequences for the memory system correspond to state sequences of a reference state machine.
- 5. The method of claim 1 further comprising:
implementing the shared-memory system according to the output specification of the state transition rules.
- 6. The method of claim 5 wherein implementing the shared-memory system includes determining a specification of circuitry whose operation is consistent with the output specification of the state transition rules.
- 7. In a coherent shared-memory system that includes a plurality of caches and a shared memory coupled to each of the caches, wherein the shared memory includes a directory for associating each of a plurality of addresses in a shared address range with caches that each has a value associated with said address in a storage at that cache, a method comprising:
at each of the plurality of caches, storing a value associated with a first address in the shared address range in the storage of said cache; while storing the values associating with the first address at each of the caches, associating in the directory the first address with some but not all of the caches which are storing said values; and while associating the first address with some but not all of the caches which are storing values associated with said first address, providing a coherent memory model for said first address to processors coupled to each of the plurality of caches.
- 8. A coherent shared-memory system comprising:
a plurality of caches, each including an interface to the shared-memory system for a different one of a plurality of processors and a storage for values associated with addresses in a shared address range shared by the processors; and a shared memory coupled to each of the plurality of caches, including a directory for associating each of a plurality of addresses in the shared address range with caches that each has a value associated with said address in its storage; wherein the directory is configured to in operation associate a first address in the shared address range with some but not all of the caches that have values in their storages associated with said first address while the shared-memory system provides a coherent memory model for said first address to each of the plurality of processor.
- 9. In a coherent shared-memory system that includes a plurality of caches each coupled to a different one of a plurality of processors and a shared memory coupled to each of the caches, a method comprising:
providing at a first cache a first storage associated with a first address in an address range shared by the processors; associating the first storage with one of a plurality of operating modes; storing a value in the first storage; receiving from a first processor coupled to the first cache a first memory instruction related to the first address; and processing the first memory instruction according to the operating mode associated with the first address, including if the first storage is associated with a first of the operating modes, causing a value associated with the first address to be transferred between the shared memory and the first cache, and if the first storage is associated with a second of the operating modes processing the memory instruction without causing a value associated with the first address to be transferred between the shared memory and the first cache.
- 10. The method of claim 9 further comprising:
providing at a second cache a second storage associated with the first address; and associating the second storage with a different one of the operating modes than the operating mode with which the first storage is associated.
- 11. The method of claim 9 wherein
receiving the first memory instruction includes receiving an instruction to make a value associated with the first address at the first cache accessible to processors other than the first processor, and causing a value associated with the first address to be transferred between the shared memory and the first cache includes transferring the value from the first cache to the shared memory.
- 12. The method of claim 11 wherein the first memory instruction include a commit instruction.
- 13. The method of claim 9 wherein
receiving the first memory instruction includes receiving an instruction that cause a value stored by another of the processors at the first address to be retrieved by the first processor, and causing a value associated with the first address to be transferred between the shared memory and the first cache includes causing the value to be transferred to the first cache from the shared memory.
- 14. The method of claim 13 wherein the first memory instruction includes a reconcile instruction.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part of U.S. application Ser. No. 09/300,641 filed on Apr. 27, 1999, which claimed the benefit of U.S. Provisional Application No. 60/112,619 filed on Dec. 17, 1998 and the benefit of U.S. Provisional Application No. 60/124,127 filed on Mar. 12, 1999. This application also claims the benefit of U.S. Provisional Application No. 60/131,229 filed on Apr. 27, 1999, which is incorporated herein by reference in its entirety.
STATEMENT AS TO FEDERALLY SPONSORED RESEARCH
[0002] This invention was made with government support under Office of Naval Research contract N00014-92-J-130 and Ft. Huachuca contract DABT63-95-C-150 awarded by the Advanced Research Projects Agency of the Department of Defense. The government has certain rights in the invention.
Provisional Applications (3)
|
Number |
Date |
Country |
|
60112619 |
Dec 1998 |
US |
|
60124127 |
Mar 1999 |
US |
|
60131229 |
Apr 1999 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
09561168 |
Apr 2000 |
US |
Child |
10325028 |
Dec 2002 |
US |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09300641 |
Apr 1999 |
US |
Child |
09561168 |
Apr 2000 |
US |