ADDRESS COUNTER FOR NONVOLATILE MEMORY DEVICE

Abstract

An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a data path flow scheme of a nonvolatile NAND type memory according to the prior art.

FIG. 2 illustrates a read sequence according to the prior art.

FIG. 3 illustrates a program sequence according to the prior art.

FIG. 4 shows a cell of a common internal counter architecture, and related clock conditions according to the prior art.

FIG. 5 illustrates an example of a pipeline implemented for a read operation according to the prior art.

FIG. 6 illustrates the behavior of an internal address counter for accessing a spare area in a memory device having a small page organization (256MX8) according to the prior art.

FIG. 7 illustrates the program sequence for accessing a spare area in a memory device having a large page organization (1GX8) according to the prior art.

FIG. 8A is a basic circuit diagram of the address counter according to the present invention.

FIG. 8B shows a pipeline implementation in a cell of the address counter of FIG. 8A.

FIG. 9 illustrates the behavior of the address counter for a read operation according to the present invention.

FIG. 10 illustrates the behavior of the address counter for a program operation according to the present invention.

FIG. 11 illustrates the behavior of the address counter when accessing a spare area in a memory device having a large page organization (1GX8) during a program operation according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In describing the features of the illustrated architecture of an internal (column) address counter compared to those in the known architecture of FIG. 5, the following TABLE 1 on the meanings of the numerous signal labels and circuit labels used in the drawings and in this description may be of assistance to the reader

TABLE 1
CLE                 Command Latch Enable.
ALE                 Address Latch Enable.
R/B!                Ready/Busy.
WEN                 Negate of Write Enable
REN                 Negate of Read Enable
I/O0~7              Data Inputs/Outputs
Erase_verify_ck     Clock that is generated when
                    executing the erase verify
                    algorithm
WEN AFTER ALE cycle WEN signal after ALE cycle. That
                    is, WEN cycle for pure data load.
CARRY[n]            the logic result of CARRY[n − 1] and
                    ADD(Q)[n − 1]
LOADADD             Address data input from PAD during
                    ALE cycle. It is the start address
                    requested by the user.
ENCOUNT             ‘H’ when the Address Counting
                    F/F(of the Main Counter) should be
                    incremented at rising edge of
                    every CK_ADD.
LOAD_UPDATE         ‘H’ when initially the value of
                    the Address Loading F/F is loaded
                    in the Address Counting F/F(of
                    the Main Counter cell or module)
                    to set the start address according
                    to the user's input.
ENLOAD              ‘H’ during ALE cycles
AX_INC_2            In order to make a pipeline for a
                    read operation, a value LOADADD + 2
                    must initially be loaded in the
                    Internal Address F/F of the
                    Internal Address BUS ADD_A0 of the
                    novel Address Counter
                    architecture.
READCTRL_CLE        ‘H’ when READ confirm (30 h) is
                    input.
AX_LOAD11           For the Address Counting
                    F/F[10:6], AX_LOAD11 is the
                    Address[11] value among the start
                    address bit values input by the
                    user. For the Address Counting
                    F/F[5:0], AX_LOAD11 is fixed to
                    ‘L’.
AX_INC_1            In order to make a pipeline for a
                    read operation, a value LOADADD + 1
                    must be loaded in the Internal
                    Address F/F off the Internal
                    Address BUS ADD_A1 of the novel
                    Address Counter architecture.
AX_LOAD0            Address[0] value among the start
                    address bit values input by the
                    user.
CK_LOAD             Corresponds to the WEN signal when
                    ALE is high
Address Loading F/F Is the added F/F of each cell or
                    module of the novel Address
                    Counter for storing Address data
                    input through the PAD when ALE is
                    high and WEN is low.
Address Counting    Is the main F/F of the basic
F/F                 Address Counter architecture. The
                    value stored in the Address
                    Loading F/F is loaded in the main
                    Address Counting F/F to set the
                    start address value according to
                    the user's input with LOAD_UPDATE
                    ‘H’.
                    Once the Address Counting F/F has
                    loaded the value stored in the
                    Address Loading F/F, the address
                    may start to be incremented by
                    CK_ADD.
ADD                 output value of any of the Address
                    Counting F/F that compose the
                    Address Counter
ADD[0]              The counted address value of the
                    Address Counting F/F[0]
Counted Address     The values stored in the Address
value               Counting F/F that compose the
                    Address Counter. The number of
                    Address Counting F/F depend on the
                    capacity of device (for 1Gbit
                    (Large) page, the number is 27,
                    for a 512M (Large) Page, the
                    number is 26)
Adder               In prior art architectures, it
                    adds ADDs values to make a
                    pipeline. In FIG. 5, Internal
                    Address BUS0 is Counted Address
                    value[n:1] + Counted Address
                    value[0], whilst Internal Address
                    BUS1 is Counted Address
                    value[n:1].
ADD_A               output of Adder. The number of
                    ADD_A values depends on the
                    capacity of device(1Gbit Large
                    page 26, 512M Large Page 25).
                    ADD_A corresponds to Internal
                    Address BUS0 of FIG. 5.
Internal Address    output of Adder. That is ADD_A
BUS0[n:1]           values. The width of Internal
                    Address BUS0 depends on the
                    capacity of device(1Gbit Large
                    page 26, 512M Large Page 25).
Internal Address    The Counted Address values[n:1],
BUS1[n:1]           That is the ADD values The width
                    of Internal Address BUS1 depends
                    on the capacity of device(1Gbit
                    Large page 26, 512M Large Page
                    25).
ADD_A0              Corresponds with the Internal
                    Address BUS0[n:1] of FIG. 5. That
                    is one internal address to make a
                    read pipeline.
ADD_A1              Corresponds with the Internal
                    Address BUS1[n:1] of FIG. 5. That
                    is the other internal address to
                    make a pipeline.

With reference to the diagram of FIG. 8A, address loading of externally input address values and their storing in the main address counting flip flop of the address counter is handled in two distinct flip-flops F/F1 and F/F2, respectively, for each cell of the address counter.

The counter is realized by coupling together a plurality of cells of FIG. 8B such that the bit CARRY generated by a cell is fed to the cell that follows in the cascade.

The address loading flip-flop F/F1 stores the externally input address bit during ALE cycles.

The functioning of the illustrated address counter for carrying out a read operation is as follows.

The signal CK_LOAD is equal to WEN signal only during ALE cycles. The address bit value is updated in the address loading F/F1 by CK_LOAD, and corresponds to a bit of the address input by the external user.

The bit value or counted address value ADD in the main or address counting flip-flop F/F2 of a cell of the address counter is eventually updated to correspond to the bit in the address loading flip flop F/F1 at the rising of CK_ADD during the read confirm cycle (30h).

At this time, in order to support a pipeline operation as the one depicted in FIG. 5, the full counted address given by the multibit bus of all the ADD bit values of the cells of the address counter is incremented by two compared to the full address loaded in the address loading flip flops F/F1 of all the cells of the address counter. This “increment by two” of the loaded address (AX_INC_—2=Q_LOAD_int[11:0]+2) takes place before LOAD_UPDATE. In other words, this is before the loaded externally input address becomes stored into the main counted flip flops F/F2 of the address counter.

Therefore, in a read operation, the signal READCTRL_CLE becomes high and the counted address value (ADD) can be updated to the incremented by two addresses at the rising edge of CK_ADD when LOAD_UPDATE=high (i.e., during the read confirm cycle (30h)).

The pipelining can be implemented with the illustrated address counter of FIG. 8A as illustrated in FIG. 8B, which depicts a cell of the cascade of cells of the counter.

FIG. 8B illustrates a cell of the cascade of cells that forms the address counter. This also includes the circuitry for implementing a pipeline identified in the circled area.

When the internal address counter is incremented at every toggling of the RE signal, the internal address buses BUS0 and BUS1 are updated to the bit values A[27:1] assumed by the cells of the internal address counter. This is according to the value A[c0] of the address counting flip flop F/F of the first cell of the of the internal address counter.

This behavior is a key feature of the pipelining of the illustrated address counter because the page buffer, contrary to what happens in the prior art architectures of the address counter, is no longer directly connected to an address counter that implements the addition. On the contrary, in the new architecture, the page buffer will receive new address values latched in the address loading flip flops at the rising edge of the CK_ADD signal. That is, after the adding by two of the input address has been already completed (AX_INC_—2=Q_LOAD_int[11:0]+2). Therefore, the risk of occurrence of glitches is significantly reduced compared to the known architectures.

Focusing on the circuitry for implementing a pipeline in the labeled circle, internal address buses BUS0 and BUS1 are updated to “load address+1” and “load address”, respectively, at the same moment when the main address counter value ADD is finally updated to the “incremented-by-two” value of the externally input address previously latched in the address loading flip flops of the cells of the counter. That is, this value is Ax_INC_—2=Q_LOAD_int[11:0]+2. The value of the internal signal AX_INC_—1 of the pipelining circuitry is AX_INC_—1=Q_LOAD_int[11:0]+1.

Thereafter, when the internal address counter is incremented by every RE signal toggling, the internal address buses BUS0 and BUS1 are updated to the address ADD stored in the internal address counter main address counting flip flops [27:1] This depends from the value of the first bit cell [0] of the internal address counter.

With the illustrated architecture, the page buffer of the memory device is no longer directly connected to a counter that accomplishes the addition on the fly. On the contrary, the page buffer will receive the new latched address bits at the rising edge of CK_ADD after the addition has already been completed. Therefore, the risk of glitches is reduced.

CK_LOAD corresponds to the WEN signal only during an ALE cycle.

The input address values LOADADD are updated in the address loading flip flops F/F1 at the rising edge of CK_LOAD.

The main F/F2 or address counting flip flops are updated to the values in the address loading flip flops F/F1 at the rising of CK_ADD during the first toggling of the input WEN of a data cycle.

There is no need to increment the address at the first rising edge of the WEN signal during a data cycle. Therefore, the first rising edge of WEN can be exploited for updating the main address counting flip flops F/F2 to the address bits input during the ALE cycles.

During a first WEN cycle, LOAD_UPDATE is high and READCTRL_CLE is low and CK_ADD corresponds to WEN. Therefore, the address counting flip flops F/F2 of the cell can be updated to the loaded address bits present in the address loading flip flops F/F1 of the cell.

From the second WEN cycle onward, the column address is incremented and the internal address buses BUS0 and BUS1 are updated to the counted address [27:1] according to the value of the first cell [0] of the internal address counter.

As shown in FIG. 11 for a program operation, the address counter values are updated to the loaded address Values during the first WEN cycle of data cycle This is similar to a confirm cycle for read operation.

Therefore, when the external user inputs an address through ALE cycles, accessing a spare area of the array, the spare area address is loaded in the address loading flip flops F/F1 by CK_LOAD.

As explained above in discussing the counting problem of known address counters, in XS mode, the spare area access in case of a large page organization is addressed through the bit [11] (X8 mode).

Therefore, with the illustrated architecture, when the user sets the input address bit [11] to high, during the ALE cycles, AX_LOAD11 becomes high and it is possible to update the address bits A6-A10 to 00000 while the other address bits correspond to those of the input address in order to ensure a correct counter operation.

Claims

1. An address counter for a nonvolatile memory device comprising a memory cell array and a page buffer for storing data read from a selected memory array page and to be read therefrom starting from an addressed memory array location during a read sequence and during data input cycles to the device to be written starting from an addressed memory array location during a program sequence, the address counter comprising a cascade of elementary cells each including an address counting flip-flop (F/F2) that is updated to the value of every newly counted address bit (ADD) or latches a column address bit value (ADD) input by an external user of the memory device during ALE cycles for addressing said start memory location on the selected page at the rising edge of a clock signal (CK_ADD) generated by an input logic circuitry managing external user's commands, and a carry signal (CARRY) propagation logic circuit along the cascaded elementary cells that form the address counter, characterized in that each elementary cell of the address counter further comprises: an additional address loading flip-flop (F/F1) for loading such a column address bit value (LOADADD) input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page at the rising edge of said clock signal (CK_LOAD) during ALE cycles;logic circuit means for updating said address counting flip flop (F/F2) at the rising edge of said clock signal (CK_ADD) to said address bit value (LOADADD) input by an external user of the memory device during ALE cycles for addressing a start memory location on the selected page when is active an internally generated control signal (ENLOAD) that is raised during a read confirm cycle (30h) in a read sequence, and during a first data input cycle (D0), in a program sequence.

2. The address counter of claim 1, including circuit means for implementing a parallel data transfer scheme (pipeline), by generating, from each new counted address in the cells of said address counter, two distinct counted address buses (BUS0, BUS1), the second (BUS1) of which is without the first bit [0] and is updated every other toggling of an external user's read enable clock signal (RE) or write enable clock signal (WE) during a read or a program sequence, respectively, said circuit means of each cell of the address counter comprising first and second address buses (BUS0, BUS1) driving flip flops (F/F3, F/F4) and related circuit for updating the address bit content of said driving flip flops (F/F3, F/F4) at every change of the counted address in the address counting flip flop (F/F2) of cells of the address counter at the rising edge of the logic AND signal of said clock signal (CK_ADD) with the negate of the first bit value (ADD[0]) of the new counted address, for the first internal bus (BUS0), and with the direct first bit value (ADD[0 ]) of the new counted address, for the second internal bus (BUS1).

3. The address counter of claim 2, wherein during a read sequence said updating circuit of the bus driving flip flops (F/F3, F/F4) respectively updates one to the loaded externally input address value plus one and the other to the externally input address value at the instant the counted address in the counting flip flops (F/F2) of the address counter is incremented-by-two at the rising edge of the clock signal (CK_ADD) and thereafter, upon incrementing the address counter at every toggling of an external user's read enable command (RE), said internal address bus driving flip flops (F/F3, F/F4) are updated according to said first bit value (ADD[0]) of every new counted address.