Claims
- 1. An address generating circuit, comprising:
- a first memory for storing a start address;
- a second memory for storing an end address, wherein the end address is the same as or larger than the start address;
- a program counter for holding an instruction address, with a selection circuit connected to the program counter operable to selectively provide to the program counter either an address incremented in response to a clock signal when a loop-end control signal is inactive or the start address from the first memory when the loop-end control signal is active;
- a comparator connected to the program counter and the second memory, the comparator operable to activate a coincidence signal when the end address is equal to the instruction address;
- a third memory for holding a repeat count, the third memory operable to be decremented in response to a repeat count control signal being active;
- a control circuit connected to receive the coincidence signal from the comparator and connected to receive the repeat count from the third memory, the control circuit being connected to the selection circuit to provide the loop-end control signal in response to the coincidence signal and connected to provide the repeat count control signal to the third memory in response to the coincidence signal; and
- wherein the control circuit is operable to delay the repeat count control signal after an activation of the loop-end control signal by a preselected number of cycles of the clock signal.
- 2. The address generation circuit of claim 1, wherein the control circuit is operable to inactivate the loop-end control signal when the coincidence signal is activated during the preselected number of cycles of the clock signal immediately before the third memory is decremented to a value of zero.
- 3. The address generation circuit of claim 2, wherein the preselected number of cycles of the clock signal corresponds to a pipeline depth of a processor connected to the program counter; whereby the processor is operable to repeatedly execute a portion of a program a number of times according to the repeat count when the block size of the portion of the program is less than or equal to the preselected number of cycles.
- 4. The address generation circuit of claim 3, further comprising a pipeline flush signal connected to the control circuit, wherein the control circuit is further operable to inactivate the repeat count control signal in response to the pipeline flush signal being active, such that the repeat count in the third memory is not decremented when the pipeline flush signal is activated within the preselected number of cycles of the clock signal after activation of the coincidence signal; whereby the repeat count is not decremented when the pipeline of the processor is flushed within the preselected number of cycles of the clock signal after activation of the coincidence signal.
Priority Claims (1)
Number |
Date |
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6-042819 |
Mar 1994 |
JPX |
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Parent Case Info
This is a divisional application of U.S. patent application Ser. No. 08/402,224, Mar. 10, 1995, now U.S. Pat. No. 5,765,218.
US Referenced Citations (10)
Divisions (1)
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Number |
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402224 |
Mar 1995 |
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