Claims
- 1. A method of operating an integrated circuit comprising:
detecting an external voltage to the integrated circuit to determine whether the external voltage is above or below a threshold value; when the external voltage is below the threshold value, generating a programming voltage using a first number of charge pump stages; and when the external voltage is above the threshold value, generating the programming voltage using a second number of charge pump stages, wherein the second number of charge pump stages is less than the first number of charge pump stages.
- 2. A method of operating an integrated circuit comprising:
detecting an external voltage to the integrated circuit to determine whether the external voltage is above or below a first threshold level and above or below a second threshold level, wherein the second threshold level is above the first threshold level; when the external voltage is below the first threshold level, generating a programming voltage using a first number of charge pump stages; when the external voltage is above the first threshold level and below the second threshold level, generating the programming voltage using a second number of charge pump stages; when the external voltage is above the second threshold level, generating the programming voltage using a third number of charge pump stages, wherein the first number of charge pump stages is greater than the second number of charge pump stages, and the second number of charge pump stages is greater than the third number of charge pump stages.
- 3. The method of claims 1 or 2 further comprising:
configuring memory cells of the integrated circuit using the programming voltage.
- 4. The method of claim 3 wherein the memory cells are nonvolatile memory cells.
- 5. The method of claim 3 wherein the memory cells are Flash memory cells.
- 6. The method of claims 1 or 2 wherein the memory cells are analog memory cells.
- 7. The method of claims 1 or 2 wherein the memory cells are multilevel memory cells.
- 8. The method of claims 1 or 2 wherein detecting an external voltage occurs during power-up of the integrated circuit.
- 9. The method of claims 1 or 2 wherein detecting an external voltage occurs within 100 microseconds of initializing the integrated circuit.
- 10. The method of claims 1 or 2 wherein detecting an external voltage occurs continually during the operating of the integrated circuit.
- 11. The method of claim 2 wherein when the external voltage is below the first threshold level, generating a low battery signal.
- 12. The method of claim 2 wherein the first threshold level is about 2.7 volts and the second threshold level is about 3.3 volts.
- 13. The method of claim 2 wherein the first number of stages is eleven.
- 14. The method of claim 2 wherein the second number of stages is nine.
- 15. The method of claim 2 wherein the third number of stages is seven.
- 16. The method of claims 1 or 2 wherein the programming voltage is in a range from about 5 volts to about 16 volts.
- 17. An integrated circuit comprising:
a first voltage detect circuit of a first threshold level; a second voltage detect circuit of a second threshold level; a third voltage detect circuit of a third threshold level; a logic circuit, coupled to outputs of the first, second, and third voltage detect circuits, generating a plurality of enable outputs; and a charge pump circuit comprising a plurality of stages, wherein based on the enable outputs, a number of stages of the charge pump are enabled.
- 18. The integrated circuit of claim 17 wherein the first voltage detect circuit comprises:
a first transistor coupled between a first voltage detect output node and first terminals of a first and a second capacitor, wherein a control electrode of the first transistor is coupled to a clock signal; a second transistor coupled between the first voltage detect output node and the first terminals of the first and second capacitors, wherein a control electrode of the second transistor is coupled to the clock signal; a first switch circuit coupled between an external voltage input and a second terminal of the first capacitor; and a second switch circuit coupled between a reference voltage input and a second terminal of the second capacitor.
- 19. The integrated circuit of claim 18 further comprising:
a third transistor and fourth transistor coupled in series between an external supply voltage and the first voltage detect output node; and a fifth transistor coupled between an external reference voltage and the first voltage detect output node.
- 20. The integrated circuit of claim 18 further comprising:
a latch coupled to store a signal at the first voltage detect output node.
- 21. The integrated circuit of claim 17 further comprising:
a plurality of memory cells, wherein a configured state of the memory cells determines the first threshold level, second voltage level, and third voltage level.
- 22. The integrated circuit of claim 17 wherein a charge pump stage comprises:
a first transistor coupled between a charge pump stage input and a charge pump stage output; a second transistor coupled between a first gate of the first transistor and the charge pump stage input, wherein a second gate of the second transistor is coupled to the charge pump stage output; a first capacitor coupled between the charge pump stage output and a first clock signal; and a second capacitor coupled between the first gate and a second clock signal.
- 23. The integrated circuit of claim 21 wherein a configured state of a memory cell is stored in a register, and the register is resettable using a reset input.
- 24. The integrated circuit of claim 17 further comprising:
a plurality of analog memory cells, wherein the charge pump circuit generates a voltage used to configure the memory cells.
Parent Case Info
[0001] This application claims the benefit of U.S. provisional application No. 60/091,326, filed Jun. 30, 1998, and U.S. provisional application No. 60/116,760, filed Jan. 22, 1999, which are incorporated by reference.
Provisional Applications (2)
|
Number |
Date |
Country |
|
60091326 |
Jun 1998 |
US |
|
60116760 |
Jan 1999 |
US |
Continuations (2)
|
Number |
Date |
Country |
Parent |
10109353 |
Mar 2002 |
US |
Child |
10382333 |
Mar 2003 |
US |
Parent |
09343206 |
Jun 1999 |
US |
Child |
10109353 |
Mar 2002 |
US |