Patent Application
20100217564
The present invention relates to electronic design generally and, more particularly, to a method and/or apparatus for implementing an advanced physical simulator.
Digital integrated circuit designs can include application specific integrated circuits (ASICs) and application specific standard products (ASSPs). Simulation for digital design is performed using simulators including VCS, NCVerilog, and Modelsim. Simulation for digital design is limited because accurate timing (i.e., signoff timing) is not available from conventional simulators. Conventional simulators do not read spef files (i.e., files containing physical data). Conventional simulators do not include delay engines. Conventional simulators read standard delay format (SDF) files. The SDF files that can be read into conventional simulators contain delay estimates for nets rather than signoff accurate timing information. For example, crosstalk impact on clock nets is not accurately captured. Conventional simulators do not consider power consumption/supply information during simulation. Conventional simulators do not provide signoff quality simulation results.
There are a number of existing approaches toward solving the above problems. To address timing concerns, Hspice simulation can be run or a combination of simulation and static timing analysis (STA) can be performed. However, Hspice simulation is not reasonable due to the huge amount of data and run times. The combination of simulation and static timing analysis reduces, but does not eliminate, the risk of inaccurate simulation results.
To address power concerns, Hspice simulations can be run. However, as mentioned above, Hspice simulations are not reasonable due to the huge amount of data and run times. Additional tools can be run to evaluate/predict power status (i.e., demand vs. supply). However, simulation results can be invalid if power planning and implementation is not done correctly.
To address signing off of a chip, a combination of signoff tools/strategies including Hspice and STA can be used, but none can be used as a stand-alone method to tape out a chip. Existing approaches have a risk of failure in the area of functional verification. Also, existing approaches provide inefficient verification of a design by independently running power analysis, timing analysis and functional verification in parallel.
It would be desirable to have a physical simulator that provides accurate, signoff quality results.
The present invention concerns a method, which in an example embodiment provides advance physical simulation, including the steps of (A) reading design information for an integrated circuit from a computer readable storage medium, (B) reading library information and physical design information from the computer readable storage medium, (C) simulating the integrated circuit design based upon the library information and the physical design information using a computer, where the simulation of the integrated circuit design provides signoff accurate results and (D) determining whether the integrated circuit design meets one or more performance goals based upon results of the simulation of the integrated circuit design.
The objects, features and advantages of the present invention include providing an advanced physical simulator that may (i) provide simulation results with signoff quality, (ii) provide simulation results based on signoff data, (iii) provide simulation results reflecting power up/down sequences, (iv) provide simulation results reflecting impact of crosstalk, (v) reduce risks (e.g., silicon failure, functional risks, etc.), (vi) reduce turnaround time (TAT), (vii) provide an efficient signoff verification strategy, (viii) allow realistic planning of resources for simulation and design completion, (ix) allow extraction of data/recommendations to guide design closure (e.g., placement and power planning) and/or (x) allow qualification of library files based upon existing chip design.
These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
Referring to
In the step 106, net delays may be calculated based upon the cell library data, the process information and the design information using a computer. The process 100 may read a lef/def file to process/calculate the net delays. The lef/def file generally contains the actual route information for signals, instead of the estimated delay values as found in an SDF file. For simulation, the process 100 generally calculates the delay values by looking at active RC values for the net in a current state, which may be more accurate. Also, since the process 100 may access all the routing information, crosstalk, noise and common clock path related calculations for timing may be more accurate. When the net delays have been calculated, the process 100 may move to the step 108.
In the step 108, a simulation of the integrated circuit design described by the HDL, RTL, netlist, cell library data, process information and physical design information may be performed using the computer. In the step 110, the computer may be instructed to determine whether particular goals (e.g., timing, etc.) have been met based upon results of the simulation run in the step 108. When the timing goals are met, the process 100 may move to the step 112 where the simulation may terminate.
When the computer determines that the timing goals have not been met, the process 100 may move to the step 114. In the step 114, the designer may make changes to the HDL, RTL, the netlist and/or the goals. When the HDL, RTL, netlist and/or goal changes have been made, the process 100 may move to the step 116. In the step 116, the process 100 may read the new HDL, RTL or netlist, and testbench information and return to the step 104. The process 100 may be repeated until the computer determines, based upon the simulation results, that the particular (e.g., timing, etc.) goals are met.
Referring to
In the step 156, simulation may be run based upon the cell library data, the process information and the physical design information using a computer. For example, the step 156 may calculate net delays and run a simulation similarly to the steps 106 and 108 described above in connection with
When the power goals are determined not to have been met, the process 150 may move to the step 164, where the designer may make changes in the HDL, RTL, the netlist and/or the goals to be met. Once the designer has made the changes to the HDL, RTL, the netlist and/or the goals, the process 150 may move to the step 166. In the step 166, the process 150 may read the new HDL, RTL or netlist and testbench information and return to the step 154. The process 150 may be repeated until the simulator determines that the power goals are met.
Referring to
The storage medium 206 may store, in one example, a file 214, a file 216, a file 218, a file 220 and a file 222. The file 214 may contain predetermined target goals and/or target goals calculated by the software program 210. The file 216 may contain a circuit description using a hardware description language (e.g., HDL code, RTL code, etc.) representation of a chip design being created. The file 218 may contain a netlist of the chip being created. The file 220 may contain cell library data and process information to be used by the software program 210. The file 222 may contain physical design information for the integrated circuit design. The files 220 and 222 may be implemented as one or more lef/def files.
The software program 210 and tool programs 212 may be read and executed by the computer 202. The computer 202 and programs 210 and 212 may access the chip design data in the files 214-222 to perform an advanced physical simulation in accordance with embodiments of the present invention.
Referring to
In the step 306, net delays may be calculated based upon the cell library data, the process information and the physical design information using a computer. When the net delays have been calculated, the process 300 may move to the step 308. In the step 308, a simulation of the existing integrated circuit design may be run based upon the HDL, RTL or netlist information, the testbench information, the cell library data, the process information and the physical design information, using the computer. In the step 310, the computer may be instructed to determine whether timing goals have been met based upon results of the simulation run in the step 308. When the timing goals have been met, the process 300 may move to the step 312 where an indication may be presented that the simulation was completed successfully. Successful completion of the simulation may signal successful qualification of the lef/def file based upon the existing chip design.
When the simulator determines that the timing goals are not met, the process 300 may move to the step 314. In the step 314, the designer may make changes to the HDL, RTL, the netlist, the lef/def file and/or the goals. When the HDL, RTL, netlist, lef/def file and/or goal changes have been made, the process 300 may move to the step 316. In the step 316, the process 300 may read the new HDL, RTL, netlist or lef/def file, and testbench information and return to the step 306. The process 300 may be repeated until the computer determines, based upon the simulation results, that the particular goals are met by the lef/def file.
By adding the capability of accurate delay and power calculation directly into the simulation (e.g., using the routing information in the form of lef or def files) for timing and power verifications, the number of tools in a design flow may be reduced and the efficiency increased. The simulation results may be more accurate and may have signoff quality because the verification results are based on actual power calculation and signoff timing rather than estimated values.
An advanced physical simulator implemented in accordance with embodiments of the present invention may (i) provide simulation results with signoff quality, (ii) provide simulation results based on signoff data, (iii) provide simulation results reflecting power up/down sequences, (iv) provide simulation results reflecting impact of crosstalk, (v) reduce risks (e.g., silicon failure, functional risks, etc.), (vi) reduce turnaround time (TAT), (vii) provide an efficient signoff verification strategy, (viii) allow realistic planning of resources for simulation and design completion, (ix) allow extraction of data/recommendations to guide design closure (e.g., placement and power planning) and/or (x) allow qualification of library files based upon existing chip design.
The functions illustrated by the diagrams of
The present invention may also be implemented by the preparation of ASICs (application specific integrated circuits), Platform ASICs, FPGAs (field programmable gate arrays), PLDs (programmable logic devices), CPLDs (complex programmable logic device), sea-of-gates, RFICs (radio frequency integrated circuits), ASSPs (application specific standard products) or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s).
The present invention thus may also include a computer product which may be a storage medium or media and/or a transmission medium or media including instructions which may be used to program a machine to perform one or more processes or methods in accordance with the present invention. Execution of instructions contained in the computer product by the machine, along with operations of surrounding circuitry, may transform input data into one or more files on the storage medium and/or one or more output signals representative of a physical object or substance, such as an audio and/or visual depiction. The storage medium may include, but is not limited to, any type of disk including floppy disk, hard drive, magnetic disk, optical disk, CD-ROM, DVD and magneto-optical disks and circuits such as ROMs (read-only memories), RAMs (random access memories), EPROMs (electronically programmable ROMs), EEPROMs (electronically erasable ROMs), UVPROM (ultra-violet erasable ROMs), Flash memory, magnetic cards, optical cards, and/or any type of media suitable for storing electronic instructions.
The elements of the invention may form part or all of one or more devices, units, components, systems, machines and/or apparatuses. The devices may include, but are not limited to, servers, workstations, storage array controllers, storage systems, personal computers, laptop computers, notebook computers, palm computers, personal digital assistants, portable electronic devices, battery powered devices, set-top boxes, encoders, decoders, transcoders, compressors, decompressors, pre-processors, post-processors, transmitters, receivers, transceivers, cipher circuits, cellular telephones, digital cameras, positioning and/or navigation systems, medical equipment, heads-up displays, wireless devices, audio recording, storage and/or playback devices, video recording, storage and/or playback devices, game platforms, peripherals and/or multi-chip modules. Those skilled in the relevant art(s) would understand that the elements of the invention may be implemented in other types of devices to meet the criteria of a particular application.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.
