Patent Application
20250225624
Diffusion models refer to a class of generative models that learn to generate data by denoising. These models may implement two processes: (1) a forward process that adds increments of Gaussian noise to an input over repeated steps, and (2) a reverse generative process that transforms the noise into an output by iterative denoising.
Gaussian noise, also known as white noise, is a random signal that exhibits statistical properties following a Gaussian distribution, often referred to as a normal distribution. It is a type of noise that has a random distribution of values centered around zero with equal probability of positive and negative values. Gaussian noise is characterized by its constant power spectral density across all frequencies, making it have a flat frequency response. Gaussian noise is commonly encountered in signal processing and image processing applications. The random nature of Gaussian noise makes it useful for simulating and analyzing the effects of random disturbances or errors in systems. Gaussian noise may be added to images/video to mimic real-world noise sources and evaluate the performance of algorithms or systems under different noise conditions. Diffusion models may be utilized to inject Gaussian noise and additional conditioning signals into images or video.
Image generating artificial intelligence networks that utilize diffusion modelling may first generate a random (technically, pseudo-random) image in the model's latent space. A noise predictor then estimates the noise of the image. The predicted noise is subtracted from the image. This process is repeated to eventually generate a final (clean) output image. “Sampling” in this context is the process of generating a new sample image at processing at each iteration. The logic utilized to carry out sampling may be referred to as the ‘sampler’.
Conventional diffusion models for image and video generation exhibit aliasing effects in their output. These effects often manifest themselves in the form of texture-sticking or flickering artifacts in moving images. Conventionally, these artifacts are removed via ad-hoc post-processing steps such as by applying additional neural networks trained to filter out the artifacts.
To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which that element is first introduced.
Disclosed herein are alias-free diffusion models utilizing injected Gaussian noise for image and video generation. The disclosed mechanisms have applications including image and video super-resolution, video-to-video translation, 360 panorama generation, and image and video generation in general. The disclosed mechanisms may generate higher quality samples than conventional approaches.
The disclosed mechanisms utilize alias-free diffusion models that are translation equivariant with regards to their inputs. These models operate such that translations (changes in coordinates) of input noise, and conditioning of the output, does not introduce aliasing or flickering artifacts. The models may utilize a functional encoding of the input and provide translation equivariance under continuous translations of the input encoding. Gaussian noise distributions cannot be represented as a continuous function, and therefore the alias-free diffusion models may instead utilize Gaussian processes.
A Gaussian process is a stochastic process that defines a distribution over functions. A Gaussian process comprises a collection of randomized values, in which any finite subset thereof follows a multivariate Gaussian distribution. Gaussian processes provide a mechanism for non-parametric regression and probabilistic modeling by leveraging the properties of Gaussian distributions in defining relationships between data points. A Gaussian process is specified by a mean function m(x) and a covariance function k(x, x′). For any set of input points {x_1, x_2, . . . , x_n}, the output {y_1, y_2, . . . , y_n} follows a multivariate normal distribution.
The mean function m(x) represents an expected value of the process at any input x. The mean function may be assumed to be zero in some Gaussian processes. The covariance function defines the covariance between the process values at any two inputs x and x′. Choices for the covariance function include the squared exponential (Gaussian) kernel and the Matérn kernel.
Gaussian processes apply a set of sampled data points to predict the function values at new points. The joint distribution of the known points and the new points is assumed to be Gaussian, allowing the conditional distribution (the prediction) to also be Gaussian. The posterior mean and covariance of the new points are computed using the sampled data and the Gaussian process prior. This provides both a predicted mean function and uncertainty estimate at each new point.
A translation equivariant object or function behaves in a consistent manner under translations or shifts in the input space. In other words, upon a shift in the input signals, the output signals shift accordingly. One example involves an image and a convolutional neural network (CNN) applied to an image. If the CNN is translation equivariant, a translation of the input image (shifting it horizontally, vertically, or both) results in the output of the CNN exhibiting a matching translation.
In a translation-equivariant system, the relationship between input and output remains unchanged by the translation operation. This property is useful for example in computer vision tasks where objects or patterns of interest may appear at different locations in an image. Translation equivariance allows the system to detect the objects or patterns regardless of their position. Implementing translation equivariance may enable consistent outputs in the presence of spatial or temporal variations in the inputs.
The training of an alias-free diffusion model may be implemented using function-space diffusion models or function-space flow matching models. In one embodiment a denoising model may be trained by minimizing the relationship:
Parameter λt is a time-dependent weighting mechanism, σt is a time-dependent injected noise schedule, and αt is a time-dependent input rescaling coefficient. In one embodiment, αt=√{square root over (1−σt2)}. In one embodiment, σt may be determined by: σt==sin (0.5πt).
The selected Gaussian process may utilize a covariance function C comprising an RBF (radial basis function) kernel such as:
The covariance function, also known as a kernel function or covariance kernel, quantifies the covariance, or the statistical measure of the linear relationship, between two values. The covariance function defines the similarity or correlation between different data points in the Gaussian process. The covariance function processes input variables into a covariance metric between corresponding output variables. It measures how the outputs of the data points relate to each other based on the inputs. The covariance function may be utilized to model the underlying structure or patterns in the variables, enabling predictions or inference about unobserved values. Covariance functions come in various forms, such as the squared exponential covariance function, Matérn covariance function, or periodic covariance function. The choice of covariance function depends on the specific problem and the characteristics of the data being modeled, as different covariance functions capture different patterns or smoothness characteristics.
Fourier approximation is a mechanism that represents a function as a sum of sinusoidal functions with different frequencies and amplitudes. It is based on the Fourier series, which expresses a periodic function as an infinite sum of sine and cosine functions. The Fourier series representation of a function involves breaking down the function into its constituent frequencies. Each frequency component is represented by a sinusoidal function with a specific amplitude and phase. By summing up these frequency components, the original function is approximated as a sum of discrete terms. In practice, Fourier approximation can be performed using techniques such as the discrete Fourier transform (DFT) or the fast Fourier transform (FFT), which are efficient algorithms for calculating the Fourier series coefficients. These coefficients capture the amplitudes and phases of the sinusoidal components.
Random Fourier Features (RFF) calculation is a technique used to approximate the computation of the kernel trick in kernel methods, such as kernel support vector machines (SVMs) or kernel ridge regression. It takes advantage of the fact that certain kernel functions may be efficiently approximated using Random Fourier Features, making the computations faster and more scalable. In many kernel methods, the computation of the kernel function involves evaluating the pairwise similarity between each pair of data points in the dataset. This may be computationally expensive, especially for large datasets. Random Fourier Features provides an alternative approach to approximate the kernel function in a lower-dimensional feature space, reducing the computational complexity. Random Fourier Features applies a random projection that maps the original input space into a higher (possibly infinite) dimensional feature space. The random projection is designed in such a way that it approximates the kernel function. By using the random projection, the computation of the kernel function may be approximated as a simple inner product in the higher-dimensional space, which is computationally efficient. Random Fourier Features are particularly useful when the kernel function exhibits certain properties, such as being shift-invariant or translation-invariant, which allows for the efficient approximation using Fourier features. By employing Random Fourier Features, the dimensionality of the feature space may be reduced, leading to faster computation and scalability while maintaining a reasonable level of accuracy in many applications of kernel methods.
The Random Fourier Features outputs may be low-pass filtered to remove high-frequency components that introduce aliasing. To avoid aliasing artifacts, the frequency coefficient (ϕ) in Equation 3 below should not exceed the Nyquist frequency.
In one embodiment of the disclosed mechanisms, samples from a Gaussian process may be generated using Fourier approximation. They may be also generated efficiently using the Random Fourier Features technique by constructing random features:
The parameters l and the distribution of ψ should be chosen to avoid generation of aliasing effects.
The decoder 106, which follows after the encoder 104, reconstructs the original input tensor resolution from the condensed information. The decoder 106 comprises upsampling layers, usually transposed convolutions or bilinear upsampling, combined with skip connections 108 from the corresponding layers in the encoder path. The decoder 106 layers may for example be configured with ReLu (Rectified Linear Unit) or SiLu (Sigmoid Linear Unit) activations.
Skip connections enable the decoder 106 to leverage the high-resolution, low-level features learned by the encoder 104, preserving finer details during the upsampling process. To combine the information from the skip connections and the upsampling layers, concatenation (not depicted) may be applied. This enables the decoder 106 to exploit both high-level and low-level features, promoting localization accuracy.
The decoder 106 path may terminate with a 1×1 convolutional layer followed by a suitable activation function, such as sigmoid or Softmax. The output assigns a probability/prediction to regions or values of the input, indicating its likelihood of belonging to a specific class or category (e.g., noise or not). Overall, the U-Net architecture's symmetrical structure with skip connections enables it to effectively leverage both global contextual information and local details.
One or both of the encoder 104 and decoder 106 may also comprise normalization layers (not depicted).
The perturbed input xt and time variable t are transformed the by the network into a denoising model prediction Dθ(xt, t). The U-net network 102 may be translation equivariant.
A Denoising Diffusion Implicit Model (DDIM) is an advanced generative model useful for image synthesis. It is a type of diffusion model that generates a final output through a sequence of gradual transformations, generally starting from noise and converging to a clean image.
In a forward process, Gaussian noise is added to the input image over several steps to progressively corrupt it. In a reverse process, the model learns to denoise the corrupted inputs to reconstruct the original input. This process is guided by a neural network trained to reverse the diffusion steps. Unlike other types of diffusion models, DDIM may employ a non-Markovian process for the reverse process, specifically deterministic mappings between iterations, making the sample paths smoother and consistent. Instead of explicitly reversing each noise addition step, DDIM learns to estimate intermediate states. This reduces the number of required denoising steps, thereby speeding up generation without significant loss in quality.
A Denoising Diffusion Implicit Model (DDIM) may be used to generate samples, in one embodiment. A DDIM is sampler that utilizes the algorithm depicted in Equation 5 below to generate samples with a trained U-Net denoising model (Dθ(xt, t)).
The DDIM may apply the denoising model to approximate a final image with the denoised image produced at each step. The samples (image or video) generated by the model at the inference time may be generated using function space diffusion models or function-space flow matching frameworks. One embodiment of the disclosed mechanisms utilizes a DDIM sampler that determines an updated image sample for processing through the denoising network from one time step t to the next time step s and t where 0<s<t<1 as follows:
The DDM may generate the initial sample x1 as x1˜P(0,C) and iteratively generate xs from xt where s:=t−Δt and Δt is a small step size.
The upsampling layers of the decoder 106 may in one embodiment be implemented using a sinc interpolation kernel. The downsampling layers of the encoder 104 may be implemented with strided (stride>1) sampling and a low-pass filter front-end to omit high-frequency spectrum from the input to the strided sampling layer. Commonly utilized non-linear activations such as ReLU and Swish, and normalization layers such as layer norm may introduce high-frequency components that generate aliasing artifacts. These artifacts may be avoided by first upsampling the signal and then applying (e.g., via skip connections 108) the activations/norms in the upsampled domain before downsampling again.
In one embodiment, the denoising model may be constructed from a neural network such as the U-net network 102 above, and it may be trained to be equivariant via data augmentation. The denoising model may be trained by minimizing:
Embodiments alias-free diffusion model noise and image generators and processes as disclosed herein may be implemented as logic on computing devices utilizing one or more graphic processing unit (GPU) and/or general purpose data processor (e.g., a 'central processing unit or CPU). Exemplary architectures will now be described that may be configured by those of ordinary skill in the art to implement the mechanisms and processes disclosed herein.
The following description may use certain acronyms and abbreviations as follows:
One or more parallel processing unit 202 modules may be configured to accelerate thousands of High Performance Computing (HPC), data center, and machine learning applications. The parallel processing unit 202 may be configured to accelerate numerous deep learning systems and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and the like.
As shown in
The NVLink 216 interconnect enables systems to scale and include one or more parallel processing unit 202 modules combined with one or more CPUs, supports cache coherence between the parallel processing unit 202 modules and CPUs, and CPU mastering. Data and/or commands may be transmitted by the NVLink 216 through the hub 212 to/from other units of the parallel processing unit 202 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). The NVLink 216 is described in more detail in conjunction with
The I/O unit 204 is configured to transmit and receive communications (e.g., commands, data, etc.) from a host processor (not shown) over the interconnect 218. The I/O unit 204 may communicate with the host processor directly via the interconnect 218 or through one or more intermediate devices such as a memory bridge. In an embodiment, the I/O unit 204 may communicate with one or more other processors, such as one or more parallel processing unit 202 modules via the interconnect 218. In an embodiment, the I/O unit 204 implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus and the interconnect 218 is a PCIe bus. In alternative embodiments, the I/O unit 204 may implement other types of well-known interfaces for communicating with external devices.
The I/O unit 204 decodes packets received via the interconnect 218. In an embodiment, the packets represent commands configured to cause the parallel processing unit 202 to perform various operations. The I/O unit 204 transmits the decoded commands to various other units of the parallel processing unit 202 as the commands may specify. For example, some commands may be transmitted to the front-end unit 206. Other commands may be transmitted to the hub 212 or other units of the parallel processing unit 202 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the I/O unit 204 is configured to route communications between and among the various logical units of the parallel processing unit 202.
In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the parallel processing unit 202 for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (e.g., read/write) by both the host processor and the parallel processing unit 202. For example, the I/O unit 204 may be configured to access the buffer in a system memory connected to the interconnect 218 via memory requests transmitted over the interconnect 218. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the parallel processing unit 202. The front-end unit 206 receives pointers to one or more command streams. The front-end unit 206 manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the parallel processing unit 202.
The front-end unit 206 is coupled to a scheduler unit 208 that configures the various general processing cluster 300 modules to process tasks defined by the one or more streams. The scheduler unit 208 is configured to track state information related to the various tasks managed by the scheduler unit 208. The state may indicate which general processing cluster 300 a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit 208 manages the execution of a plurality of tasks on the one or more general processing cluster 300 modules.
The scheduler unit 208 is coupled to a work distribution unit 210 that is configured to dispatch tasks for execution on the general processing cluster 300 modules. The work distribution unit 210 may track a number of scheduled tasks received from the scheduler unit 208. In an embodiment, the work distribution unit 210 manages a pending task pool and an active task pool for each of the general processing cluster 300 modules. The pending task pool may comprise a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular general processing cluster 300. The active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by the general processing cluster 300 modules. As a general processing cluster 300 finishes the execution of a task, that task is evicted from the active task pool for the general processing cluster 300 and one of the other tasks from the pending task pool is selected and scheduled for execution on the general processing cluster 300. If an active task has been idle on the general processing cluster 300, such as while waiting for a data dependency to be resolved, then the active task may be evicted from the general processing cluster 300 and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the general processing cluster 300.
The work distribution unit 210 communicates with the one or more general processing cluster 300 modules via crossbar 214. The crossbar 214 is an interconnect network that couples many of the units of the parallel processing unit 202 to other units of the parallel processing unit 202. For example, the crossbar 214 may be configured to couple the work distribution unit 210 to a particular general processing cluster 300. Although not shown explicitly, one or more other units of the parallel processing unit 202 may also be connected to the crossbar 214 via the hub 212.
The tasks are managed by the scheduler unit 208 and dispatched to a general processing cluster 300 by the work distribution unit 210. The general processing cluster 300 is configured to process the task and generate results. The results may be consumed by other tasks within the general processing cluster 300, routed to a different general processing cluster 300 via the crossbar 214, or stored in the memory 220. The results can be written to the memory 220 via the memory partition unit 400 modules, which implement a memory interface for reading and writing data to/from the memory 220. The results can be transmitted to another parallel processing unit 202 or CPU via the NVLink 216. In an embodiment, the parallel processing unit 202 includes a number U of memory partition unit 400 modules that is equal to the number of separate and distinct memory 220 devices coupled to the parallel processing unit 202. A memory partition unit 400 will be described in more detail below in conjunction with
In an embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the parallel processing unit 202. In an embodiment, multiple compute applications are simultaneously executed by the parallel processing unit 202 and the parallel processing unit 202 provides isolation, quality of service (QoS), and independent address spaces for the multiple compute applications. An application may generate instructions (e.g., API calls) that cause the driver kernel to generate one or more tasks for execution by the parallel processing unit 202. The driver kernel outputs tasks to one or more streams being processed by the parallel processing unit 202. Each task may comprise one or more groups of related threads, referred to herein as a warp. In an embodiment, a warp comprises 32 related threads that may be executed in parallel. Cooperating threads may refer to a plurality of threads including instructions to perform the task and that may exchange data through shared memory. Threads and cooperating threads are described in more detail in conjunction with
In an embodiment, the operation of the general processing cluster 300 is controlled by the pipeline manager 302. The pipeline manager 302 manages the configuration of the one or more data processing cluster 312 modules for processing tasks allocated to the general processing cluster 300. In an embodiment, the pipeline manager 302 may configure at least one of the one or more data processing cluster 312 modules to implement at least a portion of a graphics rendering pipeline. For example, a data processing cluster 312 may be configured to execute a vertex shader program on the programmable streaming multiprocessor 500. The pipeline manager 302 may also be configured to route packets received from the work distribution unit 210 to the appropriate logical units within the general processing cluster 300. For example, some packets may be routed to fixed function hardware units in the pre-raster operations unit 304 and/or raster engine 306 while other packets may be routed to the data processing cluster 312 modules for processing by the primitive engine 314 or the streaming multiprocessor 500. In an embodiment, the pipeline manager 302 may configure at least one of the one or more data processing cluster 312 modules to implement a neural network model and/or a computing pipeline.
The pre-raster operations unit 304 is configured to route data generated by the raster engine 306 and the data processing cluster 312 modules to a Raster Operations (ROP) unit, described in more detail in conjunction with
The raster engine 306 includes a number of fixed function hardware units configured to perform various raster operations. In an embodiment, the raster engine 306 includes a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, and a tile coalescing engine. The setup engine receives transformed vertices and generates plane equations associated with the geometric primitive defined by the vertices. The plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for the primitive. The output of the coarse raster engine is transmitted to the culling engine where fragments associated with the primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. Those fragments that survive clipping and culling may be passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. The output of the raster engine 306 comprises fragments to be processed, for example, by a fragment shader implemented within a data processing cluster 312.
Each data processing cluster 312 included in the general processing cluster 300 includes an M-pipe controller 316, a primitive engine 314, and one or more streaming multiprocessor 500 modules. The M-pipe controller 316 controls the operation of the data processing cluster 312, routing packets received from the pipeline manager 302 to the appropriate units in the data processing cluster 312. For example, packets associated with a vertex may be routed to the primitive engine 314, which is configured to fetch vertex attributes associated with the vertex from the memory 220. In contrast, packets associated with a shader program may be transmitted to the streaming multiprocessor 500.
The streaming multiprocessor 500 comprises a programmable streaming processor that is configured to process tasks represented by a number of threads. Each streaming multiprocessor 500 is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently. In an embodiment, the streaming multiprocessor 500 implements a Single-Instruction, Multiple-Data (SIMD) architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads execute the same instructions. In another embodiment, the streaming multiprocessor 500 implements a Single-Instruction, Multiple Thread (SIMT) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In an embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. When execution state is maintained for each individual thread, threads executing the same instructions may be converged and executed in parallel for maximum efficiency. The streaming multiprocessor 500 will be described in more detail below in conjunction with
The memory management unit 310 provides an interface between the general processing cluster 300 and the memory partition unit 400. The memory management unit 310 may provide translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In an embodiment, the memory management unit 310 provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in the memory 220.
In an embodiment, the memory interface 406 implements an HBM2 memory interface and Y equals half U. In an embodiment, the HBM2 memory stacks are located on the same physical package as the parallel processing unit 202, providing substantial power and area savings compared with conventional GDDR5 SDRAM systems. In an embodiment, each HBM2 stack includes four memory dies and Y equals 4, with HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits.
In an embodiment, the memory 220 supports Single-Error Correcting Double-Error Detecting (SECDED) Error Correction Code (ECC) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. Reliability is especially important in large-scale cluster computing environments where parallel processing unit 202 modules process very large datasets and/or run applications for extended periods.
In an embodiment, the parallel processing unit 202 implements a multi-level memory hierarchy. In an embodiment, the memory partition unit 400 supports a unified memory to provide a single unified virtual address space for CPU and parallel processing unit 202 memory, enabling data sharing between virtual memory systems. In an embodiment the frequency of accesses by a parallel processing unit 202 to memory located on other processors is traced to ensure that memory pages are moved to the physical memory of the parallel processing unit 202 that is accessing the pages more frequently. In an embodiment, the NVLink 216 supports address translation services allowing the parallel processing unit 202 to directly access a CPU's page tables and providing full access to CPU memory by the parallel processing unit 202.
In an embodiment, copy engines transfer data between multiple parallel processing unit 202 modules or between parallel processing unit 202 modules and CPUs. The copy engines can generate page faults for addresses that are not mapped into the page tables. The memory partition unit 400 can then service the page faults, mapping the addresses into the page table, after which the copy engine can perform the transfer. In a conventional system, memory is pinned (e.g., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing the available memory. With hardware page faulting, addresses can be passed to the copy engines without worrying if the memory pages are resident, and the copy process is transparent.
Data from the memory 220 or other system memory may be fetched by the memory partition unit 400 and stored in the level two cache 404, which is located on-chip and is shared between the various general processing cluster 300 modules. As shown, each memory partition unit 400 includes a portion of the level two cache 404 associated with a corresponding memory 220 device. Lower level caches may then be implemented in various units within the general processing cluster 300 modules. For example, each of the streaming multiprocessor 500 modules may implement an L1 cache. The L1 cache is private memory that is dedicated to a particular streaming multiprocessor 500. Data from the level two cache 404 may be fetched and stored in each of the L1 caches for processing in the functional units of the streaming multiprocessor 500 modules. The level two cache 404 is coupled to the memory interface 406 and the crossbar 214.
The raster operations unit 402 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. The raster operations unit 402 also implements depth testing in conjunction with the raster engine 306, receiving a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine 306. The depth is tested against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the depth test for the sample location, then the raster operations unit 402 updates the depth buffer and transmits a result of the depth test to the raster engine 306. It will be appreciated that the number of partition memory partition unit 400 modules may be different than the number of general processing cluster 300 modules and, therefore, each raster operations unit 402 may be coupled to each of the general processing cluster 300 modules. The raster operations unit 402 tracks packets received from the different general processing cluster 300 modules and determines which general processing cluster 300 that a result generated by the raster operations unit 402 is routed to through the crossbar 214. Although the raster operations unit 402 is included within the memory partition unit 400 in
As described above, the work distribution unit 210 dispatches tasks for execution on the general processing cluster 300 modules of the parallel processing unit 202. The tasks are allocated to a particular data processing cluster 312 within a general processing cluster 300 and, if the task is associated with a shader program, the task may be allocated to a streaming multiprocessor 500. The scheduler unit 208 receives the tasks from the work distribution unit 210 and manages instruction scheduling for one or more thread blocks assigned to the streaming multiprocessor 500. The scheduler unit 504 schedules thread blocks for execution as warps of parallel threads, where each thread block is allocated at least one warp. In an embodiment, each warp executes 32 threads. The scheduler unit 504 may manage a plurality of different thread blocks, allocating the warps to the different thread blocks and then dispatching instructions from the plurality of different cooperative groups to the various functional units (e.g., core 508 modules, special function unit 510 modules, and load/store unit 512 modules) during each clock cycle.
Cooperative Groups is a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, enabling the expression of richer, more efficient parallel decompositions. Cooperative launch APIs support synchronization amongst thread blocks for the execution of parallel algorithms. Conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads ( ) function). However, programmers would often like to define groups of threads at smaller than thread block granularities and synchronize within the defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces.
Cooperative Groups enables programmers to define groups of threads explicitly at sub-block (e.g., as small as a single thread) and multi-block granularities, and to perform collective operations such as synchronization on the threads in a cooperative group. The programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. Cooperative Groups primitives enable new patterns of cooperative parallelism, including producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.
A dispatch 518 unit is configured within the scheduler unit 504 to transmit instructions to one or more of the functional units. In one embodiment, the scheduler unit 504 includes two dispatch 518 units that enable two different instructions from the same warp to be dispatched during each clock cycle. In alternative embodiments, each scheduler unit 504 may include a single dispatch 518 unit or additional dispatch 518 units.
Each streaming multiprocessor 500 includes a register file 506 that provides a set of registers for the functional units of the streaming multiprocessor 500. In an embodiment, the register file 506 is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file 506. In another embodiment, the register file 506 is divided between the different warps being executed by the streaming multiprocessor 500. The register file 506 provides temporary storage for operands connected to the data paths of the functional units.
Each streaming multiprocessor 500 comprises L processing core 508 modules. In an embodiment, the streaming multiprocessor 500 includes a large number (e.g., 128, etc.) of distinct processing core 508 modules. Each core 508 may include a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit. In an embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. In an embodiment, the core 508 modules include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.
Tensor cores configured to perform matrix operations, and, in an embodiment, one or more tensor cores are included in the core 508 modules. In particular, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In an embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A′B+C, where A, B, C, and D are 4×4 matrices.
In an embodiment, the matrix multiply inputs A and B are 16-bit floating point matrices, while the accumulation matrices C and D may be 16-bit floating point or 32-bit floating point matrices. Tensor Cores operate on 16-bit floating point input data with 32-bit floating point accumulation. The 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4×4×4 matrix multiply. In practice, Tensor Cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements. An API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use Tensor Cores from a CUDA-C++ program. At the CUDA level, the warp-level interface assumes 16×16 size matrices spanning all 32 threads of the warp.
Each streaming multiprocessor 500 also comprises M special function unit 510 modules that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In an embodiment, the special function unit 510 modules may include a tree traversal unit configured to traverse a hierarchical tree data structure. In an embodiment, the special function unit 510 modules may include texture unit configured to perform texture map filtering operations. In an embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from the memory 220 and sample the texture maps to produce sampled texture values for use in shader programs executed by the streaming multiprocessor 500. In an embodiment, the texture maps are stored in the shared memory/L1 cache 516. The texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail). In an embodiment, each streaming multiprocessor 500 includes two texture units.
Each streaming multiprocessor 500 also comprises N load/store unit 512 modules that implement load and store operations between the shared memory/L1 cache 516 and the register file 506. Each streaming multiprocessor 500 includes an interconnect network 514 that connects each of the functional units to the register file 506 and the load/store unit 512 to the register file 506 and shared memory/L1 cache 516. In an embodiment, the interconnect network 514 is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file 506 and connect the load/store unit 512 modules to the register file 506 and memory locations in shared memory/L1 cache 516.
The shared memory/L1 cache 516 is an array of on-chip memory that allows for data storage and communication between the streaming multiprocessor 500 and the primitive engine 314 and between threads in the streaming multiprocessor 500. In an embodiment, the shared memory/L1 cache 516 comprises 128 KB of storage capacity and is in the path from the streaming multiprocessor 500 to the memory partition unit 400. The shared memory/L1 cache 516 can be used to cache reads and writes. One or more of the shared memory/L1 cache 516, level two cache 404, and memory 220 are backing stores.
Combining data cache and shared memory functionality into a single memory block provides the best overall performance for both types of memory accesses. The capacity is usable as a cache by programs that do not use shared memory. For example, if shared memory is configured to use half of the capacity, texture and load/store operations can use the remaining capacity. Integration within the shared memory/L1 cache 516 enables the shared memory/L1 cache 516 to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data.
When configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. Specifically, the fixed function graphics processing units shown in
The parallel processing unit 202 may be included in a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and the like. In an embodiment, the parallel processing unit 202 is embodied on a single semiconductor substrate. In another embodiment, the parallel processing unit 202 is included in a system-on-a-chip (SoC) along with one or more other devices such as additional parallel processing unit 202 modules, the memory 220, a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like.
In an embodiment, the parallel processing unit 202 may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the parallel processing unit 202 may be an integrated graphics processing unit (iGPU) or parallel processor included in the chipset of the motherboard.
Systems with multiple GPUs and CPUs are used in a variety of industries as developers expose and leverage more parallelism in applications such as artificial intelligence computing. High-performance GPU-accelerated systems with tens to many thousands of compute nodes are deployed in data centers, research facilities, and supercomputers to solve ever larger problems. As the number of processing devices within the high-performance systems increases, the communication and data transfer mechanisms need to scale to support the increased bandwidth.
In another embodiment (not shown), the NVLink 216 provides one or more high-speed communication links between each of the parallel processing unit modules (parallel processing unit 202, parallel processing unit 202, parallel processing unit 202, and parallel processing unit 202) and the central processing unit 602 and the switch 604 interfaces between the interconnect 218 and each of the parallel processing unit modules. The parallel processing unit modules, memory 220 modules, and interconnect 218 may be situated on a single semiconductor platform to form a parallel processing module 606. In yet another embodiment (not shown), the interconnect 218 provides one or more communication links between each of the parallel processing unit modules and the central processing unit 602 and the switch 604 interfaces between each of the parallel processing unit modules using the NVLink 216 to provide one or more high-speed communication links between the parallel processing unit modules. In another embodiment (not shown), the NVLink 216 provides one or more high-speed communication links between the parallel processing unit modules and the central processing unit 602 through the switch 604. In yet another embodiment (not shown), the interconnect 218 provides one or more communication links between each of the parallel processing unit modules directly. One or more of the NVLink 216 high-speed communication links may be implemented as a physical NVLink interconnect or either an on-chip or on-die interconnect using the same protocol as the NVLink 216.
In the context of the present description, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit fabricated on a die or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation and make substantial improvements over utilizing a conventional bus implementation. Of course, the various circuits or devices may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. Alternately, the parallel processing module 606 may be implemented as a circuit board substrate and each of the parallel processing unit modules and/or memory 220 modules may be packaged devices. In an embodiment, the central processing unit 602, switch 604, and the parallel processing module 606 are situated on a single semiconductor platform.
In an embodiment, the signaling rate of each NVLink 216 is 20 to 25 Gigabits/second and each parallel processing unit module includes six NVLink 216 interfaces (as shown in
In an embodiment, the NVLink 216 allows direct load/store/atomic access from the central processing unit 602 to each parallel processing unit module's memory 220. In an embodiment, the NVLink 216 supports coherency operations, allowing data read from the memory 220 modules to be stored in the cache hierarchy of the central processing unit 602, reducing cache access latency for the central processing unit 602. In an embodiment, the NVLink 216 includes support for Address Translation Services (ATS), enabling the parallel processing unit module to directly access page tables within the central processing unit 602. One or more of the NVLink 216 may also be configured to operate in a low-power mode.
The exemplary processing system 700 also includes input devices 706, the parallel processing module 606, and display devices 708, e.g. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices 706, e.g., keyboard, mouse, touchpad, microphone, and the like. Each of the foregoing modules and/or devices may even be situated on a single semiconductor platform to form the exemplary processing system 700. Alternately, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user.
Further, the exemplary processing system 700 may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) through a network interface 710 for communication purposes.
The exemplary processing system 700 may also include a secondary storage (not shown). The secondary storage includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (DVD) drive, recording device, universal serial bus (USB) flash memory. The removable storage drive reads from and/or writes to a removable storage unit in a well-known manner.
Computer programs, or computer control logic algorithms, may be stored in the main memory 704 and/or the secondary storage. Such computer programs, when executed, enable the exemplary processing system 700 to perform various functions. The main memory 704, the storage, and/or any other storage are possible examples of computer-readable media.
The architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the exemplary processing system 700 may take the form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic.
While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
An application writes model data for a scene (e.g., a collection of vertices and attributes) to a memory such as a system memory or memory 220. The model data defines each of the objects that may be visible on a display. The application then makes an API call to the driver kernel that requests the model data to be rendered and displayed. The driver kernel reads the model data and writes commands to the one or more streams to perform operations to process the model data. The commands may reference different shader programs to be implemented on the streaming multiprocessor 500 modules of the parallel processing unit 202 including one or more of a vertex shader, hull shader, domain shader, geometry shader, and a pixel shader. For example, one or more of the streaming multiprocessor 500 modules may be configured to execute a vertex shader program that processes a number of vertices defined by the model data. In an embodiment, the different streaming multiprocessor 500 modules may be configured to execute different shader programs concurrently. For example, a first subset of streaming multiprocessor 500 modules may be configured to execute a vertex shader program while a second subset of streaming multiprocessor 500 modules may be configured to execute a pixel shader program. The first subset of streaming multiprocessor 500 modules processes vertex data to produce processed vertex data and writes the processed vertex data to the level two cache 404 and/or the memory 220. After the processed vertex data is rasterized (e.g., transformed from three-dimensional data into two-dimensional data in screen space) to produce fragment data, the second subset of streaming multiprocessor 500 modules executes a pixel shader to produce processed fragment data, which is then blended with other processed fragment data and written to the frame buffer in memory 220. The vertex shader program and pixel shader program may execute concurrently, processing different data from the same scene in a pipelined fashion until all of the model data for the scene has been rendered to the frame buffer. Then, the contents of the frame buffer are transmitted to a display controller for display on a display device.
The graphics processing pipeline 800 is an abstract flow diagram of the processing steps implemented to generate 2D computer-generated images from 3D geometry data. As is well-known, pipeline architectures may perform long latency operations more efficiently by splitting up the operation into a plurality of stages, where the output of each stage is coupled to the input of the next successive stage. Thus, the graphics processing pipeline 800 receives input data 601 that is transmitted from one stage to the next stage of the graphics processing pipeline 800 to generate output data 802. In an embodiment, the graphics processing pipeline 800 may represent a graphics processing pipeline defined by the OpenGL® API. As an option, the graphics processing pipeline 800 may be implemented in the context of the functionality and architecture of the previous Figures and/or any subsequent Figure(s).
As shown in
The data assembly 804 stage receives the input data 820 that specifies vertex data for high-order surfaces, primitives, or the like. The data assembly 804 stage collects the vertex data in a temporary storage or queue, such as by receiving a command from the host processor that includes a pointer to a buffer in memory and reading the vertex data from the buffer. The vertex data is then transmitted to the vertex shading 806 stage for processing.
The vertex shading 806 stage processes vertex data by performing a set of operations (e.g., a vertex shader or a program) once for each of the vertices. Vertices may be, e.g., specified as a 4-coordinate vector (e.g., <x, y, z, w>) associated with one or more vertex attributes (e.g., color, texture coordinates, surface normal, etc.). The vertex shading 806 stage may manipulate individual vertex attributes such as position, color, texture coordinates, and the like. In other words, the vertex shading 806 stage performs operations on the vertex coordinates or other vertex attributes associated with a vertex. Such operations commonly including lighting operations (e.g., modifying color attributes for a vertex) and transformation operations (e.g., modifying the coordinate space for a vertex). For example, vertices may be specified using coordinates in an object-coordinate space, which are transformed by multiplying the coordinates by a matrix that translates the coordinates from the object-coordinate space into a world space or a normalized-device-coordinate (NCD) space. The vertex shading 806 stage generates transformed vertex data that is transmitted to the primitive assembly 808 stage.
The primitive assembly 808 stage collects vertices output by the vertex shading 806 stage and groups the vertices into geometric primitives for processing by the geometry shading 810 stage. For example, the primitive assembly 808 stage may be configured to group every three consecutive vertices as a geometric primitive (e.g., a triangle) for transmission to the geometry shading 810 stage. In some embodiments, specific vertices may be reused for consecutive geometric primitives (e.g., two consecutive triangles in a triangle strip may share two vertices). The primitive assembly 808 stage transmits geometric primitives (e.g., a collection of associated vertices) to the geometry shading 810 stage.
The geometry shading 810 stage processes geometric primitives by performing a set of operations (e.g., a geometry shader or program) on the geometric primitives. Tessellation operations may generate one or more geometric primitives from each geometric primitive. In other words, the geometry shading 810 stage may subdivide each geometric primitive into a finer mesh of two or more geometric primitives for processing by the rest of the graphics processing pipeline 800. The geometry shading 810 stage transmits geometric primitives to the viewport SCC 812 stage.
In an embodiment, the graphics processing pipeline 800 may operate within a streaming multiprocessor and the vertex shading 806 stage, the primitive assembly 808 stage, the geometry shading 810 stage, the fragment shading 816 stage, and/or hardware/software associated therewith, may sequentially perform processing operations. Once the sequential processing operations are complete, in an embodiment, the viewport SCC 812 stage may utilize the data. In an embodiment, primitive data processed by one or more of the stages in the graphics processing pipeline 800 may be written to a cache (e.g. L1 cache, a vertex cache, etc.). In this case, in an embodiment, the viewport SCC 812 stage may access the data in the cache. In an embodiment, the viewport SCC 812 stage and the rasterization 814 stage are implemented as fixed function circuitry.
The viewport SCC 812 stage performs viewport scaling, culling, and clipping of the geometric primitives. Each surface being rendered to is associated with an abstract camera position. The camera position represents a location of a viewer looking at the scene and defines a viewing frustum that encloses the objects of the scene. The viewing frustum may include a viewing plane, a rear plane, and four clipping planes. Any geometric primitive entirely outside of the viewing frustum may be culled (e.g., discarded) because the geometric primitive will not contribute to the final rendered scene. Any geometric primitive that is partially inside the viewing frustum and partially outside the viewing frustum may be clipped (e.g., transformed into a new geometric primitive that is enclosed within the viewing frustum. Furthermore, geometric primitives may each be scaled based on a depth of the viewing frustum. All potentially visible geometric primitives are then transmitted to the rasterization 814 stage.
The rasterization 814 stage converts the 3D geometric primitives into 2D fragments (e.g. capable of being utilized for display, etc.). The rasterization 814 stage may be configured to utilize the vertices of the geometric primitives to setup a set of plane equations from which various attributes can be interpolated. The rasterization 814 stage may also compute a coverage mask for a plurality of pixels that indicates whether one or more sample locations for the pixel intercept the geometric primitive. In an embodiment, z-testing may also be performed to determine if the geometric primitive is occluded by other geometric primitives that have already been rasterized. The rasterization 814 stage generates fragment data (e.g., interpolated vertex attributes associated with a particular sample location for each covered pixel) that are transmitted to the fragment shading 816 stage.
The fragment shading 816 stage processes fragment data by performing a set of operations (e.g., a fragment shader or a program) on each of the fragments. The fragment shading 816 stage may generate pixel data (e.g., color values) for the fragment such as by performing lighting operations or sampling texture maps using interpolated texture coordinates for the fragment. The fragment shading 816 stage generates pixel data that is transmitted to the raster operations 818 stage.
The raster operations 818 stage may perform various operations on the pixel data such as performing alpha tests, stencil tests, and blending the pixel data with other pixel data corresponding to other fragments associated with the pixel. When the raster operations 818 stage has finished processing the pixel data (e.g., the output data 802), the pixel data may be written to a render target such as a frame buffer, a color buffer, or the like.
It will be appreciated that one or more additional stages may be included in the graphics processing pipeline 800 in addition to or in lieu of one or more of the stages described above. Various implementations of the abstract graphics processing pipeline may implement different stages. Furthermore, one or more of the stages described above may be excluded from the graphics processing pipeline in some embodiments (such as the geometry shading 810 stage). Other types of graphics processing pipelines are contemplated as being within the scope of the present disclosure. Furthermore, any of the stages of the graphics processing pipeline 800 may be implemented by one or more dedicated hardware units within a graphics processor such as parallel processing unit 202. Other stages of the graphics processing pipeline 800 may be implemented by programmable hardware units such as the streaming multiprocessor 500 of the parallel processing unit 202.
The graphics processing pipeline 800 may be implemented via an application executed by a host processor, such as a CPU. In an embodiment, a device driver may implement an application programming interface (API) that defines various functions that can be utilized by an application in order to generate graphical data for display. The device driver is a software program that includes a plurality of instructions that control the operation of the parallel processing unit 202. The API provides an abstraction for a programmer that lets a programmer utilize specialized graphics hardware, such as the parallel processing unit 202, to generate the graphical data without requiring the programmer to utilize the specific instruction set for the parallel processing unit 202. The application may include an API call that is routed to the device driver for the parallel processing unit 202. The device driver interprets the API call and performs various operations to respond to the API call. In some instances, the device driver may perform operations by executing instructions on the CPU. In other instances, the device driver may perform operations, at least in part, by launching operations on the parallel processing unit 202 utilizing an input/output interface between the CPU and the parallel processing unit 202. In an embodiment, the device driver is configured to implement the graphics processing pipeline 800 utilizing the hardware of the parallel processing unit 202.
Various programs may be executed within the parallel processing unit 202 in order to implement the various stages of the graphics processing pipeline 800. For example, the device driver may launch a kernel on the parallel processing unit 202 to perform the vertex shading 806 stage on one streaming multiprocessor 500 (or multiple streaming multiprocessor 500 modules). The device driver (or the initial kernel executed by the parallel processing unit 202) may also launch other kernels on the parallel processing unit 202 to perform other stages of the graphics processing pipeline 800, such as the geometry shading 810 stage and the fragment shading 816 stage. In addition, some of the stages of the graphics processing pipeline 800 may be implemented on fixed unit hardware such as a rasterizer or a data assembler implemented within the parallel processing unit 202. It will be appreciated that results from one kernel may be processed by one or more intervening fixed function hardware units before being processed by a subsequent kernel on a streaming multiprocessor 500.
Various functional operations described herein may be implemented in logic that is referred to using a noun or noun phrase reflecting said operation or function. For example, an association operation may be carried out by an “associator” or “correlator”. Likewise, switching may be carried out by a “switch”, selection by a “selector”, and so on. “Logic” refers to machine memory circuits and non-transitory machine readable media comprising machine-executable instructions (software and firmware), and/or circuitry (hardware) which by way of its material and/or material-energy configuration comprises control and/or procedural signals, and/or settings and values (such as resistance, impedance, capacitance, inductance, current/voltage ratings, etc.), that may be applied to influence the operation of a device. Magnetic media, electronic circuits, electrical and optical memory (both volatile and nonvolatile), and firmware are examples of logic. Logic specifically excludes pure signals or software per se (however does not exclude machine memories comprising software and thereby forming configurations of matter). Logic symbols in the drawings should be understood to have their ordinary interpretation in the art in terms of functionality and various structures that may be utilized for their implementation, unless otherwise indicated.
Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. A “credit distribution circuit configured to distribute credits to a plurality of processor cores” is intended to cover, for example, an integrated circuit that has circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., a power supply is not connected to it). Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.
The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function, although it may be “configurable to” perform that function after programming.
Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Accordingly, claims in this application that do not otherwise include the “means for” [performing a function] construct should not be interpreted under 35 U.S.C § 112(f).
As used herein, the term “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”
As used herein, the phrase “in response to” describes one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B.
As used herein, the terms “first,” “second,” etc. are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise. For example, in a register file having eight registers, the terms “first register” and “second register” can be used to refer to any two of the eight registers, and not, for example, just logical registers 0 and 1.
When used in the claims, the term “or” is used as an inclusive or and not as an exclusive or. For example, the phrase “at least one of x, y, or z” means any one of x, y, and z, as well as any combination thereof.
As used herein, a recitation of “and/or” with respect to two or more elements should be interpreted to mean only one element, or a combination of elements. For example, “element A, element B, and/or element C” may include only element A, only element B, only element C, element A and element B, element A and element C, element B and element C, or elements A, B, and C. In addition, “at least one of element A or element B” may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. Further, “at least one of element A and element B” may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B.
Although the terms “step” and/or “block” may be used herein to connote different elements of methods employed, the terms should not be interpreted as implying any particular order among or between various steps herein disclosed unless and except when the order of individual steps is explicitly described.
Having thus described illustrative embodiments in detail, it will be apparent that modifications and variations are possible without departing from the scope of the intended invention as claimed. The scope of inventive subject matter is not limited to the depicted embodiments but is rather set forth in the following Claims.
This application claims priority and benefit under 35 U.S.C. 119 (e) to U.S. Application Ser. No. 63/619,013, “Alias-Free Diffusion Models”, filed on Jan. 9, 2024, the contents of which are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63619013 | Jan 2024 | US |
