The present invention is generally related to digital computer systems, more particularly, to a system and method for selecting instructions comprising an instruction sequence.
Processors are required to handle multiple tasks that are either dependent or totally independent. The internal state of such processors usually consists of registers that might hold different values at each particular instant of program execution. At each instant of program execution, the internal state image is called the architecture state of the processor.
When code execution is switched to run another function (e.g., another thread, process or program), then the state of the machine/processor has to be saved so that the new function can utilize the internal registers to build its new state. Once the new function is terminated then its state can be discarded and the state of the previous context will be restored and execution resumes. Such a switch process is called a context switch and usually includes 10's or hundreds of cycles especially with modern architectures that employ large number of registers (e.g., 64, 128, 256) and/or out of order execution.
In thread-aware hardware architectures, it is normal for the hardware to support multiple context states for a limited number of hardware-supported threads. In this case, the hardware duplicates all architecture state elements for each supported thread. This eliminates the need for context switch when executing a new thread. However, this still has multiple draw backs, namely the area, power and complexity of duplicating all architecture state elements (i.e., registers) for each additional thread supported in hardware. In addition, if the number of software threads exceeds the number of explicitly supported hardware threads, then the context switch must still be performed.
This becomes common as parallelism is needed on a fine granularity basis requiring a large number of threads. The hardware thread-aware architectures with duplicate context-state hardware storage do not help non-threaded software code and only reduces the number of context switches for software that is threaded. However, those threads are usually constructed for coarse grain parallelism, and result in heavy software overhead for initiating and synchronizing, leaving fine grain parallelism, such as function calls and loops parallel execution, without efficient threading initiations/auto generation. Such described overheads are accompanied with the difficulty of auto parallelization of such codes using sate of the art compiler or user parallelization techniques for non-explicitly/easily parallelized/threaded software codes.
In one embodiment the present invention is implemented as a global interconnect system. The global interconnect system includes a plurality of resources having data for supporting the execution of multiple code sequences and a plurality of engines for implementing the execution of the multiple code sequences. A plurality of resource consumers are within each of the plurality of engines. A global interconnect structure is coupled to the plurality of resource consumers and coupled to the plurality of resources to enable data access and execution of the multiple code sequences, wherein the resource consumers access the resources through a per cycle utilization of the global interconnect structure.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements.
Although the present invention has been described in connection with one embodiment, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended claims.
In the following detailed description, numerous specific details such as specific method orders, structures, elements, and connections have been set forth. It is to be understood however that these and other specific details need not be utilized to practice embodiments of the present invention. In other circumstances, well-known structures, elements, or connections have been omitted, or have not been described in particular detail in order to avoid unnecessarily obscuring this description.
References within the specification to “one embodiment” or “an embodiment” are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearance of the phrase “in one embodiment” in various places within the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.
Some portions of the detailed descriptions, which follow, are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals of a computer readable storage medium and are capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as “processing” or “accessing” or “writing” or “storing” or “replicating” or the like, refer to the action and processes of a computer system, or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories and other computer readable media into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
Embodiments of the present invention utilize a front end scheduler, a plurality of segmented register files or a single register file, and a memory subsystem to implement fragmented address spaces for multiple cores of a multicore processor. In one embodiment, fragmentation enables the scaling of microprocessor performance by allowing additional virtual cores (e.g., soft cores) to cooperatively execute instruction sequences comprising one or more threads. The fragmentation hierarchy is the same across each cache hierarchy (e.g., L1 cache, L2 cache). The fragmentation hierarchy divides the address space into fragments using address bits, where the address bits are used such that the fragments are identified by bits that are above cache line boundaries and below page boundaries. Each fragment is configured to utilize a multiport bank structure for storage. Embodiments of the present invention are further described in the
The engines implement virtual cores, in accordance with a selected mode. An engine includes a segment, a fragment and a number of execution units. The resources within the engines can be used to implement virtual cores that have multiple modes. As provisioned by the virtual core mode, one soft core, or many soft cores, can be implemented to support one logical core/thread. In the
It should be noted that in a conventional core implementation, the resources within one core/engine are solely allocated to one logical thread/core. In contrast, in embodiments of the present invention, the resources of any engine/core can be partitioned, collectively with other engine/core partitions, to instantiate a virtual core that is allocated to one logical thread/core. Embodiments of the present invention can also implement multiple virtual execution modes in which those same engines can be partitioned to support many dedicated cores/threads or many dynamically allocated cores/threads, as well as configurations in which where all of the resources of all engines support the execution of a single core/thread. Some representative embodiments are further described below. In other embodiments of the current invention, the techniques of the current invention can be applied directly to a conventional multi-core implementation to enable efficient contestation, reservation and allocation of multi-core shared resources and interconnects. Similarly the current invention can be applied within a single core or compute engine to enable efficient contestation, reservation and allocation of any shared resources or interconnects within the core (i.e., ports, busses, execution units, caches, structures),
For example, the embodiments shown in
The memory global interconnect comprises a routing matrix that allows a plurality of cores (e.g., the address calculation and execution units 121-124) to access data that may be stored at any point in the fragmented cache hierarchy (e.g., L1 cache, load store buffer and L2 cache).
The execution global interconnect 110b similarly comprises a routing matrix allows the plurality of cores (e.g., the address calculation and execution units 121-124) to access data that may be stored at any of the segmented register files. Thus, the cores have access to data stored in any of the fragments and 2 data stored in any of the segments through the memory global interconnect 110a or the execution global interconnect 110b.
Additionally, it should be noted that the partitionable engines shown in
As described above, communication between the resources of each of the engines 11-14 is provided by an interconnection structure. By way of example, in the
The orchestrators 21-23 comprise controlled entities that direct the routing of a resource to a consumer. For example, in one embodiment, an orchestrator can be a thread scheduler that schedules a resource for transfer through the interconnect to a consumer that is ready for execution. The orchestrator (e.g., thread scheduler) identifies the correct resource, reserves the necessary bus, and causes the transfer of that resource to a selected consumer. In this manner, the orchestrator monitors the readiness of instructions and selects the execution units that will be used to execute the instructions. This information is used to orchestrate the transfer of the resource across the interconnect to the selected execution units (e.g., selected consumer) by contending the requests at the interconnect using the reservation and allocation logic as illustrated by either of
The interconnect comprises a routing matrix that allows a plurality of resource consumers, in this case, a plurality of cores (e.g., the address calculation and execution units 121-124), to access a resource, in this case data, that may be stored at any point in the fragmented cache hierarchy (e.g., L1 cache, load store buffer and L2 cache). The cores can similarly access data that may be stored at any of the segmented register files. Thus, the cores have access to data stored in any of the fragments and to data stored in any of the segments through the interconnect structure 30. In one embodiment, the interconnect structure comprises two structures, the memory interconnect 110a and the execution interconnect 110b, as shown and described above in the discussion of
Thus, the interconnect structure itself comprises a resource that must be shared by each of the cores of each of the partitionable engines. The interconnect structure 30 and the local interconnect structures 40-42 implement an interconnect structure that allows cores from any of the partitionable engines to access resources of any other of the partitionable engines. This interconnect structure comprises transmission lines that span all of the partitionable engines of the integrated circuit device, in the case of the interconnect structure, and span between engines of the integrated circuit device, in the case of the local interconnect structure.
Embodiments of the present invention implement a non-centralized access process for using the interconnects and the local interconnects. The finite number of global buses and local buses comprise resources which must be efficiently shared by the orchestrators. Additionally, a non-centralized access process is used by the orchestrators to efficiently share the finite number of ports that provide read/write access to the resources of each of the partitionable engines. In one embodiment, the non-centralized access process is implemented by the orchestrators reserving a bus (e.g., a local interconnect bus or an interconnect bus) and a port into the desired resource. For example, orchestrator 21 needs to reserve an interconnect and a port in order for consumer 1 to access resource 3, while orchestrator 22 to needs to reserve an interconnect and the port in order for consumer for to access resource 2.
It should be noted that this port allocation and reservation problem can be illustrated similar to the bus segment allocation table of
Embodiments of the present invention implement a non-centralized access process for using the interconnects and the local interconnects. Requests, accesses and controls can be initiated for shared interconnects, resources or consumers by multiple non-centralized fetchers, senders, orchestrators, or agents. Those non centralized requests, accesses and controls contend at the shared resources using variations of methods and logic implementation as described in this invention depending on the topologies and structures of those shared resources. By way of example, the resources of the engines and their read/write ports need to be efficiently shared by the cores. Additionally, the finite number of global buses and local buses comprise resources that need to be efficiently shared. In the
A reservation adder and a threshold limiter control access to each contested resource. As described above, to access a resource, a core needs to reserve the necessary bus and reserve the necessary port. During each cycle, orchestrators attempt to reserve the resources necessary to execute their pending instruction. For example, for an orchestrator scheduling an instruction I1 shown in
An orchestrator will not receive confirmation to execute its instruction unless all of its flags necessary to execute the instruction are set. Hence, the orchestrator will receive confirmation to execute the instruction if the flags for the necessary buses are set and the flags for the necessary read write ports are set. If a cancel signal is received for any of the flags, all flags for that orchestrator's request are cleared, and the request is queued until the next cycle.
In this manner, each of the orchestrators contends with each other for the resources on a cycle by cycle basis. Requests that are canceled are queued and given priority in the next cycle. This ensures that one particular core is not locked out of resource access for large number of cycles. It should be noted that the resources in the proposed implementations get assigned automatically to the resources, for example if the request succeed in obtaining a resource (e.g., it is not canceled by the adder and threshold logic) then the adder sum output corresponding to that request represent the resource number assigned to that request, thus completing the resource assignment without requiring any further participation from the orchestrators. This reservation and allocation adder and threshold limiters fairly balance access to contested resources in a decentralized manner (e.g., there is no need for requestors/orchestrators to actively participate in any centralized arbitration). Each remote orchestrator sends its requests to the shared resources, those requests that succeed will be granted resources/buses automatically.
As described above, embodiments of the present invention implement a non-centralized access process for using the interconnects and the local interconnects. The finite number of global buses and local buses comprise resources which must be efficiently shared by the cores. Thus, a reservation adder and a threshold limiter control access to each contested resource, in this case, the ports into each fragment. As described above, to access a resource, a core needs to reserve the necessary bus and reserve the necessary port.
The non-centralized access process for using the interconnects and the local interconnects employ the reservation adder and a threshold limiter control access to each contested resource, in this case, the ports into each segment. As described above, to access a resource, a core needs to reserve the necessary bus and reserve the necessary port.
The interconnect structure comprises a plurality of global segmented buses. The local interconnect structure comprises a plurality of locally connected engine to engine buses. Accordingly, to balance costs in both performance and fabrication, there are a finite number of global buses and a finite number of local buses. In the
In one embodiment, the global buses can be segmented into 3 portions. The segmentation allows the overall length of the global buses to be adjusted in accordance with the distance of the global access. For example, an access by consumer 1 to resource 4 would span the entire bus, and thus not be segmented. However, an access by consumer 1 to resource 3 would not span the entire bus, and thus the global bus can be segmented between resource 3 and resource 4.
In the
The
The
The
It should be noted that the sender model and the fetch model of an interconnect can be simultaneously supported using a common interconnect structure and a common contesting mechanism. This is shown by the similarity of the diagram of
It should be noted that current presentations in the current invention of different models of communications (Sender, Fetch, Orchestrator, etc.) and different interconnect topologies (point to point busses, multi-bus, and segmented busses, etc.) should not be interpreted as the only communication modes or the only interconnect topologies applicable to the current invention. To the contrary, one skilled in the art can easily mix and match the different contestation, reservation and allocation techniques of the current invention with any communication mode or bus topology.
It should be further noted that the described embodiments of the current invention present interconnects alongside the resources. This should be understood as a generalized illustration meant to show a broader set of possibilities for implementing the current invention, but it should be noted that the meaning of interconnects as used in the current invention is not limited to data interconnects between different cores or compute engines or between register files or memory fragments, but refers also to the control interconnects that carry the requests to the resources and the physical interconnects that carry data from structures (i.e., register file ports, memory ports, array decoder busses, etc.). This broader meaning is illustrated in
For purposes of explanation, the foregoing description refers to specific embodiments that are not intended to be exhaustive or to limit the current invention. Many modifications and variations are possible consistent with the above teachings. Embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, so as to enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as may be suited to their particular uses.
The present application is a continuation of U.S. patent application Ser. No. 13/475,708, filed May 18, 2012, entitled “DECENTRALIZED ALLOCATION OF RESOURCES AND INTERCONNECT STRUCTURES TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES,” naming Mohammad Abdallah as inventor, and which is herein incorporated by reference in its entirety, and which claims the benefit of commonly assigned U.S. Provisional Patent Application Ser. No. 61/488,662, titled “DECENTRALIZED ALLOCATION OF RESOURCES AND INTERCONNECT STRUCTURES TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES” by Mohammad A. Abdallah, filed on May 20, 2011, and which is incorporated herein in its entirety.
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Number | Date | Country | |
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20170068534 A1 | Mar 2017 | US |
Number | Date | Country | |
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61488662 | May 2011 | US |
Number | Date | Country | |
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Parent | 13475708 | May 2012 | US |
Child | 15354742 | US |