Patent Application
20080157910
The field of invention relates generally to on-die inductively coupled wires, and, more specifically, to on-die inductively coupled wires having improved electrical power consumption efficiency through reduced eddy currents.
Referring to
In order to create a strong “coupling” between the induced signal Is and the primary signal Ip, the magnetic properties of the magnetic core 104 should be sufficiently “soft”. Referring to the hysteresis loop 140 of
The strength of the magnetic field strength H may be made to increase for a given primary signal by looping the primary wire around the magnetic core a number of times. Similarly, the magnitude of the response signal Is may be made to increase by looping the secondary wire a number of times around the magnetic core 104. The magnetic properties of the core 104 and the number of windings associated with the primary and/or secondary signals may be specially designed so that the inductively coupled wires can be used as a transformer where the amplitudes of the primary and secondary signals have a specific designed for ratio. In the case of a 1:1 primary: secondary winding ratio (i.e., each wire runs once through the core) the inductively coupled wires effectively form an inductor in which a voltage V appears across the secondary wire as a function of K(∂Ip/∂t).
A problem with inductively coupled wires is the generation of eddy currents within the magnetic core. Here, the phenomena described by Faraday's law induces electrical currents to flow within the magnetic core 104. These currents cause the magnetic core to consume electrical power owing to the electrical power consumption relationship P=I2R where P is the electrical power consumed by the magnetic core, I is the magnitude of an eddy current that flows through the magnetic core and R is the electrical resistance of the magnetic core through which the eddy current flows. The power consumption of the magnetic core can be reduced by increasing the inherent resistivity of the magnetic core 104. Here, a higher resistivity will result in less eddy current in the magnetic core. This, in turn, drops the overall power consumption of the core because power consumption is a function of the square of the eddy current flow.
In the manufacture of electronic systems, there exists economic efficiency in integrating as many electronically interconnected components as possible with a single manufacturing process. This often results in a motivation to combine as many electronic components as possible onto a single “die” of processed semiconductor material. Moreover, it is not uncommon for a packaged semiconductor chip to be designed to use a voltage regulator that that is located external to the semiconductor chip package on the same “planar” or “PC board” that the semiconductor chip package is mounted to. The voltage regulator essentially suppresses variations in a power supply voltage that is ideally a constant, DC voltage. As is well known in the art, voltage regulators may be built with an “LC” filter where L corresponds to an inductor that physically resides external to the semiconductor chip package.
With the need for a voltage regulator and the need to integrate as many electronic components onto a semiconductor die as is possible, a motivation exists to build “on-die” voltage regulators. That is, a motivation exists to construct a voltage regulator into the various layering of conductive and dielectric materials that are processed onto a semiconductor wafer, which is subsequently cut into a “die and packaged.
By eliminating the need for an external voltage regulator printed circuit board space is conserved which should lower the manufacturing costs of the printed circuit board end-product.
According to the on die inductively coupled wiring design of
In order to reduce the detrimental effects of eddy currents, the magnetic core material constructed from magnetic layers 204, 213 should exhibit sufficiently high electrical resistance while maintaining sufficiently “soft” magnetic properties. As described in the background, high electrical resistance suppresses the flow of any induced eddy currents. That is, the overall magnitude of induced electrical current flow from eddy currents will be lower in a magnetic core material having higher electrical resistance than an otherwise identical magnetic core material having lower electrical resistance. Because the magnitude of the induced eddy currents is lower, the energy loss (or power consumption) of the inductively coupled wires will be reduced resulting in a more electrically efficient device. Also, for the reasons discussed above in the background with respect to the hysteresis loop of
The following dimensions as depicted in
According to this design, sufficiently soft magnetic properties for both the lower and higher magnetic layers 204, 213 corresponds to a saturation magnetic flux density (βSAT) of greater than 1.0 Tesla (T) and a magnetic coercivity (Hc) of less than 10.0 Oersteds (Oe)). Moreover, in order to sufficiently suppress the magnitude of induced eddy currents, both the lower and higher magnetic layers 204, 213 are also designed to have resistivities higher than 140 μΩ·cm and preferably at least as high as 400 μΩ·cm. Here, note that the magnetic flux density and the coercivity are each measured along the x axis while the resistivity is measured along the z axis of
FIGS. 3_A through 3_G show a process flow for forming on die inductively coupled wires as described above including magnetic layering having both sufficiently soft magnetic properties to maintain magnetic coupling efficiency and sufficiently high resistivity to improve power dissipation efficiency. According to FIG. 3_A, a nitride passivation layer 301 (e.g., Si3N4) is coated over the highest interconnect metal wiring level 300 that has been formed over the semiconductor die. Then, a seed layer 302 for promoting the deposition of the lower magnetic layer, discussed in more detail below, is deposited by plasma vapor deposition (PVD) over the nitride layer 301. According to one possible approach, the seed layer 302 may be any of Copper (Cu), Cobalt (Co), Platinum (Pt), Palladium (Pd), an alloy of Aluminum (Al) or an alloy of AlxCu1-x or NixFe1-x (where x is within a range of 0-1). Ranges of process parameters suitable for depositing the seed layer by PVD include: 1) wafer pressure=3000-6000 mtorr; 2) DC power=4000-40000 Watts; 3) Ar gas flow=2-20 sccm; 4) temperature set point=20-35° C.
After the seed layer 302 is deposited, a layer of photoresist 303 is coated over the wafer (e.g., by being spun on) and is patterned with photolithography techniques to form an opening where the lower magnetic layer is to be formed. The lower magnetic layer 304 is then formed by electroless-plating or electroplating an Cobalt(Co)-Tungsten(W)-Boron(B) film over the seed layer 302 in the presence of an applied magnetic field along the x axis. As discussed more thoroughly below, the lower magnetic layer 304 is formed with a sufficient amount of Co to keep the film “soft” in magnetic terms and with a sufficient amount of W and B to keep the film amorphous so that the electrical resistivity of the film is high. Workable respected percentage ranges of W and B are believed to be approximately 10-40% for W and 1-10% for B.
A pertinent aspect associated with a magnetic film 304 made of Co, W and B is that the film 304 is amorphous rather than single crystalline because of the introduction of W and B. Here, because of the non-uniformity in the arrangement of the atoms within an amorphous layer, a higher resistivity results as compared to a single crystalline film (which would have a continuous and regular arrangement of atoms) or a poly-crystalline film (which would have sizeable grains of crystalline material). Thus, in a more general sense, the higher resistance stems from the purposeful deposition of an amorphous magnetic layer 304.
Moreover, the lower magnetic layer 304 is kept sufficiently soft (magnetically speaking) due to its amorphous nature and the application of the applied magnetic field during the layer's deposition. The application of the magnetic field during the deposition of the lower magnetic layer 304 causes the film to exhibit uniaxial anisotropy such that the magnetic moment of the film “prefers” to point substantially in either direction along the x axis. The uniaxial anisotropy, the high BSAT and the low coercvity all stem from the sufficiently high percentage of Co in the lower magnetic layer.
As mentioned above, the lower magnetic layer may be formed with either electroless-plating or electroplating. According to one embodiment, the plating bath for the deposition of the lower magnetic layer 304 includes: 1) 0.01 to 0.05 Moles/Liter (M) of Co2+; 2) 0.1-0.5 M of a complexing agent to prevent the precipitation of Co hydroxide from the solution at high pH levels (a possible complexing agent includes citrate); 3) 0.001-0.05 M of a sulfate or chloride electrolyte that includes WO42− (here, the sulfate or chloride acts as counter ion for charge neutrality to counter-balance the presence of Co2+ ions, and, the WO42− acts as a source of W for deposition); 4) a pH buffer such as BO33− to help maintain a constant pH level of the solution; and, 5) 0.02-0.2 M of dimethylamineborane ((CH3)2NH:BH3) which acts as a source of boron as well as a reducing agent (i.e., a source of electrons to convert the Co2+ ions into Co atoms for deposition). According to one embodiment, the pH level is kept within a range of 8.3-9.7, the temperature is kept within a range of 50° C. to 80° C. and the applied electric field is within a range of 100 Oe-1000 Oe.
The applicable chemical reactions are as follows.
For the deposition of Co:
(CH3)2NH:BH3+3H2O+OH−+3Co2+(CH3)2NH2++B(OH)4−+5H++3Co Eqn. 1.
For the deposition of W:
WO22++(CH3)2NH:BH3+4H2O→W+(CH3)2NH2++B(OH)4−+3H Eqn. 2.
For the deposition of B:
(CH3)2NH:BH3+H++→BH3+(CH3)2NH2++B+1.5H2+(CH3)2NH+ Eqn. 3
Magnetically soft amorphous layers having resistivities as high as 700 μΩ·cm have been achieved with the above described process.
As mentioned above the seed layer 302 is used to initiate these chemical reactions. According to one approach, the minimum thickness of the seed layer 302 is bounded so that the magnetic layer does not oxidize during the highest temperatures that will be applied to the wafer during subsequent processing. As the particular inductively coupled wires depicted in FIGS. 3hd —A through 3_G is constructed above the highest layer of metal interconnect 300, the highest temperatures are expected to be no higher than 200° C. to 300° C. for current processes. The maximum thickness of the seed layer is bounded so that the magnetic properties of the magnetic layer are not diluted. It is believed that a seed layer thickness range of 200 to 800 Å should be sufficient for current processes.
Referring to FIG. 3_B, after the lower magnetic layer 304 is formed, the photoresist layer 303 (see
After etching any nitride layer 301 that resides over an I/O wire 306 to expose the I/O wire 306 (noting that the portions of the nitride layer 301 beneath magnetic layer 304 and lower dielectric layer 305 are not removed by the etch because they are protected by respective layers 304, 305), referring now to
Another layer of photoresist 350 is deposited, patterned and etched to create regions where electrically conductive wiring such as contact via 308 and primary and secondary wires 309 and 310, respectively are later deposited. In one embodiment the electrically conductive wiring is composed of Cu. In this case, the barrier/seed layer 307 acts as a barrier layer for the Cu contact via 308 and primary, secondary wiring metal 309, 310. After removing the photoresist 350, the higher layer dielectric 311 is then deposited or spun on over the wafer as depicted in FIG. 3_E.
Another layer of photoresist (not shown) is subsequently applied, patterned and etched to expose openings over any contact vias (such as contact via 308) and over the lower magnetic layer 304 where the interlayer lower and higher magnetic layers are to be connected. As depicted in FIG. 3_F, after removing the photoresist, another seed layer 312 similar to seed layer 302 is then deposited over the wafer. According to one embodiment, seed layer 312 (like seed layer 302) is formed by depositing Cu, Co, Pt, Pd, an Al alloy or an AlxCu1-x alloy. Another layer of photoresist 351 is then applied, patterned and etched to form an opening where the higher magnetic layer 313 is to be deposited.
As depicted in FIG. 3_G, the higher magnetic layer 313 is deposited. Like lower magnetic layer 304, higher magnetic layer 313 may be a material that includes Co, W and B having enough Co to exhibit soft magnetic properties yet having enough W and B to be amorphous so as to exhibit high resistivity. Also, plating solutions like those described above used to deposit lower magnetic layer 304 may also be used to deposit higher magnetic layer 313. After removing the resist, seed layer 312 is removed everywhere except beneath the higher magnetic layer 313.
Referring to
It will be evident to one of ordinary skill that the secondary wire 210, 310 of
The semiconductor die on which the inductively coupled wires are integrated may be a semiconductor die used to implement a component within a computing system.
The one or more processors 401 execute instructions in order to perform whatever software routines the computing system implements. The instructions frequently involve some sort of operation performed upon data. Both data and instructions are stored in system memory 403 and cache 404. Cache 404 is typically designed to have shorter latency times than system memory 403. For example, cache 404 might be integrated onto the same silicon chip(s) as the processor(s) and/or constructed with faster SRAM cells whilst system memory 403 might be constructed with slower DRAM cells. By tending to store more frequently used instructions and data in the cache 404 as opposed to the system memory 403, the overall performance efficiency of the computing system improves
System memory 403 is deliberately made available to other components within the computing system. For example, the data received from various interfaces to the computing system (e.g., keyboard and mouse, printer port, LAN port, modem port, etc.) or retrieved from an internal storage element of the computing system (e.g., hard disk drive) are often temporarily queued into system memory 403 prior to their being operated upon by the one or more processor(s) 401 in the implementation of a software program.
Similarly, data that a software program determines should be sent from the computing system to an outside entity through one of the computing system interfaces, or stored into an internal storage element, is often temporarily queued in system memory 403 prior to its being transmitted or stored. The ICH 405 is responsible for ensuring that such data is properly passed between the system memory 403 and its appropriate corresponding computing system interface (and internal storage device if the computing system is so designed).
The MCH 402 is responsible for managing the various contending requests for system memory 403 access amongst the processor(s) 401, interfaces and internal storage elements that may proximately arise in time with respect to one another. One or more I/O devices 408 are also implemented in a typical computing system. I/O devices generally are responsible for transferring data to and/or from the computing system (e.g., a networking adapter); or, for large scale non-volatile storage within the computing system (e.g., hard disk drive). ICH 405 has bi-directional point-to-point links between itself and the observed I/O devices 408.
In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
