Patent Application
20240339535
This application claims priority based on Japanese Patent Application No. 2023-061667 filed on Apr. 5, 2023, and the entire contents of the Japanese patent applications are incorporated herein by reference.
The present disclosure relates to an amplifier circuit.
There is known an amplifier circuit in which a source-grounded field effect transistor (FET) and a gate-grounded FET are cascode-connected, as a high frequency amplifier circuit (for example, Non-Patent Document 1: Proceeding of 2019 15th Conference on Ph. D Research in Microelectronics and Electronics (PRIME), pp. 165 to 168, Ferdinando Costanzo et al. “A Ka-band Doherty Power Amplifier using an innovative Stacked-FET Cell”).
An amplifier circuit according to the present disclosure includes: a first FET (Field Effect Transistor) including a first source electrode provided on the semiconductive layer and connected to a first reference potential in a high frequency manner, a first gate electrode provided on the semiconductive layer and inputting a high frequency signal, a first drain electrode provided on the semiconductive layer, and a first field plate having at least a part thereof provided above the semiconductive layer between the first gate electrode and the first drain electrode; and a second FET including a second source provided on the semiconductive layer and electrically connected to the first drain, a second gate provided on the semiconductive layer and connected to a second reference potential in the high frequency manner, a second drain provided on the semiconductive layer and outputting a high frequency signal, and a second field plate having at least a part thereof provided above the semiconductor layer between the second gate electrode and the second drain electrode; wherein a first distance between an end closer to the first drain electrode in ends of a surface of the first gate electrode facing the semiconductor layer and an end closer to the first drain electrode in ends of the first field plate is shorter than a second distance between an end closer to the second drain electrode in ends of a surface of the second gate electrode facing the semiconductor layer and an end closer to the second drain electrode in ends of the second field plate.
When a field plate is used for the FETs of the cascode-connected amplifier circuit, it is required to provide the field plate so as to improve the characteristics of the amplifier circuit.
The present disclosure has been made in view of the above problem, and an object of the present disclosure is to improve the characteristics of the amplifier circuit.
First, the contents of the embodiments of this disclosure are listed and explained.
Specific examples of a cascode amplifier and a method for manufacturing the same according to embodiments of the present disclosure will be described below with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, but is defined by the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.
A gate bias voltage VG1 of the FET Q1 is applied to the gate G1. A gate bias voltage VG2 of the FET Q2 is applied to the gate G2. A drain bias voltage VD of the FET Q2 is applied to the drain D2 of the FET Q2. An impedance matching circuit (not illustrated) and a bias circuit (not illustrated) that supplies the gate bias voltage VG1 to the gate G1 are connected between the gate G1 and the input terminal Tin. A bias circuit (not illustrated) that supplies the gate bias voltage VG2 to the gate G2 is connected to the gate G2. An impedance matching circuit (not illustrated) and a bias circuit (not illustrated) that supplies the drain bias voltage VD to the drain D2 are connected between the drain D2 and the output terminal Tout. The gate widths of the FET Q1 and the FET Q2 may be the same as each other or different from each other.
The FETs Q1 and Q2 are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors). The FETs Q1 and Q2 may be GaAs-based FETs.
A center frequency of the band of the amplifier circuit 100 is, for example, 0.5 GHz to 10 GHZ, and is used in a base station of mobile communication, for example.
As illustrated in
A field plate 20a (first field plate) and a field plate 20b (second field plate) are provided in the insulating film 28. Each of the field plates 20a and 20b includes a bottom portion 21a and a top portion 21b. The bottom portion 21a is provided between the gate electrode 18 and the drain electrode 16, and above the semiconductor layer 12 across the insulating film 28. A lower surface of the bottom portion 21a is substantially parallel to an upper surface of the semiconductor layer 12. The top portion 21b is provided from the bottom portion 21a to a position above the gate electrode 18 (+Z direction). Each of the field plates 20a and 20b is electrically connected and short-circuited to the source electrode 14 by a connection wiring 22. As a result, the potential of the source electrode 14 and the potential of the field plates 20a and 20b become substantially the same as each other. The connection wiring 22 may pass over the gate electrode 18 in the active region 11 and be electrically connected to the source electrode 14. The potentials of the field plates 20a and 20b may be potentials other than the potential of the source electrode 14. The FETs Q1 and Q2 may be multi-finger type FETs.
At least a part of each of the field plates 20a and 20b is positioned above the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16, so that the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 can be reduced. This improves the gate-drain breakdown voltage. In addition, the memory effect described later can be suppressed. Further, a gate-drain capacitance Cgd can be reduced. At least a part of the top portion 21b overlaps at least a part of the gate electrode 18 as viewed from the Z direction, thereby further suppressing the gate-drain capacitance Cgd. The top portion 21b and the gate electrode 18 may not overlap each other when viewed from the Z direction.
As illustrated in
As illustrated in
A distance between the source electrode 14 and the gate electrode 18 is a source-gate distance Lsg, a distance between the gate electrode 18 and the drain electrode 16 is a gate-drain distance Lgd, and a length of the gate electrode 18 in the X direction is a gate length Lg. A width of the active region 11 in the Y direction is a gate width Wg. In the FET Q1 of
In the case of a GaN HEMT, the substrate 10 is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, or a gallium nitride (GaN) substrate. The channel layer 12a is, for example, a gallium nitride layer, and the barrier layer 12b is an aluminum gallium nitride (AlGaN) layer. Each of the source electrode 14 and the drain electrode 16 is a metal layer including, for example, a titanium layer and an aluminum layer stacked in this order from the semiconductor layer 12. The gate electrode 18 is a metal layer including, for example, a nickel layer and a gold layer stacked in this order from the semiconductor layer 12. The source wiring 24, the drain wiring 26, the field plates 20a and 20b, and the connection wiring 22 are metal layers, for example, gold layers. The insulating film 28 is an inorganic insulating film such as a silicon nitride film. At least a part of the insulating film 28 may be an organic insulating film such as a polyimide film or a BCB (benzocyclobutene) film.
In this way, the FETs Q1 and Q2 are connected in parallel between the input terminal Tin and the output terminal Tout. The high frequency signal input to the input terminal Tin is amplified by the FETs Q1 and Q2, and the amplified high frequency signal is output from the output terminal Tout.
In the source-grounded FET of the first comparative example, when an output power increases, the number of FETs connected in parallel increases. When the output power is doubled for one FET, two FETs Q1 and Q2 are connected in parallel. Assuming that a voltage Vdd is applied to one FET, the drain bias voltages VD applied to the drains D1 and D2 of the FETs Q1 and Q2 are the same voltage Vdd. Assuming that a maximum current in the case of the one FET is Imax, the maximum current flowing through the output terminal Tout is 2×Imax, which is twice as large as the current flowing through the output terminal Tout. This results in a load impedance of ½ for the FETs Q1 and Q2. Thus, when the output power increases in the source-grounded FET, the number of parallel connections of the FETs Q1 and Q2 increases, and the load impedance of the FETs Q1 and Q2 reduces. Therefore, a difference between the load impedance of the FETs Q1 and Q2 and a load resistance (e.g., 50Ω) increases. If the load impedance and the load resistance are matched by impedance conversion, it becomes difficult to achieve a wide band.
As illustrated in
In a high-output FET, a field plate is used to increase a breakdown voltage. However, in an amplifier circuit in which the FETs Q1 and Q2 are cascode-connected, the appropriate structures of the field plates 20a and 20b of the FETs Q1 and Q2 are not known. Therefore, when the high frequency signal was input to the input terminal Tin, the changes with respect to time of the sources S1 and S2, the drains D1 and D2, and the gates G1 and G2 in the cascode-connected FETs Q1 and Q2 were simulated.
The simulation conditions are as follows.
The ground potential was set to 0 V, the source potentials of the sources S1 and S2 in the FETs Q1 and Q2 were set to Vs, the drain potentials of the drains D1 and D2 were set to Vd, and the gate potentials of the gates G1 and G2 were set to Vg.
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
When the amplitude of the potential difference Vd−Vg is large, the electric field concentration is likely to occur in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16. This may cause dielectric breakdown of the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16. When an input signal having a large amplitude is input, there is a possibility that the FET Q2 mainly causes the dielectric breakdown.
When the electric field in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 increases, a phenomenon called a memory effect is likely to occur. The memory effect is a drain idle current (Idq) drift or a drift phenomenon of a drain current called a current collapse phenomenon. The mechanism of the memory effect will be described. The high electric field increases the energy of electrons, and the electrons are captured by traps in the semiconductor layer 12. This reduces the drain current. Electrons captured in the trap are released with time. Therefore, when the electric field between the gate electrode 18 and the drain electrode 16 is reduced, the drain current recovers with time. In this way, the memory effect occurs. In the amplifier circuit 100, since the amplitude of the potential difference Vd-Vg of the FET Q2 is larger than that of the FET Q1, when the amplitude of the input signal changes, the memory effect occurs mainly in the FET Q2.
The following represents a change amount ΔIds of the drain current and a drain-source capacitance Cds, which indicate a magnitude of the memory effect with respect to a length L2 in the X direction of the bottom portion 21a of the field plates 20a and 20b in the GaN HEMT. The length L2 corresponds to the length L2a of the FET Q1 and the length L2b of the FET Q2.
The change amount ΔIds of the drain current in
Regarding the drain-source capacitance Cds of
As illustrated in
As the length L2 increases, the drain-source capacitance Cds increases. For example, the drain-source capacitance Cds is about 0.15 pF/mm when the length L2 is 0.3 μm, and the drain-source capacitance Cds is about 0.22 pF/mm when the length L2 is 1.4 μm. Thus, the drain-source capacitance Cds when the length L2 is 1.4 μm, is approximately 1.5 times as large as the drain-source capacitance Cds when the length L2 is 0.3 μm. The drain-source capacitance Cds changes substantially linearly with the length L2.
In order to increase a maximum oscillation frequency of the amplifier circuit, it is required to reduce a feedback capacitance Cfb.
As illustrated in
By increasing the length L2b corresponding to the length L2 of the FET Q2 in this manner, the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 of the FET Q2 can be suppressed, and the influence on an increase in the feedback capacitance Cfb can be reduced. However, when the length L2a of the FET Q1 increases, the drain-source capacitance of the FET Q1 increases. This causes deterioration of the high frequency characteristics such as narrowing of the band of the amplifier circuit 100. Therefore, the distance L1a (first distance) in the FET Q1 is made shorter than the distance L1b (second distance) in the FET Q2. That is, the length L2a (first length) of the FET Q1 is made shorter than the length L2b (second length) of the FET Q2. This makes it possible to reduce the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 in the FET Q2. Therefore, the drain breakdown voltage can be improved. In addition, the memory effect can be suppressed. Furthermore, the drain-source capacitance Cds of the FET Q1 can be reduced. This makes it possible to improve the high frequency characteristics such as widening the band of the amplifier circuit 100.
The lengths L2a and L2b are the lengths of the portions of the lower surfaces of the field plates 20a and 20b in the X direction, which are parallel to the upper surface of the semiconductor layer 12 (that is, the bottom portions 21a). The portion parallel (substantially parallel) to the upper surface of the semiconductor layer 12 allows variations due to manufacturing errors in the thickness of the insulating film formed between the bottom portion 21a and the semiconductor layer 12. For example, a distance between the lower surface of the bottom portion 21a and the upper surface of the semiconductor layer 12 may vary within a range of ±10%.
From the viewpoint of reducing the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 in the FET Q2, the length L2a may be set to 0.9 times or less, 0.8 times or less, or 0.5 times or less the length L2b. If the length L2a is too short, it is hard to suppress the electric field concentration between the gate electrode 18 and the drain electrode 16 in the FET Q1. From this viewpoint, the length L2a may be set to 0.1 times or more the length L2b.
Similarly, from the viewpoint of reducing the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 in the FET Q2, the distance L1a may be set to 0.9 times or less, 0.8 times or less, or 0.5 times or less the distance L1b. If the distance L1a is too short, it is hard to suppress the electric field concentration between the gate electrode 18 and the drain electrode 16 in the FET Q1. From this viewpoint, the distance L1a may be set to 0.1 times or more the distance L1b.
If the length L2a of the FET Q1 is too short, the effect of suppressing the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 reduces. From this viewpoint, the length L2a may be 0.1 μm or more, or 0.2 μm or more. If the length L2a is too long, the drain-source capacitance Cds increases. From this viewpoint, the length L2a may be 1.0 μm or less, or 0.5 μm or less. If the length L2b of the FET Q2 is too short, the effect of suppressing the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 reduces. From this viewpoint, the length L2b may be 0.5 μm or more, or 1.0 μm or more. If the length L2b is too long, the drain-source capacitance Cds increases. From this viewpoint, the length L2b may be set to 3.0 μm or less, or 2.0 μm or less.
When the gate-drain distance Lgd is taken as a reference, the length L2a may be 0.02 times or more, 0.04 times or more, 0.2 times or less, or 0.1 times or less the distance Lgd. The length L2b may be 0.1 times or more, 0.2 times or more, 1.0 times or less, or 0.5 times or less the distance Lgd.
The field plates 20a and 20b are at the same potential as the source electrode 14. This makes it possible to suppress the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 in the FET Q2. The same potential (or substantially the same potential) allows a potential difference due to the influence of the parasitic resistance, the parasitic inductance and the parasitic capacitor.
The gate width Wg of the FET Q1 is the same as the gate width Wg of the FET Q2. In this case, a potential difference Vg-Vd of the FET Q2 is larger than the potential difference Vg-Vd of the FET Q1. Therefore, by making the distance L1a shorter than the distance L1b, the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 in the FET Q2 can be suppressed. The term “gate width Wg is the same (substantially the same)” means that the potential difference Vg−Vd of the FET Q2 should be larger than the potential difference Vg−Vd of the FET Q1. For example, when the gate width Wg of the FET Q1 is Wg1 and the gate width Wg of the FET Q2 is Wg2, 2×|Wg1−Wg2|/(Wg1+Wg2) may be 0.1 or less.
When the gate width Wg of the FET Q1 and the gate width Wg of the FET Q2 are the same as each other, the gate bias voltage VG1 (first gate bias voltage) of the FET Q1 is equal to a value obtained by subtracting a half of the drain bias voltage VD from the gate bias voltage VG2 (second gate bias voltage) of the FET Q2. That is, VG1=VG2−VD/2 is satisfied. In this case, the potential difference Vg−Vd of the FET Q2 is larger than the potential difference Vg−Vd of the FET Q1. Therefore, by making the distance L1a shorter than the distance L1b, the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 in the FET Q2 can be suppressed. The term “VG1 is the same as (approximately same as) VG2−VD/2” means that the potential difference Vg−Vd of the FET Q2 should be larger than the potential difference Vg−Vd of the FET Q1. For example, VG1−(VG2−VD/2)<VD/25 is sufficient.
The structures of the FET Q1 and the FEF Q2 are the same as each other. For example, in addition to the gate widths Wg, the gate lengths Lg are the same as each other, the distances Lsg are the same as each other, and the distances Lgd are the same as each other. For example, when Lg, Lsg, and Lgd of the FET Q1 are Lg1, Lsg1, and Lgd1, respectively, and Lg, Lsg, and Lgd of the FET Q2 are Lg2, Lsg2, and Lgd2, respectively, 2×Lg1−Lg2/(Lg1+Lg2) may be 0.1 or less, 2×Lsg1−Lsg2/(Lsg1+Lsg2) may be 0.1 or less, and 2×Lgd1−Lgd2/(Lgd1+Lgd2) may be 0.1 or less. In this case, the potential difference Vg−Vd of the FET Q2 is larger than the potential difference Vg−Vd of the FET Q1. Therefore, by making the distance L1a shorter than the distance L1b, the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 can be suppressed. The FET Q1 and the FEF Q2 may have different structures from each other.
The FETs Q1 and Q2 are integrated on the same substrate 10, and the semiconductor layer 12 in the FETs Q1 and Q2 is the same. In this case, the potential difference Vg−Vd of the FET Q2 is larger than the potential difference Vg−Vd of the FET Q1. Therefore, by making the distance L1a shorter than the distance L1b, the electric field concentration in the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16 can be suppressed. The FET Q1 and the FEF Q2 may be provided on different substrates.
When the semiconductor layer 12 is a nitride semiconductor layer, the memory effect increases. Therefore, when the semiconductor layer 12 is the nitride semiconductor layer, the distance L1a is made shorter than the distance L1b, and the length L2a is made shorter than the length L2b. This makes it possible to suppress the memory effect in the FET Q2. The nitride semiconductor layer includes at least one layer of, for example, a gallium nitride layer, an aluminum gallium nitride layer, and an indium gallium nitride (InGaN) layer.
As illustrated in
The embodiments disclosed here should be considered illustrative in all respects and not restrictive. The present disclosure is not limited to the specific embodiments described above, but various variations and changes are possible within the scope of the gist of the present disclosure as described in the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-061667 | Apr 2023 | JP | national |
