Claims
- 1. A circuit for generating a digital data signal from an analog input data signal comprising:
a) master-slave flip-flop receiving said analog input data signal; b) an amplitude detecting circuit for detecting the amplitude of said analog input data signal and generating an amplitude detection signal in response thereto; and c) a phase shifting circuit responsive to said amplitude detection signal for supplying a phase shifted clock signal as a clock input to said master-slave flip-flop.
- 2. The circuit of claim 1, wherein said master-slave flip-flop is a D-type flip-flop.
- 3. The circuit of claim 1, wherein said analog input data signal includes a clock signal; and further comprising a clock recovery circuit receiving said analog input data signal and generating a recovered clock signal from said clock signal in said analog input data signal.
- 4. The circuit of claim 3, wherein said master-slave flip-flop comprises a pair of cascaded latch circuits actuated by said phase shift signal.
- 5. The circuit of claim 3, wherein said clock recovery circuit comprises:
a) a plurality of latch circuits for generating a plurality of sample signals from said analog data input signal; b) a phase detector logic circuit for generating a phase detected signal in response to said plurality of sample signals; c) a phase-locked-loop filter for generating a control signal in response to said phase detected signal; and d) a voltage controlled oscillator for supplying a clock signal to said plurality of latch circuits and said phase shifting circuit in response to said control signal.
- 6. The circuit of claim 3, wherein said analog input data signal has a maximum amplitude; and wherein said amplitude detecting circuit detects said maximum amplitude of said analog input data signal to generate said amplitude detection signal.
- 7. The circuit of claim 6, wherein said phase shift signal from said phase shifting circuit is input to said amplitude detecting circuit, said amplitude detecting circuit detecting said maximum amplitude in response thereto.
- 8. The circuit of claim 7, wherein said amplitude detecting circuit includes a sample and hold circuit for sampling said analog input data signal in response to said phase shifted clock signal and generating a sampled signal in response thereto.
- 9. The circuit of claim 8, wherein said amplitude detecting circuit includes a signal processing circuit for shaping said sampled signal.
- 10. The circuit of claim 9, wherein said signal processing circuit includes a squaring and integrating circuit for receiving said sampled signal and a low pass filter.
- 11. The circuit of claim 8, wherein said amplitude detecting circuit includes a fixed phase shift circuit for applying a fixed phase shift to said phase shifted clock signal and generating a fixed phase shift signal.
- 12. The circuit of claim 8, wherein said amplitude detecting circuit includes a frequency divider circuit for dividing said fixed phase shift signal by a predetermined amount and supplying a divided clock signal to said sample and hold circuit.
- 13. The circuit of claim 6, and further comprising:
a) a dithering circuit for generating a dither signal; b) an adder for adding said dither signal to said amplitude detection signal to generate a dithered amplitude detection signal; and c) a circuit for supplying said dithered amplitude detection signal to said phase shifting circuit.
- 14. The circuit of claim 13, wherein said dithering circuit generates said dither signal according to the formula
- 15. The circuit of claim 3, wherein said amplitude detecting circuit includes a sample and hold circuit for receiving said analog input data signal.
- 16. The circuit of claim 15, wherein said master-slave flip-flop includes a pair of cascaded latch circuits actuated by said clock signal from said phase shifting circuit.
- 17. The circuit of claim 15, wherein said clock recovery circuit comprises:
a) a plurality of latch circuits for generating a plurality of sample signals from said analog data input signal; b) a phase detector logic circuit for generating a phase detected signal in response to said plurality of sample signals; c) a phase-locked-loop filter for generating a control signal in response to said phase detected signal; and d) a voltage controlled oscillator for supplying a clock signal to said plurality of latch circuits and said phase shifting circuit in response to said control signal.
- 18. The circuit of claim 15, wherein said amplitude detecting circuit includes a plurality of said sample and hold circuits.
- 19. The circuit of claim 15, wherein said amplitude detecting circuit includes a frequency divider circuit for dividing said recovered clock signal by a predetermined amount and supplying a divided clock signal to said sample and hold circuit.
- 20. The circuit of claim 19, wherein said amplitude detecting circuit includes a squaring and integrating circuit coupled to said sample and hold circuit.
- 21. The circuit of claim 20, wherein said amplitude detecting circuit includes a signal processing circuit coupled to said squaring and integrating circuit for calculating said amplitude detection signal supplied to said phase shifting circuit.
- 22. The circuit of claim 21, wherein said amplitude detecting circuit includes at least a second squaring and integrating circuit.
- 23. The circuit of claim 22, wherein said amplitude detecting circuit includes at least a second sample and hold circuit; wherein each of said squaring and integrating circuits generates a respective output signal, said output signals having a largest value signal; and wherein said signal processing circuit compares said output signals from said squaring and integrating circuits to identify said largest value signal.
- 24. The circuit of claim 23, wherein said amplitude detecting circuit includes a plurality of phase shifting circuits coupled to said frequency divider circuit and each of said sampling and holding circuits.
- 25. The circuit of claim 21, wherein said amplitude detecting circuit includes a frequency multiplier circuit coupled to said frequency dividing circuit for multiplying said divided clock signals by a second predetermined amount to generate trigger signals.
- 26. The circuit of claim 25, wherein said amplitude detecting circuit includes a counter coupled to said frequency multiplier circuit for generating a count signal in response to said trigger signals.
- 27. The circuit of claim 26, wherein said amplitude detecting circuit includes at least a second sample and hold circuit, each responsive to said trigger signals and generating a plurality of sampled signals, and at least a second squaring and integrating circuit, each associated with a respective one of said sample and hold circuits; and further comprising a selector circuit coupled to said frequency multiplier circuit and said counter for selecting said sampled signals to be supplied to said squaring and integrating circuits.
- 28. A circuit for generating a digital data signal from an analog input data signal having a maximum vertical eye opening and an input clock signal, comprising:
a) a master-slave flip-flop receiving said analog input data signal; b) an amplitude detecting circuit for detecting said maximum vertical eye opening of said analog input data signal and generating a maximum vertical eye opening signal in response thereto; c) a clock recovery circuit for generating a recovered clock signal from said input clock signal; and d) a phase shifting circuit responsive to said maximum vertical eye opening signal and said recovered clock signal for supplying a phase shifted clock signal as a clock input to said master-slave flip-flop.
- 29. The circuit of claim 28, and wherein said phase shifted clock signal from said phase shifting circuit is input to said amplitude detecting circuit, said amplitude detecting circuit detecting said maximum vertical eye opening in response thereto.
- 30. The circuit of claim 29, wherein said amplitude detecting circuit includes a sample and hold circuit for generating a sampled signal from said analog input data signal.
- 31. The circuit of claim 30, wherein said amplitude detecting circuit includes a signal processing circuit for shaping said sampled signal.
- 32. The circuit of claim 31, wherein said signal processing circuit includes a squaring and integrating circuit and a low pass filter.
- 33. The circuit of claim 32, wherein said amplitude detecting circuit includes a fixed phase shift circuit for applying a fixed phase shift to said phase shifted clock signal to generate a fixed phase shifted clock signal.
- 34. The circuit of claim 33, wherein said amplitude detecting circuit includes a frequency divider circuit for dividing said fixed phase shift signal by a preset amount and supplying a divided clock signal to said sample and hold circuit.
- 35. The circuit of claim 28, wherein said amplitude detecting circuit includes a sample and hold circuit for receiving said analog input data signal.
- 36. The circuit of claim 35, wherein said amplitude detecting circuit includes a at least a second sample and hold circuit.
- 37. The circuit of claim 35, wherein said amplitude detecting circuit includes a frequency divider circuit for dividing said recovered clock signal by a preset amount and supplying a divided clock signal to said sample and hold circuit.
- 38. The circuit of claim 37, wherein said amplitude detecting circuit includes a squaring and integrating circuit coupled to said sample and hold circuit.
- 39. The circuit of claim 38, wherein said amplitude detecting circuit includes a signal processing circuit coupled to said squaring and integrating circuit for calculating said amplitude detection signal supplied to said phase shifting circuit.
- 40. The circuit of claim 39, wherein said amplitude detecting circuit includes at least a second sample and hold circuit and at least a second squaring and integrating circuit; wherein said squaring and integrating circuits generates a respective output signal, one of said respective output signals having a largest value signal; and wherein said signal processing circuit compares said output signals from said respective squaring and integrating circuits to identify said largest value signal.
- 41. The circuit of claim 40, wherein said amplitude detecting circuit includes at least a second phase shifting circuit coupled between said frequency divider circuit and a respective of sample and hold circuit.
- 42. The circuit of claim 39, wherein said amplitude detecting circuit includes a frequency multiplier circuit coupled to said frequency dividing circuit for multiplying said divided clock signal by a second preset amount to generate trigger signals.
- 43. The circuit of claim 42, wherein said amplitude detecting circuit includes a counter coupled to said frequency multiplier circuit for generating a count signal in response to said trigger signals.
- 44. The circuit of claim 43, wherein said amplitude detecting circuit includes a selector circuit connecting said counter with said signal processing circuit.
- 45. The circuit of claim 43, wherein said amplitude detecting circuit includes at least a second sample and hold circuit, each responsive to said trigger signals and generating a sampled signal, and at least a second squaring and integrating circuit, each associated with a respective one of said sample and hold circuits; and further comprising a selector circuit coupled to said frequency multiplier circuit and said counter for selecting said sampled signals to be supplied to said respective squaring and integrating circuits.
- 46. A circuit for generating a digital data signal from an analog input data signal carried on a high-speed communications network, said analog input data signal having a maximum vertical eye opening and a clock signal, comprising:
a) a D-type master-slave flip-flop for receiving said analog input data signal; b) an amplitude detecting circuit for detecting said maximum vertical eye opening of said analog input data signal and generating a maximum vertical eye opening signal in response thereto, said amplitude detecting circuit comprising:
i) a fixed phase shift circuit for generating a fixed phase shift signal; ii) a sample and hold circuit for sampling said analog input data signal and producing a sampled signal; iii) a squaring and integrating circuit for producing an output signal; and iv) a low pass filter for filtering said output signal to produce said maximum vertical eye opening signal; c) a phase shifting circuit responsive to said maximum vertical eye opening signal for supplying a phase shifted clock signal to said master-slave D-type flip-flop and said amplitude detecting circuit; d) a clock recovery circuit for generating a recovered clock signal from said clock signal contained in said analog input data signal, said clock recovery circuit comprising:
i) a plurality of latch circuits for generating a plurality of clock sample signals from said analog data input signal; ii) a phase detector logic circuit for generating a phase detected signal in response to said plurality of clock sample signals; iii) a phase-locked-loop filter for generating a control signal in response to said phase detected signal; and iv) a voltage controlled oscillator for actuating said plurality of latch circuits and said phase shifting circuit in response to said control signal; e) a dithering circuit for generating a dither signal; f) an adding circuit for adding said dither signal to said maximum vertical eye opening signal to generate a dithered maximum vertical eye opening signal; and g) a circuit for supplying said dithered maximum vertical eye opening signal to said phase shifting circuit.
- 47. A circuit for generating a digital data signal from an analog input data signal carried on a high-speed communications network, said analog input data signal having a maximum vertical eye opening and a clock signal, comprising:
a) a D-type master-slave flip-flop for receiving said analog input data signal; b) an amplitude detecting circuit for detecting said maximum vertical eye opening of said analog input data signal and generating a maximum vertical eye opening signal in response thereto, said amplitude detecting circuit comprising:
i) a sample and hold circuit for sampling said analog input data signal and outputting a sampled circuit in response to said analog input data; ii) a squaring and integrating circuit for outputting a squared and integrated signal response to said data; iii) a signal processing circuit for determining a maximum vertical eye opening value in response to said square and integrated signal; and iv) a frequency divider circuit outputting clock signal to said sample and hold circuit; c) a phase shifting circuit responsive to said maximum vertical eye opening signal for supplying a phase shift signal to said master-slave D-type flip-flop; and d) a clock recovery circuit for generating a recovered clock signal from said clock signal contained in said analog input data signal, said clock recovery circuit comprising:
i) a plurality of latch circuits for generating a plurality of clock sample signals from said analog data input signal; ii) a phase detector logic circuit for generating a phase detected signal in response to said plurality of clock sample signals; iii) a phase-locked-loop filter for generating a control signal in response to said phase detected signal; and iv) a voltage controlled oscillator for actuating said plurality of latch circuits and said phase shifting circuit in response to said control signal.
- 48. The circuit of claim 47, wherein said amplitude detecting circuit includes at least a second sample and hold circuit, and at least a second phase shifting circuit coupled to said frequency divider circuit and said plurality of said sample and hold circuits.
- 49. The circuit of claim 47, wherein said amplitude detecting circuit includes a frequency multiplier circuit coupled to said frequency dividing circuit for generating trigger signals, and a counter coupled to said frequency multiplier circuit for generating a count signal in response to said trigger signals.
- 50. The circuit of claim 49, wherein each of said sample and hold circuits, is responsive to said trigger signals and generating a plurality of sampled signals, and at least a second squaring and integrating circuit, each being associated with a respective one of said sample and hold circuits; and further comprising a selector circuit coupled to said frequency multiplier circuit and said counter for selecting said sampled signals to be supplied to said squaring and integrating circuits.
- 51. A method of generating a digital data signal from an analog input data signal carried on a high-speed communications network, comprising the steps of:
a) supplying said analog input data signal to a master-slave flip-flop; b) detecting the amplitude of said analog input data signal and generating an amplitude detection signal in response thereto; and c) supplying a phase shift signal as a clock signal to said master-slave flip-flop in response to said amplitude detection signal.
- 52. The method of claim 51, and further comprising the steps of:
a) generating a recovered clock signal from said analog input data signal; and b) supplying said recovered clock signal to said master-slave flip-flop.
- 53. The method of claim 51, and further comprising the steps of:
a) detecting th e maximum amplitude of said analog input data signal; and b) supplying said clock signal to said master-slave flip-flop in response to said detecting step.
- 54. The method of claim 53, and further comprising the step of supplying said phase shift signal to said amplitude detecting circuit in a feedback loop.
- 55. The method of claim 53, and further comprising the step of sampling said analog input data signal at predetermined intervals.
- 56. The method of claim 55, and wherein said step of sampling includes the step of sampling at predetermined equal intervals.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] Priority is claimed from provisional application Serial No. 60/288,374, filed May 3, 2001.
Provisional Applications (1)
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Number |
Date |
Country |
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60288374 |
May 2001 |
US |