Patent Application
20140159157
Antenna effect is a phenomenon that occurs during manufacturing of an integrated circuit. This phenomenon may occur when a substantial amount of electrical charge that is generated as a result of certain semiconductor manufacturing processes flows through a transistor structure into a semiconductor substrate, thereby causing gate oxide breakdown. The antenna effect therefore decreases yield and causes reliability issues for an integrated circuit.
Antenna diodes are often utilized to mitigate the antenna effect. Typically, an antenna diode is inserted into a region on an integrated circuit that is prone to antenna effect. Locations at which the antenna diodes are formed may be determined through an antenna violation check that is governed by antenna design rules. The antenna design rules may depend on the current state of the art process technology node.
The design and size of the antenna diode have remained relatively the same over a number of process generations. However, with newer process nodes, inserting antenna diodes on integrated circuit devices has become significantly more challenging. In order to include an antenna diode on an integrated circuit, substantial alterations (some or all of which may need to be performed manually) may need to be made to the layout of the integrated circuit. Compared to other functional circuitry, antenna diodes may also occupy a disproportionately large area on the integrated circuit.
It is within this context that the embodiments described herein arise.
Embodiments described herein include antenna diode circuitry and a method to manufacture the antenna diode circuitry. It should be appreciated that the embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or a method. Several embodiments are described below.
In one embodiment, an antenna diode circuitry structure that may overcome antenna effect in an integrated circuit is disclosed. The antenna diode may serve to discharge any accumulated charge (e.g., charge built up on the surface of a conductive trace) to ground. The antenna diode does not require additional area within the integrated circuit as it utilizes layout area adjacent to a dummy gate. Furthermore, the antenna diode may be readily formed on the integrated circuit layout as it does not require significant alterations to the layout.
In one embodiment, an integrated circuit with an antenna diode is described. The integrated circuit may include a substrate, a transistor, first and second diffusion regions, and a dummy gate. The transistor and the first and second diffusion regions may be formed in the substrate. The transistor has an associated gate structure disposed on the substrate. The dummy gate structure may be disposed on a region of the substrate such that the dummy gate structure separates the first diffusion region from the second diffusion region. The dummy gate structure may also be coupled to the transistor gate structure.
In an alternative embodiment, another integrated circuit with an antenna diode is described. The integrated circuit includes a substrate, a transistor, an antenna diode and a dummy gate structure. The transistor and the antenna diode are formed on the substrate. The dummy gate structure is formed in such that it extends over the antenna diode circuitry on the substrate.
In another embodiment, a method of forming an integrated circuit with an antenna diode is described. The method includes forming a dummy gate structure on a substrate. After forming the dummy gate structure, the method includes implanting dopants into the substrate to form a pair of diffusion regions in the substrate. The pair of diffusion regions may be formed immediately adjacent to the dummy gate structure.
In an alternative embodiment, another method to manufacture an integrated circuit having an antenna diode is described. The method includes forming a transistor gate structure and a plurality of dummy gate structures. The transistor gate structure and the plurality of dummy gate structures may be located close to each other. Furthermore, the plurality of dummy gate structures may be parallel to the transistor gate structure. The method further includes forming at least a first diffusion region pair immediately adjacent to the transistor gate structure and at least a second diffusion region pair immediately adjacent to a selected one of the dummy gate structures. Furthermore, the method includes forming a conductive path that couples the transistor gate structure and at least one of the diffusion regions of the second diffusion region pairs.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
The following embodiments describe antenna diode circuitry and a method to manufacture the antenna diode circuitry. It will be recognized, however, by one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.
Integrated circuit 10, in one instance, may be a programmable logic device (PLD) such as a field programmable gate array (FPGA) device. It should be appreciated that PLDs may be programmed or configured to include customized circuit designs. This provides advantages over fixed design integrated circuits (e.g., application specific integrated circuits (ASICs)). In one embodiment, a PLD (e.g., IC 10) may include programmable logic elements configured to perform any of a variety of functions. In one instance, the programmable logic elements may be configured as storage and processing circuitry 50.
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The circuits in storage and processing circuitry 50 may be formed by a plurality of transistors. Each transistor may include a gate electrode and source and drain diffusion regions. Storage and processing circuitry 50 may also include antenna diode circuitry 100, as shown in the embodiment of
It should be appreciated that antenna effects may occur during a wafer manufacturing process, especially during the manufacturing of metal pathways on metal layers. For example, electrostatic charge may be generated because of the relatively large friction on the metal pathways generated by the chemical mechanical polishing (CMP) process. If the accumulated charge is large enough, it may flow through the transistor into the substrate and damage gate oxide material that is formed underneath the gate of the transistor. The flow of chargethrough the transistor may also damage PN junctions (e.g., junctions at which P-type regions and N-type regions meet).
Accordingly, antenna diode circuitry 100 may serve as a safe discharge pathway for the electrostsatic charge. In one embodiment, antenna diode circuitry 100 may be placed near the gate of the transistor. Automated computer-aided design (CAD) tools may be used to design antenna diode circuitry 100 according to specific antenna design rules.
Antenna diode circuitry 100 may include dummy gate structure 120, a pair of diffusion regions 130 and interconnects 150. Dummy gate structure 120 may be an electrode formed over a substrate of an integrated circuit. In one embodiment, dummy gate structure 120 may not be coupled to any power source or circuits and may be at a floating voltage level. Dummy gate structure 120 may also be formed as part of the DFM requirements. Accordingly, dummy gate structure 120 may be composed of similar material as transistor gate structure 140. In one instance, the material may be polycrystalline silicon (polysilicon).
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In one embodiment, the size of each of diffusion regions 130 depends on the amount of charge that needs to be discharged. As described in
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Shallow trench isolation 310 may be placed between transistor structure 160 and antenna diode circuitry 100. In one embodiment, STI 310 may also be formed on perimeter of transistor structure 160 and antenna diode circuitry 100. STI 310 may provide isolation between active structures (e.g., transistor structure 160 and antenna diode circuitry 100).
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Referring still to the embodiment of
At step 420, a dummy gate structure is placed adjacent to the transistor structure. In one embodiment, the dummy gate structure may be similar to the top-view of dummy gate structure 120 in
At step 430, an antenna violation check is performed. It should be appreciated that antenna violation checks may be performed based on antenna rules that may be utilized to identify the probability of antenna effects. It should be appreciated that the antenna rules may take into account different factors. In one embodiment, the antenna rules may take into account the ratio between an area that includes the gate and an exposed area that includes the metal pathways. It should be appreciated that the antenna violation check may be performed by a CAD tool.
At step 440, it is determined whether there is an antenna violation through antenna violation checks. When there is no violation, method 400 ends. However, when there is an antenna violation based on the given antenna rules, method 400 moves on to step 450. At step 450, an antenna diode circuit may be created by placing a diffusion region adjacent to the layout of the dummy gate structure. Therefore, the diffusion region layout may be associated with the layout of the dummy gate structure. The diffusion region and the dummy gate structure may be similar to the top-view of diffusion regions 130 and dummy gate 120 of
Finally at step 460, the transistor gate structure is coupled to the diffusion region of the antenna diode circuitry. In one embodiment, the layout for the transistor gate structure is coupled to the diffusion region through a conductive pathway. The conductive pathway may include interconnects 150 and metal pathways 320 of
It should be appreciated that after step 460, the integrated circuit may include a transistor structure and an antenna diode circuitry. In one embodiment, the layout may be similar to that shown in the embodiment of
According to one embodiment, absence of interconnects 150 from one side of diffusion region 130 provides a greater flexibility for manufacturing metal pathways compared to layout structure 200 of
At step 710, a region on a P-type silicon substrate is identified. The antenna diode circuitry may be formed on that region. In one embodiment, the antenna diode circuitry may be similar to antenna diode circuitry 100 of
At step 720, an N-well is formed on the identified region. The N-well may be formed by a diffusion of N-type dopants. In one embodiment, the N-well is similar to N-well 360 of
Subsequently, at step 730, a dummy polysilicon is formed on the substrate over the N-well. In one embodiment, the dummy polysilicon may be similar to dummy gate structure 120 of
At step 740, P+ dopants are implanted into the substrate to form diffusion regions within the N-well. The implanted regions may be immediately adjacent to the dummy polysilicon. It should be appreciated that during the implantation process, the region on the substrate that is exposed to P+ dopants may include the dummy polysilicon region and regions adjacent to the dummy polysilicon. However, only the regions adjacent to the dummy polysilicon may be implanted with P+ dopants. In one embodiment, the resulting implanted regions may be similar to diffusion regions 130 in
At step 750, the diffusion region that is associated with the dummy polysilicon is coupled to the gate of a nearby transistor. In one embodiment, the diffusion region may be coupled to the gate through conductive pathways (e.g., metal pathways 320 and interconnects 150 of
The embodiments thus far have been described with respect to integrated circuits. The methods and apparatuses described herein may be incorporated into any suitable circuit. For example, they may be incorporated into numerous types of devices such as programmable logic devices, application specific standard products (ASSPs), and application specific integrated circuits (ASICs). Examples of programmable logic devices include programmable arrays logic (PALs), programmable logic arrays (PLAs), field programmable logic arrays (FPGAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), just to name a few.
The programmable logic device described in one or more embodiments herein may be part of a data processing system that includes one or more of the following components: a processor; memory; IO circuitry; and peripheral devices. The data processing can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable. The programmable logic device can be used to perform a variety of different logic functions. For example, the programmable logic device can be configured as a processor or controller that works in cooperation with a system processor. The programmable logic device may also be used as an arbiter for arbitrating access to a shared resource in the data processing system. In yet another example, the programmable logic device can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the programmable logic device may be one of the family of devices owned by ALTERA Corporation.
Although the methods of operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way.
Although the foregoing invention has been described in some detail for the purposes of clarity, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.
