The subject matter herein generally relates to an antenna module and a method for manufacturing the antenna module.
With the development of the 5th generation wireless systems, more components need to be integrated in the antenna module. This would result in an increase in a size of the antenna module at a time when devices for the wireless system are becoming smaller.
Therefore, there is room for improvement within the art.
Implementations of the present disclosure will now be described, by way of embodiments, with reference to the attached figures.
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale, and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure.
The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like.
In at least one embodiment, each antenna structure 48 may be sheet-like or circular. In another embodiment, a shape of each antenna structure 48 may be varied as needed. Specifically, each antenna structure 48 may be a patch antenna, a vibrator antenna, a slot antenna, an F-type antenna, a dipole antenna, or a Yagi antenna, to correspond to different frequency bands or different frequency band combinations.
In at least one embodiment, the inner circuit board 110 includes a first inner wiring layer 14, a first inner dielectric layer 15 covering the first inner wiring layer 14, a second inner wiring layer 18 on the first inner dielectric layer 15, a second inner dielectric layer 25 covering the second inner wiring layer 18, a third inner wiring layer 28 on the second inner dielectric layer 25, a third inner dielectric layer 35 covering the third inner wiring layer 28, and a fourth inner wiring layer 38 on the third inner dielectric layer 35. The first inner wiring layer 14 includes at least one inner pad 141. The inner pad 141 is buried in the first inner dielectric layer 15, and a surface of the inner pad 141 facing away from the second inner wiring layer 18 is exposed from the first inner dielectric layer 15. The first inner wiring layer 14 electrically connects to the second inner wiring layer 18 through at least one first inner conductive via 161. The second inner wiring layer 18 electrically connects to the third inner wiring layer 28 through at least one second inner conductive via 261. The third inner wiring layer 28 electrically connects to the fourth inner wiring layer 38 through at least one third inner conductive via 361.
In at least one embodiment, the first inner conductive via 161 is buried in the first inner dielectric layer 15, the second inner conductive via 261 is buried in the second inner dielectric layer 25, and the third inner conductive via 361 is buried in the third inner dielectric layer 35.
The second inner dielectric layer 25 fills in gaps of the second inner wiring layer 18 so as to be in contact with the first inner dielectric layer 15. The third inner dielectric layer 35 fills in gaps of the third inner wiring layer 28 so as to be in contact with the second inner dielectric layer 25.
The antenna structure 48 electrically connects to the fourth inner wiring layer 38 through at least one antenna connecting structure 461, and the chip 140 electrically connects to the first inner wiring layer 14, thereby achieving an electrical connection between the chip 140 and the antenna structure 48.
In at least one embodiment, the antenna circuit board 120 may further include an antenna dielectric layer 41 covering the fourth inner wiring layer 38 and filling in gaps of the fourth inner wiring layer 38 so as to be in contact with the third inner dielectric layer 35. The antenna connecting structure 461 is buried in the antenna dielectric layer 41.
In at least one embodiment, the antenna circuit board 120 may further include a second solder mask 72 on the antenna dielectric layer 41. At least one third opening 721 passing through the second solder mask 72 is defined. The antenna structure 48 is exposed from the third opening 721.
In at least one embodiment, the antenna circuit board 120 may further include a second antioxidant layer 74 on the antenna structure 48 to protect the antenna structure 48. The second antioxidant layer 74 may be a nickel-gold alloy layer formed by Electroless Nickel/Immersion Gold.
In at least one embodiment, the outer circuit board 130 includes an outer dielectric layer 42 covering the first inner dielectric layer 15, an outer wiring layer 58 on the outer dielectric layer 42, and a first solder mask 71 covering the outer dielectric layer 42. The outer wiring layer 58 includes at least one first soldering pad 581 to electrically connect to a circuit board (not shown). At least one second opening 711 is defined on the first solder mask 71 to expose the first soldering pad 581.
The outer dielectric layer 42 is in contact with the first inner dielectric layer 15.
The outer wiring layer 58 electrically connects to the first inner wiring layer 14 through at least one outer conductive via 561. The outer conductive via 561 is buried in the outer dielectric layer 42.
In at least one embodiment, the outer circuit board 130 may further include a first antioxidant layer 73 formed on the first soldering pad 581 to protect the first soldering pad 581. The first antioxidant layer 73 may be a nickel-gold alloy layer of paragraph [0033].
In at least one embodiment, each chip 140 includes at least one pin 1401 to electrically connect to the first inner wiring layer 14. In at least one embodiment, a size of each first soldering pad 581 is greater than a size of each inner pad 141 to ensure reliability of the outer wiring layer 58 when subsequently soldered to the circuit board.
In at least one embodiment, each of the first inner dielectric layer 15, the second inner dielectric layer 25, the third inner dielectric layer 35, the outer dielectric layer 42, and the antenna dielectric layer 41 has a dielectric constant Dk of less than 3 and a dielectric loss Df of less than 0.2, to ensure quality of high-frequency signal transmission.
At block 101, referring to
At block 102, referring to
In at least one embodiment, the protective film 40 may be a releasable film.
At block 103, referring to
At block 104, referring to
At block 105, referring to
In at least one embodiment, a thickness of each chip 140 is less than a thickness of the outer circuit board 130.
In at least one embodiment, the chip 140 includes at least one pin 1401 to connect to the inner pad 141.
At block 301, referring to
In at least one embodiment, the carrier sheet 10 includes a carrier 11 and a seed layer 12 deposited on a surface of the carrier 11. The seed layer 12 is made of a conductive material, such as metal.
In another embodiment, the seed layer 12 may be omitted. The carrier 11 can be a conductive plate.
At block 302, referring to
In at least one embodiment, the first wiring groove 131 may be defined by exposure and development.
In the illustrated embodiment, the first dry film 13 is formed on the seed layer 12 facing away from the carrier 11.
At block 303, referring to
In at least one embodiment, the first inner wiring layer 14 may be formed by electroplating.
At block 304, referring to
In at least one embodiment, the first inner wiring layer 14 is embedded in the first inner dielectric layer 15. The first inner dielectric layer 15 covers the first inner wiring layer 14 and fills in gaps of the first inner wiring layer 14.
At block 305, referring to
In at least one embodiment, the first inner conductive via 161 is formed by electroplating.
The first inner conductive via 161 is buried in the first inner dielectric layer 15.
At block 306, referring to
In at least one embodiment, at block 305, referring to
In at least one embodiment, the second inner conductive via 261 is buried in the second inner dielectric layer 25, and the third inner conductive via 361 is buried in the third inner dielectric layer 35.
The second inner dielectric layer 25 fills in gaps of the second inner wiring layer 18 so as to be in contact with the first inner dielectric layer 15. The third inner dielectric layer 35 fills in gaps of the third inner wiring layer 28 so as to be in contact with the second inner dielectric layer 25.
In at least one embodiment, the antenna circuit board 120 and the outer circuit board 130 may be formed by the following steps:
referring to
referring to
referring to
referring to
referring to
referring to
In at least one embodiment, a size of each first soldering pad 581 is greater than a size of each inner pad 141 to ensure reliability of the outer wiring layer 58 during subsequent soldering to the circuit board.
Depending on the embodiment, certain of the steps of methods described may be removed, others may be added, and the sequence of steps may be altered. It is also to be understood that the description and the claims drawn to a method may include some indication in reference to sequential steps. However, the indication used is only to be viewed for identification purposes and not as a suggestion as to an order for the steps.
In the method for manufacturing the antenna module 100, the chip 140 is embedded in the outer circuit board 130, thereby not only reducing the overall thickness of the antenna module 100, but also protecting the chip from collision with other elements.
It is to be understood, even though information and advantages of the present embodiments have been set forth in the foregoing description, together with details of the structures and functions of the present embodiments, the disclosure is illustrative only; changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the present embodiments to the full extent indicated by the plain meaning of the terms in which the appended claims are expressed.
Number | Date | Country | Kind |
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201910698354.0 | Jul 2019 | CN | national |
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20090061721 | Isa | Mar 2009 | A1 |
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20180053036 | Baek | Feb 2018 | A1 |
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Number | Date | Country | |
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20210036416 A1 | Feb 2021 | US |