SUMMARY DESCRIPTION OF THE DRAWINGS
FIG. 1A is a top-down view of a prior art back-illuminated imager with lateral anti-blooming drain structures;
FIG. 1B shows a cross-section of the back-illuminated CCD imager of FIG. 1A which depicts the structure of a single pixel;
FIG. 1C shows a simulated channel potential profile for the pixel of FIG. 2 with no charge collected;
FIG. 2 is cross-section of a front-illuminated imager in the prior art with anti-blooming structures moved away from the imaging-component upper-portions of a silicon substrate;
FIG. 3A is a cross section of an anti-blooming drain structure incorporated into a back-illuminated imager structure, constructed in accordance with an embodiment of the present invention;
FIG. 3B shows a simulated channel potential profile for a pixel constructed formed in the device of FIG. 3A with no charge collected;
FIG. 4 shows a top plan view of a frame transfer CCD array employing the anti-blooming drain structure of FIG 3 A;
FIG. 5 shows a cross-sectional view of a frame transfer CCD imager structure in the vicinity of the border between a charge-collecting region and the frame storage region;
FIG. 6 is a top plan view of a line transfer CCD array structure employing an anti-blooming drain structure, constructed in accordance with a second embodiment of the present invention;
FIG. 7A shows a top plan view of one of the pixels of the line transfer CCD array structure of FIG. 6; and
FIG. 7B is across-sectional view of the pixel structure of FIG. 7A.
DETAILED DESCRIPTION OF THE INVENTION
The following embodiments are intended as exemplary, and not limiting. In keeping with common practice, figures, are not necessarily drawn to scale.
A cross section of an anti-blooming drain structure incorporated into a back-illuminated imager structure (e.g. CCD or CMOS), constructed in accordance with an embodiment of the present invention is depicted in FIG. 3A, which is juxtaposed with a simulated bulk potential profile in FIG. 3B. As with the front-side CCD structure of FIG. 2, the back-illuminated imager structure 50 of the present invention is formed in a portion of a bulk semiconductor substrate 52, preferable made of but not limited to silicon. The semiconductor substrate 52 having a front side 54 and a back side 56 is doped to be of a first conductivity type (e.g., p-type). A drain region 58 of the second conductivity type (e.g., n+) can be formed by low energy ion implantation at least partially underlying a portion of the back side 56 of the silicon substrate 52. A barrier region 60 of the first conductivity type can be formed by an intermediate energy ion implantation at least partially underlying the drain region 58. A channel region 62 of a second conductivity type (e.g., n) is formed deep inside the bulk semiconductor substrate 52 substantially underlying the barrier region 60 via high energy ion implantation. The regions 58, 60, 62 can be formed by ion implantation in any order in the semiconductor substrate 52, so long as the proper implantation energy and net doping profile are attained. Although the doping profiles are described in terms of a p-type substrate and corresponding regions of a first or second conductivity type with electron carriers, a person skilled in the art would appreciate that the opposite type of carrier (holes) and similar regions of the appropriate net doping type can be formed using an n-type doped semiconductor substrate. One or more gates (not shown) can overlay the drain region 58. A drain contact (not shown) is electrically connected with at least a portion of the drain region 58. The drain contact can be biased at constant value for the removal of excess charge carriers to be described hereinbelow.
Light impinging on the back side 56 of the imager structure 50 creates charge carrier which migrate to the channel region 62. The charges are accumulate in the channel region 62 because the barrier region 60 initially provides an electrical barrier to the charges confined in the channel region 62. Initially, when there is no accumulated charge in the channel region 62, the channel potential 64 in FIG. 3B will be high. Barrier region potential 66 will be low, and drain region potentials 68 will be high. However, as more charges accumulate in the channel region 62, channel potential 64 collapses, and an instant in time is reached when the channel potential 64 is level with the barrier potential 66. From that point onwards, any further accumulated carriers will overcome the barrier potential, and move to the drain region 58. The excess charges in the drain region 58 is collected as a drain current through the drain contact.
FIG. 4 shows a top plan view of a frame transfer CCD array 69 employing the anti-blooming drain structure of the present invention. The frame transfer CCD array 69 comprises an array of pixels 70 forming a charge-collecting region 72, and an array of equal number of pixels 74 forming a frame storage region 76. The frame transfer CCD array 69 also includes a horizontal line transfer register 78, and output amplifier circuits 80. During an image integration period, photo generated carriers can be collected in each of the pixels 70 of the charge collecting region 72 via potentials applied to one or more overlying gates (not shown). At the end of the image integration period, charge packets collected in each of the pixels 70 of the entire pixel array of the collecting region 72 are transferred to corresponding pixels 74 of the frame storage region 76 via appropriate potentials applied to the or more gates. During the subsequent image integration period, the charges stored in each line 81 of the frame storage region 76 are collected in the horizontal line transfer register 78. Charge packets stored in the horizontal line transfer register 78 are then moved to the amplifier circuits 80. The amplifier circuits 80 convert each charge packet to a voltage signal which are then converted to a digital signal (not shown).
FIG. 5 shows a cross-sectional view of the frame transfer CCD imager structure 82 in the vicinity of the border between the charge-collecting region 72 and the frame storage region 76 of FIG. 4. The frame transfer CCD imager structure 82 employs the same anti-blooming structure described previously in FIG. 3 As with the CCD imager structure of FIG. 3, the frame transfer CCD imager structure 82 is formed in a portion of a bulk semiconductor substrate 84, preferable made of but not limited to silicon. The semiconductor substrate 84 having a front side 86 and a back side 88 is doped to be of a first conductivity type (e.g., p-type). A drain region 90 of the second conductivity type (e.g., n+) can be formed by low energy ion implantation extending into at least a portion of the front side 86 of the silicon substrate 84. A barrier region 92 of the first conductivity type can be formed by an intermediate energy ion implantation substantially underlying the drain region 90. A channel region 94 of a second conductivity type (e.g. n) is formed deep inside the bulk semiconductor substrate 84 substantially underlying the barrier region 92 via high energy ion implantation. A plurality of charge collecting gates 96 in the charge-collecting region 72 (see FIG. 4) of the frame transfer CCD imager structure 82 and a plurality of charge transfer gates 98 in the frame storage region 76 of the frame transfer CCD imager structure 82 can substantially overlay the drain region 90. A gate dielectric 100 substantially overlays the entire channel region 94 to electrically isolate the drain region 90 from the overlaying gates 96, 98. To allow for a continuous transfer of charge, successive gates overlap preceding gates. In FIG. 5, one of the plurality of charge transfer gates 98 is shown at least partially overlapping one of the plurality of charge collection gates 96. Overlapping gates 96, 98 are electrically separated from each other by an intervening inter gate dielectric 102.
One of the concerns in implementing such anti-blooming structures in back illuminated devices is the collection of charge in undesirable areas. Typically in any CCD imager architecture, a CCD imager comprises one or more charge-sensing regions where photo-generated charge carriers will be collected, and a charge transfer region where charge packets will be moved to output amplifier circuits. In the back-illuminated CCD imager devices, since light can fall on the entire back surface of the device, charge carriers can be generated anywhere in the bulk semiconductor substrate. However, these carriers should end up only in the charge collection region. Charges should be prevented from entering into charge transfer regions under transfer gates. Otherwise, photo generated carriers accumulating under the charge transfer gates will ultimately contribute heavy noise to the resulting image, which is referred to as the phenomenon called smear.
In the present invention as depicted in FIG. 5, charge carriers can be prevented from collecting under charge transfer gates 98 by forming an electrical barrier region 104 of the first conductivity type deep inside the bulk semiconductor substrate 84 by ion implantation substantially underlying the transfer gates 98. For the frame transfer CCD imager structure 82, the electrical barrier region can be formed substantially underlying the entire frame storage region 76 (see FIG. 4). In this way, charges coming from the back side 88 drift towards the charge-collecting region 72 underlying the collecting gates 96.
FIG. 6 shows a top plan view of a line transfer CCD array structure 106 employing an anti-blooming drain structure, constructed in accordance with a second embodiment of the present invention. The line transfer CCD array structure 106 comprises a charge-collecting region 108 and a charge transfer region 110 separate from the charge-collecting region 108 by a channel stop region 112. Like the frame transfer CCD array structure 82 of FIG, 4, the line transfer CCD array structure 106 includes a horizontal line transfer register 114, and output amplifier circuits 116. The vertical charge collection region 108 and the vertical charge transfer region 110 are constructed of a plurality of horizontally aligned pixels 118 comprising charge collection portions 120 and charge transfer portions 122 having one or more overlying charge transfer gates 124. During an image integration period, photo generated carriers can be collected in each of the charge collection portions 120 of the pixels 118. After the integration time period, the collected charges (or charge packet) are transferred to the charge transfer portions 122 of the pixels 118 under the transfer gates 124 by a clocking signal. Then charge packets can be moved to the horizontal line transfer register 114 and thence to the output amplifier circuits 116 by another sequential clocking signal. The amplifier circuits 116 convert each charge packet to a voltage signal which are then converted to a digital signal (not shown).
FIG. 7A shows a top plan view of one of the pixels 118, while FIG. 7B shows a cross-sectional view of the same pixel structure of FIG. 7A. The line transfer CCD array of FIGS. 7A and 7B employs an anti-blooming structure constructed in accordance with the second embodiment of the present invention. As with the CCD imager structure of FIGS. 3 and 5, the line transfer CCD imager structure 106 is formed in a portion of a bulk semiconductor substrate 126, preferable made of but not limited to silicon. The semiconductor substrate 126 having a front side 128 and aback side 130 is doped to be of a first conductivity type (e.g., p-type). Using photolithography, a drain region 132 of the second conductivity type (e.g., n+) can be formed by low energy ion implantation substantially extending into at least a portion of the front side 128 of the silicon substrate 126. A barrier region 134 of the first conductivity type can be formed by an intermediate energy ion implantation substantially underlying and about the drain region 132. A channel region 136 of a second conductivity type (e.g. n) is formed deep inside the bulk semiconductor substrate 126 substantially underlying and about the barrier region 134 via high energy ion implantation. A drain contact 138 at least partially overlays the drain region 132. A charge transfer gate 140 can be formed overlying the channel region 136 proximal to the drain barrier region 134. A gate dielectric 142 substantially underlies the charge transfer gate 140 to electrically isolate the latter from the underlying channel region 136. An inter-metal dielectric 144 substantially overlies the charge transfer gate 140, the drain region 132, and the barrier region 134, and at least partially underlies the drain contact 138. Unlike the frame transfer CCD structure of FIG. 5, there are a plurality of individual drain regions 132 and barrier regions 134, one for each of the plurality of pixels 118, while a single channel region 136 can extend throughout the entire vertical charge collection region 108 and the vertical frame storage region 110 underlying all of the pixels 118.
As with the frame transfer CCD imager structure 82 of FIGS. 4 and 5, for the line transfer CCD imager structure 106 of the present invention as depicted in FIG. 7B, charge carriers are prevented from collecting in tire vertical charge transfer region 110 by forming an electrical barrier region 146 of the first conductivity type (e.g., n+) deep inside the bulk semiconductor substrate 106 by ion implantation substantially underlying the transfer gates 140. For the line transfer CCD imager structure 106, the electrical barrier region 142 can be formed substantially underlying the entire vertical charge transfer region 110 (see FIG. 7B). In this way, charges coming from the back side 130 can drift towards the charge-collecting region 108.
It is to be understood that the exemplary embodiments are merely illustrative of the invention and that many variations of the above-described embodiments may be devised by one skilled in the art without departing from the scope of the invention. It is therefore intended that all such variations be included within the scope of the following claims and their equivalents.
Patent Application
20080079032
