Claims
- 1. An interposer for use in testing/stressing IC chips in a tester, each of said chips having a plurality of contacts on one face thereof, said contacts being arranged in a predetermined pattern, said tester having contact pads arranged in said predetermined pattern, said interposer comprising:
- a dielectric substrate,
- said substrate having a chip contacting face and a tester contacting face,
- a first set of raised releasable connectors on said chip contacting face arranged in said predetermined pattern, said first set of raised releasable connectors being configured to penetrate the contacts on said one face of said chip,
- a second set of raised releasable connectors on said tester contacting face arranged in said predetermined pattern, said second set of raised releasable connectors being configured to penetrate the contact pads on said tester,
- conducting vias connecting the corresponding connectors of said first and second sets of connectors, and
- said dielectric substrate including a member embedded in said dielectric substrate to control the coefficient of thermal expansion to about 6 ppm/.degree. C. or less.
- 2. The interposer as defined in claim 1, wherein said raised releasable connectors include dendrites.
RELATED APPLICATIONS
This application is a divisional of application Ser. No 08/789,926 filed on Jan. 28, 1997, now U.S. Pat. No. 5,949,246.
US Referenced Citations (19)
Foreign Referenced Citations (1)
Number |
Date |
Country |
RD-309064 |
Jan 1990 |
WOX |
Non-Patent Literature Citations (1)
Entry |
"Soft Probe for Direct Chip Cell Burn-in," Pape, et al., IBM Technical Disclosure Bulletin, vol. 35, No. 1B, Jun., 1992. |
Divisions (1)
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Number |
Date |
Country |
Parent |
789926 |
Jan 1997 |
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