Patent Application
20230316968
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0039295, filed on Mar. 30, 2022, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.
Embodiments of the present disclosure relate to an apparatus and a method for defect inspection of a display panel, and more particularly, relate to an apparatus and a method for inspecting a defect of a display panel, which affects an input sensor.
Various electronic devices, that are used in multi-media devices such as, for example, a television, a mobile phone, a tablet computer, a navigation system, and a game console, include a display device for displaying images. The display device includes a display panel as an output device and includes, for example, a keyboard, a mouse, or a remote controller as an input device. Also, the display device further includes an input sensor such as a touch panel, as an input device. The complex manufacturing processes used in producing the display panel may inevitably introduce defects to the display panel. These defects introduced to the display panel may affect the quality of the images displayed by the display panel and the performance of the input sensor disposed over the display panel. Thus, it is desirable to have an apparatus and/or a method capable of effectively detecting the defects of the display panel for defect inspection.
Embodiments of the present disclosure provide an apparatus and a method for defect inspection of a display panel capable of effectively detecting a defect of the display panel, which reduces the performance of an input sensor.
Embodiments of the present disclosure provide an apparatus and a method for defect inspection of a display panel capable of effectively detecting a defect of the display panel by determining a specific inspection frequency allowing a magnitude of a jitter of an input sensor to increase and setting the determined inspection frequency upon driving the input sensor to inspect and detect the defect of the display panel.
According to an embodiment of the present disclosure, an apparatus for inspecting a defect of a display panel includes the display panel that displays an image, an input sensor that is disposed on the display panel and senses an input applied from outside, a sensor driving part that drives the input sensor, and an inspection part that is connected with the sensor driving part, sets a frequency of the input sensor to an inspection frequency, and detects the defect of the display panel based on a change in a jitter occurring when the input sensor is driven at the inspection frequency. The inspection frequency includes a harmonic frequency of a driving frequency of the display panel.
The display panel may include a base layer, a circuit element layer disposed on the base layer, a display element layer disposed on the circuit element layer, and an encapsulation layer disposed on the display element layer. The display element layer may include a first electrode, a second electrode disposed on the first electrode, and a light-emitting layer disposed between the first electrode and the second electrode.
The inspection part may detect a deposition defect of the second electrode.
The inspection part may include a frequency setting part that sets the frequency of the input sensor to the inspection frequency, and a defect detection part that determines the defect of the display panel when a level of the jitter is higher than a reference level.
The input sensor may include a plurality of sensing electrodes, and the plurality of sensing electrodes may include a plurality of transmit electrodes and a plurality of receive electrodes crossing each other.
The defect detection part may extract specific sensing electrodes, at which the level of the jitter is higher than the reference level, from among the plurality of sensing electrodes, and may determine specific portions of the display panel, which overlap the specific sensing electrodes thus extracted, as the defect.
The inspection part may further include a frequency selection part that selects a frequency, which allows a magnitude of the change in the jitter of the input sensor to increase, as the inspection frequency and stores the selected frequency in the sensor driving part.
The frequency selection part may select a value obtained by multiplying a number of scan lines of the display panel and a refresh rate of a screen together as the inspection frequency.
The frequency selection part may drive the input sensor at a plurality of frequencies of a given range, with the display panel driven, and may select frequencies, at which a change magnitude in the level of the jitter is equal to or greater than a specific reference, as the inspection frequency.
The frequency selection part may calculate the inspection frequency from the driving frequency of the display panel through fast Fourier transform, with the display panel driven and the input sensor not driven.
The inspection part may monitor the change in the jitter while increasing a number of frames to be driven in the input sensor.
According to an embodiment of the present disclosure, a method for inspecting a defect of a display panel includes driving the display panel, setting an inspection frequency of an input sensor disposed on the display panel, driving the input sensor at the inspection frequency, and inspecting the defect of the display panel based on a change in a jitter occurring when the input sensor is driven. The inspection frequency includes a harmonic frequency of a driving frequency of the display panel.
The inspecting of the defect of the display panel may include detecting a deposition defect of a power electrode disposed between a light-emitting layer and an encapsulation layer included in the display panel.
The inspecting of the defect of the display panel may include determining the defect of the display panel when a level of the jitter is higher than a reference level.
The input sensor may include a plurality of sensing electrodes, and the plurality of sensing electrodes may include a plurality of transmit electrodes and a plurality of receive electrodes crossing each other.
The determining of the defect may include extracting specific sensing electrodes, at which the level of the jitter is higher than the reference level, from among the plurality of sensing electrodes, and determining specific portions of the display panel, which overlap the specific sensing electrodes thus extracted, as the defect.
The method may further include selecting a frequency, which allows a magnitude of the change in the jitter of the input sensor to increase, as the inspection frequency, so as to be stored in a memory.
The selecting of the inspection frequency may include selecting a value obtained by multiplying a number of scan lines of the display panel and a refresh rate of a screen as the inspection frequency.
The selecting of the inspection frequency may include driving the input sensor at a plurality of frequencies of a given range, with the display panel driven, and selecting frequencies, at which a change magnitude of the level of the jitter is equal to or greater than a specific reference, from among the plurality of frequencies as the inspection frequency.
The inspecting of the defect of the display panel may include monitoring the change in the jitter while increasing a number of frames to be driven in the input sensor.
The above and other aspects and features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which:
Since the drawings in
In the specification, the expression that a first component (or area, layer, part, portion, etc.) is “on”, “connected with”, or “coupled to” a second component means that the first component is directly on, directly connected with, or directly coupled to the second component or means that a third component is disposed therebetween.
Like reference numerals refer to like components. The expression “and/or” includes any and all combinations which associated components are capable of defining.
Although the terms “first”, “second”, etc. may be used to describe various components, the components should not be construed as being limited by the terms. The terms are only used to distinguish one component from another component. For example, without departing from the scope and spirit of the present disclosure, a first component may be referred to as a “second component”, and similarly, the second component may be referred to as the “first component”. The singular forms are intended to include the plural forms unless the context clearly indicates otherwise.
“About” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.
The terms “under”, “below”, “on”, “above”, etc. are used to describe the correlation of components illustrated in drawings. The terms that are relative in concept are described based on a direction shown in drawings, and it will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation illustrated in the drawings.
It will be further understood that the terms “comprise”, “include”, “have”, etc. specify the presence of stated features, numbers, steps, operations, elements, components, or a combination thereof but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or a combination thereof.
Unless otherwise defined, all terms (including technical terms and scientific terms) used in the specification have the same meaning as commonly understood by one skilled in the art to which the present disclosure belongs. Furthermore, terms such as terms defined in the dictionaries commonly used should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present specification.
Below, embodiments of the present disclosure will be described with reference to accompanying drawings.
Referring to
The display device DD is in the shape of a rectangle having a long edge (or side) in a first direction DR1 and a short edge (or side) in a second direction DR2 intersecting the first direction DR1. A corner where the short side in second direction DR2 and the long side in the first direction DR1 meet may be formed to have a round shape with a predetermined curvature or have a right-angled shape. However, the shape of the display device DD is not limited thereto. For example, the display device DD may be implemented in various shapes such as, for example, a circular shape, an oval shape, an atypical shape, or another polygonal shape such as, for example, a triangle, a pentagon or a hexagon. The display device DD may display an image IM on a display surface IS parallel to each of the first direction DR1 and the second direction DR2, so as to face a third direction DR3. For example, the display device DD may display the image IM towards the third direction DR3. The display surface IS on which the image IM is displayed may correspond to a front surface of the display device DD. The image IM includes not only a moving image, but also a still image.
In this embodiment, a front surface (or an upper/top surface) and a rear surface (or a lower/bottom surface) of each member are defined with respect to a direction in which the image IM is displayed. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. While the display device DD having a flat shape is illustrated in
A separation distance between the front surface and the rear surface in the third direction DR3 may correspond to a thickness of the display device DD in the third direction DR3. Meanwhile, directions that the first, second, and third directions DR1, DR2, and DR3 indicate may be relative in concept and may be changed to different directions.
The display device DD may sense an external input applied from the outside. The external input may include various types of inputs that are provided from the outside of the display device DD. The display device DD according to an embodiment of the present disclosure may sense an external input TC of a user US, which is applied from the outside. The external input TC of the user US may be one of various types of external inputs, such as, for example, a part of the user's body, light, heat, and pressure, or a combination thereof. In addition, the display device DD may detect inputs that contact and also are close to or adjacent to the display device DD. In this embodiment, an example in which the external input TC of the user US is a touch input by a hand of the user US is described, but the present disclosure is not limited thereto. For example, as described above, the external input TC of the user US may be provided in various types. Also, the display device DD may sense the external input TC of the user US applied to a side surface or a rear surface of the display device DD depending on a structure of the display device DD and is not limited to one embodiment.
The display device DD according to an embodiment of the present disclosure may sense a second input that is applied from the outside. The second input may include inputs by an input device (e.g., a stylus pen, an active pen, a touch pen, an electronic pen, an e-pen, or the like) in addition to the hand of the user US.
The front surface of the display device DD may be divided into a transmission area TA and a bezel area BZA. The transmission area TA may be an area in which the image IM is displayed. The transmission area TA may be an optically transparent area. For example, the transmission area TA may exhibit a light transmittance of about 90% or greater in a visible light area. The user US visually perceives the image IM through the transmission area TA. In this embodiment, the transmission area TA is illustrated in the shape of a quadrangle whose vertexes are rounded. However, this is illustrated as an example. The transmission area TA may have various shapes and may not be limited to any one embodiment.
The bezel area BZA is adjacent to the transmission area TA. The bezel area BZA may be an area having a relatively low light transmittance compared to the transmission area TA, and may include an opaque material that blocks a light. The bezel area BZA may have a given color. The bezel area BZA may surround the transmission area TA. As such, a shape of the transmission area TA may be defined substantially by the bezel area BZA. For example, the bezel area BZA may be located outside the transmission area TA. However, this is illustrated as an example. The bezel area BZA may be disposed adjacent to only one side of the transmission area TA or may be omitted. The display device DD according to an embodiment of the present disclosure may include various embodiments and is not limited to any one embodiment.
As illustrated in
The display panel DP according to an embodiment of the present disclosure may be a light-emitting display panel. The display panel DP may be, for example, an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. An emission layer of the organic light-emitting display panel may include an organic light-emitting material. An emission layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. An emission layer of the quantum dot light-emitting display panel may include a quantum dot, a quantum rod, etc. The quantum dot and the quantum rod may be small semiconductor particles which are several nanometers in size. The inorganic light-emitting material may include crystalline semiconductors such as, for example, gallium nitride, indium phosphide, etc. Alternatively, the display panel DP according to an embodiment of the present disclosure may include an organic material and a quantum dot, or may include an inorganic material and a quantum dot. Below, the description will be given under the condition that the display panel DP is an organic light-emitting display panel in an embodiment of the present disclosure.
The display panel DP may output the image IM, and the output image IM may be displayed on the display surface IS. For example, the image IM may be displayed on the transmission area TA of the display surface IS. The input sensor ISP may be disposed on the display panel DP to sense the external input TC and the second input. A configuration and an operation of the input sensor ISP will be described with reference to
The window WM may be formed of a transparent material capable of outputting the image IM. For example, the window WM may be formed of glass, sapphire, plastic, or the like. An example in which the window WM is implemented with a single layer is illustrated, but the present disclosure is not limited thereto. For example, the window WM may include a plurality of layers. For example, the window WM may have a laminated structure of a plurality of plastic films bonded with an adhesive, or may have a laminated structure of a glass substrate and a plastic film bonded with an adhesive. In the case of a flexible display device, a plastic film that has excellent ductility may be used to form the window WM.
The bezel area BZA of the display device DD described above may correspond to an area that is defined by printing a material including a given color on one area of the window WM. In an embodiment of the present disclosure, the window WM may include a light blocking pattern for defining the bezel area BZA. The light blocking pattern that is a colored organic film may be formed, for example, in a coating manner. For example, when the window WM is provided as a glass or plastic substrate, the bezel area BZA may be a color layer printed or deposited on one side of a glass or plastic substrate. For example, the bezel area BZA may be formed by coloring the corresponding area of the glass or plastic substrate.
The window WM may be coupled to the display module DM by an adhesive film. In an embodiment of the present disclosure, the adhesive film may include an optically clear adhesive (OCA) film. The optically clear adhesive OCA film may be formed from a pre-coated film or from a liquid paste. In general, the optically clear adhesive OCA may require optical clarity and may provide shock resistance. However, the adhesive film is not limited thereto. For example, the adhesive film may include a typical adhesive or sticking agent. For example, the adhesive film may include an optically clear resin (OCR) film or a pressure sensitive adhesive (PSA) film.
An anti-reflection layer may be further disposed between the window WM and the display module DM. The anti-reflection layer decreases reflectivity of an external light incident from above the window WM. The anti-reflection layer according to an embodiment of the present disclosure may include a retarder and a polarizer. The retarder may have a film type or a liquid crystal coating type and may include a 212 retarder and/or a 214 retarder. In an embodiment of the present disclosure, the anti-reflection layer may include two layers of retarder with a first retarder having a λ/2 retardation value, and a second retarder positioned below the first retarder and having a λ/4 retardation value. The polarizer may also have a film type or a liquid crystal coating type. The film type may include a stretch-type synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a given direction. The film-type polarizer may be a uniaxially stretched film or a biaxially stretched film. The retarder and the polarizer may be implemented with one polarization film.
The display module DM may display an image depending on an electrical signal and may transmit/receive information about an external input. The display module DM may be defined by an active area AA and a non-active area NAA. The active area AA may be defined as an area through which an image IM provided from the display module DM is output. For example, the image IM may be provided from the display panel DP of the display module DM. Also, the active area AA may be defined as an area in which the input sensor ISP senses the external input TC and the second input applied from the outside.
The non-active area NAA is adjacent to the active area AA. For example, the non-active area NAA may surround the active area AA. The non-active area NAA may be covered by the bezel area BZA and not be visible from the outside. However, this is illustrated as an example. The non-active area NAA may be defined in various shapes, not limited to any one embodiment. According to an embodiment of the present disclosure, the active area AA of the display module DM may correspond to at least a portion of the transmission area TA.
The display module DM may include a main circuit board MCB, a flexible circuit film FCB, and a driver chip DIC. The main circuit board MCB may be connected with the flexible circuit film FCB so as to be electrically connected with the display panel DP. The flexible circuit film FCB may be connected with the display panel DP such that the display panel DP and the main circuit board MCB are electrically connected. Meanwhile, in an embodiment of the present disclosure, the flexible circuit film FCB may be omitted, and the main circuit board MCB may be directly connected to the display panel DP at this time.
The main circuit board MCB may include a plurality of driver devices, or connectors for power supply. The plurality of driver devices may include a circuit part for driving the display panel DP. The plurality of driver devices may include a main driving part MCP (refer to
The input sensor ISP may be electrically connected with the main circuit board MCB through the flexible circuit film FCB. For example, the flexible circuit film FCB may be connected to pads of the input sensor ISP disposed in the non-active area NAA, and may electrically connect the main circuit board MCB and the input sensor ISP. However, the present disclosure is not limited thereto. For example, the display module DM may further include a separate flexible circuit film for electrically connecting the input sensor ISP and the main circuit board MCB.
The display device DD further includes an outer case OC accommodating the display module DM. The outer case OC may be coupled with the window WM to define the exterior of the display device DD. For example, the window WM and the outer case OC may be combined to define the appearance of the display device DD. The display module DM, the flexible circuit film FCB and the main circuit board MCB may be enclosed by the window WM and the outer case OC. In an embodiment of the present disclosure, the window WM may couple with the outer case OC to fix in place the display module DM, the flexible circuit film FCB and the main circuit board MCB. The outer case OC may absorb external shocks and may prevent a foreign material/moisture or the like from being infiltrated into the display module DM such that components accommodated in the outer case OC are protected. Meanwhile, in an embodiment of the present disclosure, the outer case OC may be provided in the form of a combination of a plurality of accommodating members.
The display device DD according to an embodiment of the present disclosure may further include an electronic module including various functional modules for operating the display module DM, a power supply module for supplying a power necessary for overall operations of the display device DD, a bracket coupled with the display module DM and/or the outer case OC to partition an inner space of the display device DD, etc.
Referring to
The base layer BL may include at least one plastic film. The base layer BL may include, for example, a plastic substrate, a glass substrate, a metal substrate, or an organic/inorganic composite substrate. In an embodiment of the present disclosure, the base layer BL may be a flexible substrate. For example, when the base layer BL is a flexible substrate, the base layer may include a polymer resin, and may be foldable, rollable, and/or bendable. The active area AA and the non-active area NAA described with reference to
The circuit element layer DP-CL includes at least one intermediate insulating layer and a circuit element. The intermediate insulating layer includes at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit element includes signal lines, a driving circuit of a pixel, etc. The driving circuit of the pixel may include a transistor.
The display element layer DP-OLED includes a light-emitting element. The light-emitting element may include at least one organic light-emitting diode OLED. The display element layer DP-OLED may further include an organic film such as a pixel defining film.
The encapsulation layer TFE seals the display element layer DP-OLED. The encapsulation layer TFE includes at least one inorganic layer. The encapsulation layer TFE may further include at least one organic layer. The inorganic layer protects the display element layer DP-OLED from moisture/oxygen, and the organic layer protects the display element layer DP-OLED from a foreign material such as a dust particle. The inorganic layer may include, for example, a silicon nitride (Si3N4) layer, a silicon oxynitride (SiON) layer, a silicon oxide (SiO2) layer, a titanium oxide (TiO2) layer, or an aluminum oxide (Al2O3) layer. The organic layer may include a polymer-based material. Examples of the polymer-based material may include, for example, an acrylic resin, an epoxy resin, polyimide, and/or polyethylene. In an embodiment of the present disclosure, the organic layer may include an acrylic-based organic layer.
The input sensor ISP may be formed on the display panel DP by a continuous process. Also, the input sensor ISP and the display panel DP may be coupled to each other by an adhesive film. The input sensor ISP may have a multi-layer structure. The input sensor ISP may include a single insulating layer or multiple insulating layers. According to an embodiment of the present disclosure, when the input sensor ISP is directly disposed on the display panel DP by a continuous process, the input sensor ISP is directly disposed on the encapsulation layer TFE, and an adhesive film is not disposed between the input sensor ISP and the display panel DP. However, in an embodiment of the present disclosure, an adhesive film may be disposed between the input sensor ISP and the display panel DP. In this case, the input sensor ISP is not manufactured by a process continuous to that of the display panel DP. That is, the input sensor ISP may be manufactured through a process separate from that of the display panel DP and may then be fixed on an upper surface of the display panel DP by an adhesive film.
In an embodiment of the present disclosure, the display panel DP may further include an encapsulation substrate. The encapsulation substrate may be disposed on the display element layer DP-OLED so as to face the base layer BL. The encapsulation substrate may include, for example, a plastic substrate, a glass substrate, a metal substrate, or an organic/inorganic composite material substrate. According to an embodiment of the present disclosure, the encapsulation substrate may include, for example, glass, and the glass may be ultra-thin glass (UTG). A sealant may be disposed between the encapsulation substrate and the base layer BL, and the encapsulation substrate and the base layer BL may be coupled to each other by the sealant. The sealant may include an organic adhesive or a frit being a ceramic adhesive material. The display element layer DP-OLED may be sealed by the sealant and the encapsulation substrate.
When the input sensor ISP is directly disposed on the display panel DP by a continuous process, the input sensor ISP may be directly disposed on the encapsulation substrate. However, in an embodiment of the present disclosure, when an adhesive film is disposed between the input sensor ISP and the display panel DP, the input sensor ISP may be fixed on the upper surface of the encapsulation substrate by the adhesive film.
Referring to
The buffer layer BFL may enhance a bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may be configured to reduce or block penetration of foreign materials, moisture, or ambient air from a bottom portion of the base layer BL and may provide a flat surface on the base layer BL. The buffer layer BFL may include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). For example, the buffer layer BFL may include a structure in which a silicon oxide (SiO2) layer and a silicon nitride (Si3N4) layer are stacked alternately.
The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon (p-Si). However, the present disclosure is not limited thereto, and the semiconductor pattern may include, for example, amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), or oxide semiconductor.
The conductivity of the first area may be higher than the conductivity of the second area, and the first area may substantially serve as an electrode or a signal line. The second area may correspond to an active (or channel) of a transistor substantially. In other words, a portion of the semiconductor pattern may be an active of a transistor, another portion thereof may be a source or a drain of the transistor, and the other portion thereof may be a connection electrode or a connection signal line.
Each of pixels may be expressed by an equivalent circuit including 7 transistors, one capacitor, and a light-emitting element ED, and the equivalent circuit of the pixel may be modified in various forms. In an embodiment of the present disclosure, for driving the light-emitting element ED, the light-emitting element ED may be connected to a pixel circuit which includes two or more transistors and one or more capacitors. One transistor 100PC and one light-emitting element ED included in a pixel are illustrated in
A source SC, an active AL, and a drain DR of the transistor 100PC may be formed from the semiconductor pattern. The source SC and the drain DR may extend from the active AL in directions facing away from each other in a cross-sectional view, and may be arranged respectively on opposite sides of the active AL (i.e., the channel region). A portion of a connection signal line SCL forming from the semiconductor pattern is illustrated in
A first insulating layer 10 may be disposed on the buffer layer BFL, may overlap a plurality of pixels in common, and may cover the semiconductor pattern. The first insulating layer 10 may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of, for example, aluminum oxide (Al2O3), titanium oxide (TiO2), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), zirconium oxide (ZrO2), or hafnium oxide (HfO2) In an embodiment of the present disclosure, the first insulating layer 10 may be a single silicon oxide (SiO2) layer. An insulating layer of the circuit element layer DP-CL to be described later as well as the first insulating layer 10 may be an inorganic layer and/or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the materials described above but is not limited thereto.
A gate GT of the transistor 100PC is disposed on the first insulating layer 10. The gate GT may be a part of a metal pattern. The gate GT overlaps the active AL. The gate GT may function as a mask in the process of doping the semiconductor pattern. For example, the source SC and the drain DR of the transistor 100PC may be formed by doping the semiconductor pattern with an N-type dopant or a P-type dopant using the gate GT as a mask in the doping process.
A second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate GT. The second insulating layer 20 may overlap the pixels in common. The second insulating layer 20 may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. The second insulating layer 20 may include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). In this embodiment, the second insulating layer 20 may have a multi-layer structure including a silicon oxide (SiO2) layer and a silicon nitride (Si3N4) layer.
A third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may have a single-layer or multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide (SiO2) layer and a silicon nitride (Si3N4) layer.
A first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 penetrating the first, second, and third insulating layers 10, 20, and 30.
A fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single silicon oxide (SiO2) layer. A fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.
A second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected with the first connection electrode CNE1 through a contact hole CNT-2 penetrating the fourth insulating layer 40 and the fifth insulating layer 50.
A sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover the second connection electrode CNE2. The sixth insulating layer 60 may be an organic layer.
The display element layer DP-OLED may be disposed on the circuit element layer DP-CL, and may include the light-emitting element ED. For example, the display element layer DP-OLED may include, for example, an organic light emitting material, a quantum dot, a quantum rod, a micro-LED, or a nano-LED. Below, the description will be given under the condition that the light-emitting element ED is an organic light-emitting element. For example, the light-emitting element ED may include at least one organic light-emitting diode OLED, but the present disclosure is not limited thereto.
The light-emitting element ED may include a first electrode AE, an emission layer EL, and a second electrode CE. The first electrode AE may also be referred to as a pixel electrode or an anode electrode, and the second electrode CE may also be referred to as a common electrode or a cathode electrode.
The first electrode AE may be disposed on the sixth insulating layer 60. The first electrode AE may be connected with the second connection electrode CNE2 through a contact hole CNT-3 penetrating the sixth insulating layer 60.
A pixel defining layer 70 may be disposed on the sixth insulating layer 60 and may cover a portion of the first electrode AE. An opening 70-OP is defined in the pixel defining layer 70. The opening 70-OP of the pixel defining layer 70 exposes at least a portion of the first electrode AE. In an embodiment of the present disclosure, the pixel defining layer 70 may include an organic material such as, for example, polyimide, but the present disclosure is not limited thereto.
The active area AA (refer to
A light-emitting layer EL may be disposed on the first electrode AE. The light-emitting layer EL may be disposed in an area defined by the opening 70-OP. That is, the light-emitting layer EL may be independently disposed for each pixel. The light emitting layer EL may emit light in response to a potential difference between the first electrode AE and the second electrode CE. For example, when an anode voltage is applied to the first electrode AE and a cathode voltage is applied to the second electrode CE, the holes and electrons move to the light-emitting layer EL, such that they combine in the light-emitting layer EL to emit light. In the case where the light-emitting layer EL is independently disposed for each pixel, each of the light-emitting layers EL may emit a light of at least one of a blue color, a red color, or a green color. However, the present disclosure is not limited thereto. For example, the light-emitting layer EL may be provided to be connected in common with the pixels. In this case, the light-emitting layer EL may provide a blue color or may provide a white color. In an embodiment of the present disclosure, the light-emitting layer EL may include at least one of materials emitting red, green, blue, or white light, and may include a fluorescent material or a phosphorescent material.
The second electrode CE may be disposed on the light-emitting layer EL, and may be integrally disposed in a plurality of pixels in common. In an embodiment of the present disclosure, the second electrode CE may include a transparent conductive material or a semi-transparent conductive material. Accordingly, light generated in the light-emitting layer EL may be easily emitted toward the third direction DR3 through the second electrode CE.
A hole control layer may be interposed between the first electrode AE and the light emitting layer EL. The hole control layer may be disposed in common in the emission region PXA and the non-emission region NPXA. The hole control layer may include a hole transport layer and may further include a hole injection layer. An electron control layer may be disposed between the light-emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer. The hole control layer and the electron control layer may be formed in common at a plurality of pixels by using an open mask. Thus, the light-emitting layer EL may generate a color light corresponding to each of the pixels, and may be interposed between the hole transport layer and the electron transport layer.
The encapsulation layer TFE may be disposed on the display element layer DP-OLED. The encapsulation layer TFE may cover the display element layer DP-OLED to prevent the display element layer DP-OLED from being damaged or degraded by external impurities. The encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer sequentially stacked, and layers constituting the encapsulation layer TFE are not limited thereto.
The inorganic layer protects the display element layer DP-OLED from moisture/oxygen, and the organic layer protects the display element layer DP-OLED from a foreign material such as a dust particle. The inorganic layers may include, for example, a silicon nitride (Si3N4) layer, a silicon oxynitride (SiON) layer, a silicon oxide (SiO2) layer, a titanium oxide (TiO2) layer, an aluminum oxide (Al2O3) layer, or the like. The organic layer may include an acrylic-based organic layer but is not limited thereto. In an embodiment of the present disclosure, the two inorganic layers may be deposited to directly contact each other in an edge area of the display device DD, and thus the two inorganic layers may seal the organic layer such that the organic layer is not exposed to the outside. Accordingly, external moisture or oxygen may be prevented or reduced from being infiltrated into the display area through the organic layer.
The input sensor ISP may include a base insulating layer IIL1, a first conductive layer ICL1, a sensing insulating layer IIL2, a second conductive layer ICL2, and a cover insulating layer IIL3.
The base insulating layer IIL1 may be an inorganic layer including at least one of, for example, silicon nitride (Si3N4), silicon oxynitride (SiON), or silicon oxide (SiO2) Alternatively, the base insulating layer IIL1 may be an organic layer including, for example, an epoxy resin, an acrylic resin, or an imide-based resin. The base insulating layer IIL1 may have a single-layer structure or may have a multi-layer structure in which a plurality of layers are stacked in the third direction DR3.
Each of the first conductive layer ICL1 and the second conductive layer ICL2 may have a single-layer structure or may have a structure in which multiple layers are stacked in the third direction DR3.
Each of the first conductive layer ICL1 and the second conductive layer ICL2 includes a plurality of conductive patterns. The conductive patterns may include a plurality of sensing electrodes SE1_1 to SE1_5 and SE2_1 to SE2_4 (refer to
Each of the first conductive layer ICL1 and the second conductive layer ICL2 having the single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include, for example, molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), or an alloy thereof. The transparent conductive layer may include transparent conductive oxide such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include conductive polymer such as poly-(3,4)-ethylene-dihydroxy thiophene (PEDOT), metal nanowire, or graphene.
Each of the first conductive layer ICL1 and the second conductive layer ICL2 having the multi-layer structure may include metal layers. The metal layers may have, for example, a three-layer structure of titanium/aluminum/titanium (Ti/Al/Ti) or molybdenum/copper/molybdenum (Mo/Cu/Mo). The conductive layer of the multi-layer structure may include at least one metal layer and at least one transparent conductive layer.
At least one of the sensing insulating layer IIL2 or the cover insulating layer IIL3 may include an inorganic layer. The inorganic layer may include at least one of, for example, aluminum oxide (Al2O3), titanium oxide (TiO2), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), zirconium oxide (ZrO2), or hafnium oxide (HfO2).
At least one of the sensing insulating layer IIL2 or the cover insulating layer IIL3 may include an organic layer. The organic layer may include at least one of, for example, acrylate-based resin, methacrylate-based resin, polyisoprene-based resin, vinyl-based resin, epoxy-based resin, urethane-based resin, cellulose-based resin, siloxane-based resin, polyimide-based resin, polyamide-based resin, or perylene-based resin.
A parasitic capacitance Cb may be present between the input sensor ISP and the second electrode CE. The parasitic capacitance Cb may also be referred to as a “base capacitance”. As a distance between the input sensor ISP and the second electrode CE decreases, a value of the parasitic capacitance Cb may become greater. The greater the parasitic capacitance Cb, the smaller the ratio of a variation in capacitance to a reference value. The variation in capacitance means a change in a capacitance that occurs before and after an input by an input means, for example, the body of the user US (refer to
A sensor driving part ICP (refer to
The input sensor ISP may be disposed over the second electrode CE. The encapsulation layer TFE may be disposed between the second electrode CE and the input sensor ISP. The second electrode CE may generate a reference voltage of the display panel DP. For example, the second electrode CE may be connected with a second voltage line VL2 (refer to
In an embodiment of the present disclosure, the second electrode CE may be disposed between the first electrode AE and the light-emitting layer EL and the input sensor ISP and may prevent a noise, which depends on the influence by the display panel DP, from occurring in the input sensor ISP. That is, the second electrode CE may play a role of shielding the input sensor ISP from the light-emitting layer EL and the first electrode AE.
Referring to
In an embodiment of the present disclosure, the sensing electrodes SE1_1 to SE1_5 and SE2_1 to SE2_4 include transmit electrodes SE1_1 to SE1_5 and receive electrodes SE2_1 to SE2_4.
The signal lines SL1_1 to SL1_5 and SL2_1 to SL2_4 may include transmit signal lines SL1_1 to SL1_5 connected with the transmit electrodes SE1_1 to SE1_5 and receive signal lines SL2_1 to SL2_4 connected with the receive electrodes SE2_1 to SE2_4.
The transmit electrodes SE1_1 to SE1_5 and the receive electrodes SE2_1 to SE2_4 cross each other. The transmit electrodes SE1_1 to SE1_5 are arranged to be spaced apart from each other in the second direction DR2 and extend in the first direction DR1. The receive electrodes SE2_1 to SE2_4 are arranged to be spaced apart from each other in the first direction DR1 and extend in the second direction DR2. Since the receive electrodes SE2_1 to SE2_4 are longer than the transmit electrodes SE1_1 to SE1_5, a voltage drop of a detection signal (or a transmission signal) occurs and thus sensing sensitivity may be reduced. According to an embodiment of the present disclosure, unlike shown in
The input sensor ISP described above may obtain coordinate information in a mutual-capacitive sensing manner A capacitance is formed between the transmit electrodes SE1_1 to SE1_5 and the receive electrodes SE2_1 to SE2_4. The capacitance between the transmit electrodes SE1_1 to SE1_5 and the receive electrodes SE2_1 to SE2_4 may be changed by the external input TC (refer to
In an embodiment of the present disclosure, the input sensor ISP is not limited to one of the mutual-capacitive sensing manner and the self-capacitive sensing manner in obtaining coordinate information. The input sensor ISP may obtain the coordinate information by using both the mutual-capacitive sensing manner and the self-capacitive sensing manner.
Each of the transmit electrodes SE1_1 to SE1_5 includes a first sensor part SSP1 and a first connection part CP1 disposed in the active area AA. Each of the receive electrodes SE2_1 to SE2_4 includes a second sensor part SSP2 and a second connection part CP2 disposed in the active area AA.
Two first sensor parts SSP1 disposed at opposite ends of one of the transmit electrodes SE1_1 to SE1_5 among the first sensor parts SSP1 may be smaller in size than a first sensor part SSP1 disposed at the center, for example, may have a size corresponding to half a size of the first sensor part SSP1 disposed at the center. Each of two second sensor parts SSP2 disposed at opposite ends of one of the receive electrodes SE2_1 to SE2_4 among the second sensor parts SSP2 may be smaller in size than a second sensor part SSP2 disposed at the center, for example, may have a size corresponding to half a size of the second sensor part SSP2 disposed at the center.
The first sensor parts SSP1 are arranged in the second direction DR2 in each of the transmit electrodes SE1_1 to SE1_5, and the second sensor parts SSP2 are arranged in the first direction DR1 in each of the receive electrodes SE2_1 to SE2_4. Each of the first connection parts CP1 connects the first sensor parts SSP1 adjacent thereto, and each of the second connection parts CP2 connects the second sensor parts SSP2 adjacent thereto.
Each of the transmit electrodes SE1_1 to SE1_5 and the receive electrodes SE2_1 to SE2_4 may have a mesh shape. As each of the transmit electrodes SE1_1 to SE1_5 and the receive electrodes SE2_1 to SE2_4 has a mesh shape, a parasitic capacitance between electrodes of the input sensor ISP and electrodes included in the display panel DP (refer to
The mesh-shaped transmit electrodes SE1_1 to SE1_5 and the mesh-shaped receive electrodes SE2_1 to SE2_4 may include, but is not limited to, silver (Ag), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), etc.
The transmit signal lines SL1_1 to SL1_5 and the receive signal lines SL2_1 to SL2_4 may be disposed in the non-active area NAA.
The input sensor ISP may include input pads I_PD that extend from one ends of the transmit signal lines SL1_1 to SL1_5 and the receive signal lines SL2_1 to SL2_4 and are disposed in the non-active area NAA. The input pads I_PD may be electrically connected with the transmit signal lines SL1_1 to SL1_5 and the receive signal lines SL2_1 to SL2_4. In an embodiment of the present disclosure, the input pads I_PD may include a transmit input pad I_PD1 with which the transmit signal lines SL1_1 to SL1_5 are electrically connected and a receive input pad I_PD2 with which the receive signal lines SL2_1 to SL2_4 are electrically connected.
In an embodiment of the present disclosure, a pad area PLD in which the input pads I_PD are disposed may be included in the non-active area NAA. The input pads I_PD may be provided as some of circuit elements disposed in the circuit element layer DP-CL (refer to
The pad area PLD may further include pixel pads D_PD for connecting the flexible circuit film FCB (refer to
The display device DD may further include the sensor driving part ICP that controls the driving of the input sensor ISP.
In an embodiment of the present disclosure, the sensor driving part ICP may be electrically connected with the input sensor ISP. The sensor driving part ICP may be electrically connected with the transmit signal lines SL1_1 to SL1_5 and the receive signal lines SL2_1 to SL2_4 through the input pads I_PD.
The sensor driving part ICP transmits driving control signals DCS to the transmit electrodes SE1_1 to SE1_5, and receives sensing signals RS, to which a variation in a capacitance between the transmit electrodes SE1_1 to SE1_5 and the receive electrodes SE2_1 to SE2_4 is applied, from the receive electrodes SE2_1 to SE2_4. In an embodiment of the present disclosure, the driving control signals DCS may be sensing scan signals that are sequentially transferred to the transmit electrodes SE1_1 to SE1_5.
In an embodiment of the present disclosure, the sensor driving part ICP may drive the input sensor ISP in a first manner and/or a second manner. The first manner may be the mutual-capacitive sensing manner. The second manner may be a self-capacitive sensing manner. For example, the sensor driving part ICP may transmit the driving control signal DCS, which includes a first driving signal driving an input sensor in the first manner and a second driving signal driving the input sensor in the second manner, to each of the transmit electrodes SE1_1 to SE1_5.
The sensor driving part ICP may transmit the driving control signal DCS to the input sensor ISP based on a driving frequency of the display panel DP. In an embodiment of the present disclosure, the sensor driving part ICP may not transmit the driving control signal DCS when the driving frequency of the display panel DP is a high frequency and may transmit the driving control signal DCS when the driving frequency of the display panel DP is a low frequency. This will be described in detail later.
Referring to
The display driving part DCP includes a data driver DDR, a scan driver (SD1, SD2), an emission driver EDC, a voltage generator 300, and a driving controller DVC.
The driving controller DVC receives an image signal RGB and a control signal CTRL. The driving controller DVC generates an image data signal DATA by converting a data format of the image signal RGB in compliance with the specification for an interface with the data driver DDR. The control signal CTRL may include a vertical synchronization signal Vsync (refer to
The data driver DDR receives the data control signal SDS and the image data signal DATA from the driving controller DVC. The data driver DDR converts the image data signal DATA into data signals and outputs the data signals to a plurality of data lines DL1 to DLm to be described later. A data signal refers to an analog voltage corresponding to a gray scale value of the image data signal DATA.
The scan driver (SD1, SD2) includes a first scan driver SD1 and a second scan driver SD2. The first scan driver SD1 receives the first scan control signal SCS1 from the driving controller DVC, and the second scan driver SD2 receives the second scan control signal SCS2 from the driving controller DVC. The first scan driver SD1 may output low-frequency scan signals in response to the first scan control signal SCS1, and the second scan driver SD2 may output high-frequency scan signals in response to the second scan control signal SCS2.
The voltage generator 300 generates voltages necessary for an operation of the display panel DP. In an embodiment of the present disclosure, the voltage generator 300 generates a first driving voltage ELVDD, the second driving voltage ELVSS, and an initialization voltage VINT.
The display panel DP includes low-frequency scan lines SL_A1 to SL_An, high-frequency scan lines SL_B0 to SL_Bn, emission control lines EML1 to EMLn, the data lines DL1 to DLm, and pixels PX. The low-frequency scan lines SL_A1 to SL_An, the high-frequency scan lines SL_B0 to SL_Bn, the emission control lines EML1 to EMLn, the data lines DL1 to DLm, and the pixels PX may be disposed in a display area DA. The low-frequency scan lines SL_A1 to SL_An, the high-frequency scan lines SL_B0 to SL_Bn, and the emission control lines EML1 to EMLn extend in the first direction DR1. The low-frequency scan lines SL_A1 to SL_An, the high-frequency scan lines SL_B0 to SL_Bn, and the emission control lines EML1 to EMLn are arranged to be spaced apart from each other in the second direction DR2. The second direction DR2 may be a direction intersecting the first direction DR1. The data lines DL1 to DLm extend in the second direction DR2 and are arranged to be spaced apart from each other in the first direction DR1.
The plurality of pixels PX are electrically connected with the low-frequency scan lines SL_A1 to SL_An, the high-frequency scan lines SL_B0 to SL_Bn, the emission control lines EML1 to EMLn, and the data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected with three scan lines. For example, as illustrated in
The first and second scan drivers SD1 and SD2 may be disposed in a non-display area NDA of the display panel DP. The first scan driver SD1 outputs low-frequency scan signals to the low-frequency scan lines SL_A1 to SL_An in response to the first scan control signal SCS1, and the second scan driver SD2 outputs high-frequency scan signals to the high-frequency scan lines SL_B0 to SL_Bn in response to the second scan control signal SCS2.
The first scan driver SD1 may drive the low-frequency scan lines SL_A1 to SL_An at a first scan frequency in response to the first scan control signal SCS1, and the second scan driver SD2 may drive the high-frequency scan lines SL_B0 to SL_Bn at a second scan frequency in response to the second scan control signal SCS2. Herein, the second scan frequency may be higher than the first scan frequency.
The emission driver EDC receives an emission driving signal ECS from the driving controller DVC. The emission driver EDC may output emission control signals to the emission control lines EML1 to EMLn in response to the emission driving signal ECS.
The emission driver EDC may be disposed in the non-display area NDA of the display panel DP. In an embodiment of the present disclosure, the first and second scan drivers SD1 and SD2 may be disposed adjacent to a first side of the display area DA, and the emission driver EDC may be disposed adjacent to a second side of the display area DA. In other words, the display area DA may be provided between the first and second scan drivers SD1 and SD2 and the emission driver EDC. However, the present disclosure is not limited thereto. For example, the emission driver EDC may be disposed adjacent to the first side of the display area DA together with the first and second scan drivers SD1 and SD2. Alternatively, the first scan driver SD1 may be disposed adjacent to the first side of the display area DA, and the second scan driver SD2 and the emission driver EDC may be disposed adjacent to the second side of the display area DA.
Each of the plurality of pixels PX includes a light-emitting element ED (refer to
Each of the plurality of pixels PX may receive the first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT from the voltage generator 300.
An equivalent circuit diagram of one pixel PXij among the plurality of pixels PX illustrated in
Referring to
The pixel PXij includes the light-emitting element ED and the pixel circuit part PXC. The pixel circuit part PXC includes first to sixth transistors T1, T2, T3, T4, T5, and T6, first and second emission control transistors ET1 and ET2, and a capacitor Cst. Each of the first to sixth transistors T1, T2, T3, T4, T5, and T6 and the first and second emission control transistors ET1 and ET2 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. The first to sixth transistors T1 to T6 may be implemented with transistors of the same type. In an embodiment of the present disclosure, each of the first to sixth transistors T1 to T6 may be a P-type transistor, and each of the first and second emission control transistors ET1 and ET2 may also be a P-type transistor. A configuration of the pixel circuit part PXC according to the present disclosure is not limited to the embodiment illustrated in
The first transistor T1 includes a first electrode connected with a first voltage line VL1 through the first emission control transistor ET1, a second electrode electrically connected with an anode of the light-emitting element ED through the second emission control transistor ET2, and a third electrode connected with a first end of the capacitor Cst. The first voltage line VL1 may transfer the first driving voltage ELVDD to the pixel PXij. The first transistor T1 may be supplied with a data signal Dj, which the current data line DLj transfers, depending on a switching operation of the second transistor T2 and may supply a driving current Id to the light-emitting element ED. The light-emitting element ED may emit light having a certain luminance according to the driving current Id.
The second transistor T2 includes a first electrode connected with the current data line DLj, a second electrode connected with the first electrode of the first transistor T1, and a third electrode receiving a first scan signal SS1_Ai. The third electrode of the second transistor T2 may be electrically connected with the current low-frequency scan line SL_Ai. Accordingly, the second transistor T2 may receive an i-th low-frequency scan signal transferred through the current low-frequency scan line SL_Ai as the first scan signal SS1_Ai. The second transistor T2 may be turned on depending on the first scan signal SS1_Ai to transfer the data signal Dj transferred through the current data line DLj to the first electrode of the first transistor T1.
The third transistor T3 includes a first electrode connected with a first node N1, a second electrode connected with the second electrode of the first transistor T1, and a third electrode receiving a second scan signal SS2_Bi. The third electrode of the third transistor T3 may be electrically connected with the current high-frequency scan line SL_Bi. Accordingly, the third transistor T3 may receive an i-th high-frequency scan signal transferred through the current high-frequency scan line SL_Bi as the second scan signal SS2_Bi. The third transistor T3 may be turned on depending on the second scan signal SS2_Bi to electrically connect the first node N1 and the second electrode of the first transistor T1.
The fourth transistor T4 includes a first electrode connected with the first node N1, a second electrode connected with a third voltage line VL3, and a third electrode receiving a third scan signal SS3_Bi−1. The third voltage line VL3 may transfer the initialization voltage VINT to the pixel PXij. The third electrode of the fourth transistor T4 may be electrically connected with the previous high-frequency scan line SL_Bi−1. Accordingly, the fourth transistor T4 may receive an (i−1)-th high-frequency scan signal transferred through the previous high-frequency scan line SL_Bi−1 as the third scan signal SS3_Bi−1. The fourth transistor T4 may be turned on depending on the third scan signal SS3_Bi−1 to transfer the initialization voltage VINT to the first node Ni. In this case, the first node N1 may be initialized, that is, an initialization operation for the first node N1 may be performed.
In an embodiment of the present disclosure, the third transistor T3 and the fourth transistor T4 may each be configured to have a dual gate structure to cut off a leakage current. However, the present disclosure is not limited thereto.
The fifth transistor T5 includes a first electrode connected with the third electrode of the first transistor T1, a second electrode connected with the first node N1, and a third electrode receiving a fourth scan signal SS4_Ai. The third electrode of the fifth transistor T5 may be electrically connected with the current low-frequency scan line SL_Ai. Accordingly, the fifth transistor T5 may receive the i-th low-frequency scan signal transferred through the current low-frequency scan line SL_Ai as the fourth scan signal SS4_Ai. The fifth transistor T5 may be turned on depending on the fourth scan signal SS4_Ai to electrically connect the first node N1 and the third electrode of the first transistor T1.
The first end of the capacitor Cst is connected with the third electrode of the first transistor T1, and a second end thereof is connected with the first voltage line VL1. For example, the first transistor T1 is connected to the first voltage line VL1 and the capacitor Cst, and may be configured to control the driving current Id flowing through the light-emitting element ED from the first voltage line VL1, in response to the voltage stored in the capacitor Cst. The light-emitting element ED may be configured to emit light having a predetermined brightness according to the driving current Id. The turn-on time of the first transistor T1 may be determined according to the amount of voltage or charge stored in the capacitor Cst. The first transistor T1 may then provide to the light-emitting element ED the first driving voltage ELVDD transmitted through the first voltage line VL1 during the turn-on time.
The first emission control transistor ET1 includes a first electrode connected with the first voltage line VL1, a second electrode connected with the first electrode of the first transistor T1, and a third electrode connected with the current emission control line EMLi.
The second emission control transistor ET2 includes a first electrode connected with the second electrode of the first transistor T1, a second electrode connected with the anode of the light-emitting element ED, and a third electrode connected with the current emission control line EMLi.
The first and second emission control transistors ET1 and ET2 are simultaneously turned on depending on an emission control signal EMi transferred through the current emission control line EMLi. The first driving voltage ELVDD applied through the first emission control transistor ET1 turned on may be transferred to the light-emitting element ED through the first transistor T1 and the second emission control transistor ET2 turned on.
The sixth transistor T6 includes a first electrode connected with the second electrode of the fourth transistor T4, a second electrode connected with the second electrode of the second emission control transistor ET2, and a third electrode receiving a fifth scan signal SS5_Bi. The third electrode of the sixth transistor T6 may be electrically connected with the current high-frequency scan line SL_Bi. Accordingly, the sixth transistor T6 may receive the i-th high-frequency scan signal transferred from the current high-frequency scan line SL_Bi as the fifth scan signal SS5_Bi. When the sixth transistor T6 is turned on by the fifth scan signal SS5_Bi, the anode of the light-emitting element ED may be initialized to the initialization voltage VINT, that is, an initialization operation for the anode of the light-emitting element ED may be performed. When the sixth transistor T6 is in the turned off state, a part of the driving current Id may be discharged through the sixth transistor T6 as the bypass current Ibp. Thus, the emission current Ied of the light-emitting element ED may be reduced by the amount of the bypass current Ibp that has escaped from the driving current Id through the sixth transistor T6.
The anode of the light-emitting element ED may be connected with the second electrode of the second emission control transistor ET2 and the second electrode of the sixth transistor T6, and a cathode of the light-emitting element ED may be connected with the second voltage line VL2. The second voltage line VL2 may transfer the second driving voltage ELVSS to the pixel PXij.
The first and fourth scan signals SS1_Ai and SS4_Ai may be low-frequency scan signals output from the first scan driver SD1 operating at the first scan frequency, and the second, third, and fifth scan signals SS2_Bi, SS3_Bi−1, and SS5_Bi may be high-frequency scan signals output from the second scan driver SD2 operating at the second scan frequency. In an embodiment of the present disclosure, each of the first and fourth scan signals SS1_Ai and SS4_Ai may be the i-the low-frequency scan signal supplied from the current low-frequency scan line SL_Ai. Each of the second and fifth scan signals SS2_Bi and SS5_Bi may be the i-th high-frequency scan signal supplied from the current high-frequency scan line SL_Bi. However, the present disclosure is not limited thereto. For example, the first and fourth scan signals SS1_Ai and SS4_Ai may be signals that are supplied from different low-frequency scan lines, and the second and fifth scan signals SS2_Bi and SS5_Bi may be signals that are supplied from different high-frequency scan lines.
Referring to
The input sensor ISP may be disposed on the display panel DP to sense an external input. The input sensor ISP may sense the external input TC (refer to
The main driving part MCP may control an overall operation of the display device DD, and may serve as a central processing unit (CPU) of the display device DD. In an embodiment of the present disclosure, the main driving part MCP may control operations of the display driving part DCP and the sensor driving part ICP. The main driving part MCP may be disposed on the main circuit board MCB (refer to
The display driving part DCP may receive the image signal RGB and the control signal CTRL from the main driving part MCP. The control signal CTRL may include various signals. For example, the control signal CTRL may include the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, a main clock, a data enable signal, and the like.
The display driving part DCP may generate display signals SS for driving the display panel DP based on the image signal RGB and the control signal CTRL provided by the main driving part MCP. In an embodiment of the present disclosure, the display signals SS may include a data signal and scan signals.
The sensor driving part ICP may control the input sensor ISP. The sensor driving part ICP may receive a sensing control signal ICS, the vertical synchronization signal Vsync, and the horizontal synchronization signal Hsync. The sensor driving part ICP may receive information FCS about a driving frequency of a display panel from the display driving part DCP.
The sensing control signal ICS may include a sensing clock signal, a signal including information about a relationship between a sensing frequency of the input sensor ISP and a driving frequency of the display panel DP, and the like.
The sensor driving part ICP may generate the driving control signal DCS for driving the input sensor ISP based on the sensing control signal ICS, the vertical synchronization signal Vsync, and the horizontal synchronization signal Hsync. The sensor driving part ICP may control the output of the driving control signal DCS based on information FCS about the driving frequency of the display panel DP.
The sensor driving part ICP may calculate coordinate information of the external input TC (refer to
Referring to
The main driving part MCP may drive the input sensor ISP in a sensing mode or an inspection mode through the sensor driving part ICP. The input sensor ISP may be normally driven in the sensing mode and may sense an external input such as a touch of a user. The input sensor ISP may inspect a defect of a display panel in the inspection mode. In an embodiment of the present disclosure, the input sensor ISP may be driven at different frequencies in the inspection mode and the sensing mode.
The inspection part 100 may be included in the main driving part MCP. The inspection part 100 may be included in the main driving part MCP and may be connected with the sensor driving part ICP.
The inspection part 100 may be electrically connected with the sensor driving part ICP and the input sensor ISP and may detect a jitter change of the input sensor ISP. In this embodiment, the inspection part 100 may detect the jitter change of the input sensor ISP in the inspection mode and may inspect whether a defect (e.g., a deposition defect) of the display panel DP is disposed under the input sensor ISP, based on a detection result.
Herein, the jitter may correspond to “differences of an unstable signal”, which occur between a desired signal and an actually generated signal with regard to a specific signal. The jitter may include a phenomenon in which a digital pulse signal waveform is distorted on a time axis. That is, the jitter refers to a signal difference that appears during a short time with respect to an ideal position in time, and is one of important quality indices of a reproduced signal. As a change level of the jitter becomes greater, the probability that the quality is abnormal may be determined as becoming higher. On the other hand, as the change level of the jitter becomes smaller, the probability that the quality is normal may be determined as becoming higher.
In the case where a variation in a jitter occurring at a specific channel or sensing electrode of the input sensor ISP is relatively great, it may occur due to a shadow phenomenon according to a defect of the display panel DP adjacent to the corresponding sensing electrode. For example, in the case where the display panel DP is not shielded from the input sensor ISP due to the defect of the display panel DP, a noise may occur in the input sensor ISP due to the influence of the display panel DP. In this case, a change in the jitter of the input sensor ISP, which is measured by the inspection part 100, may increase.
As described above, the sensor driving part ICP may set a driving frequency when the input sensor ISP is normally driven. In an embodiment of the present disclosure, the inspection part 100 may be electrically connected with the sensor driving part ICP and may set an inspection frequency in the inspection mode of the input sensor ISP through the sensor driving part ICP.
The inspection part 100 may inspect a defect of the display panel DP through a change in the jitter that appears when the input sensor ISP is driven at the set inspection frequency in the inspection mode. In this embodiment, the inspection frequency may include a harmonic frequency of a driving frequency of a display panel.
Herein, the harmonics may be multiples of the fundamental frequency. For example, when the fundamental frequency is 1.2 GHz, the higher harmonics may be 2.4 GHz, 3.6 GHz, 4.8 GHz, and so on. That is, the harmonics of a frequency of a display panel may include multiples of the driving frequency of the display panel.
In an embodiment of the present disclosure, the inspection part 100 may detect a deposition defect of the second electrode CE of the display panel DP. In the case where a hole is present in the second electrode CE due to the deposition defect of the second electrode CE, a noise may occur in the input sensor ISP due to insufficient shielding.
The inspection part 100 may detect a jitter change of the input sensor ISP made by the noise coming from the deposition defect of the second electrode CE, may determine whether the deposition defect occurs in the second electrode CE based on a result of the detection, and may detect a location of the deposition defect. In detail, in the inspection mode where the input sensor ISP is driven at the inspection frequency, the inspection part 100 may detect a specific sensing electrode at which a jitter level is higher than a reference level and may detect a deposition defect with respect to a specific portion of the second electrode CE disposed physically adjacent to the specific sensing electrode thus detected. For example, the specific sensing electrode of the input sensor ISP having the higher jitter level may overlap the deposition defect of the second electrode CE of the display panel DP.
Referring to
The frequency selection part 110 may select an inspection frequency of the input sensor ISP, and may store the selected inspection frequency. The frequency selection part 110 may select a frequency, which allows a magnitude of a change in the jitter of the input sensor ISP to increase, as the inspection frequency. The frequency selection part 110 may select a harmonic of a frequency of the display panel DP as the inspection frequency. The inspection frequency may be provided in plurality. For example, the frequency selection part 110 may be connected to the sensor driving part ICP to drive the input sensor ISP at a plurality of frequencies of a given range, with the display panel DP being driven.
In an embodiment of the present disclosure, the frequency selection part 110 may select a value, which is obtained by multiplying the number of scan lines of the display panel DP and a refresh rate of a screen together, as the inspection frequency. For example, in the 2400×1080 resolution, in the case where the number of scan lines is 2400 and a refresh rate is 120 Hz, a frequency of about 288 KHz may be selected as the inspection frequency. Herein, the refresh rate may correspond to a frame rate.
In an embodiment of the present disclosure, the frequency selection part 110 may select frequencies, at which a magnitude of a level change of the jitter is a specific reference or more, from among a plurality of arbitrary frequencies as the inspection frequency. The frequency selection part 110 may select frequencies, at which a level of the jitter is relatively great due to the harmonics of the frequency of the display panel DP, from among the plurality of arbitrary frequencies as the inspection frequency. For example, in a frequency range from 225 KHz to 270 HKz, when jitter levels at 226.5 KHz and 230 KHz are higher than jitter levels at the remaining frequencies, frequencies of 226.5 KHz and 230 KHz may correspond to the harmonics of the frequency of the display panel DP, and the frequency selection part 110 may select the frequencies 226.5 KHz and 230 KHz from a plurality of frequencies belonging to a range from 225 KHz to 270 KHz as the inspection frequency.
In an embodiment of the present disclosure, the frequency selection part 110 may select a frequency, for example, through a calculation, from the driving frequency of the display panel DP through the fast Fourier transform, with the display panel DP driven and the input sensor ISP not driven. The selected frequency may correspond to a harmonic of the driving frequency of the display panel DP. The frequency selection part 110 may select the calculated frequency as the inspection frequency.
The frequency selection part 110 may store selected frequencies in a memory. The memory may be included in the main driving part MCP or the inspection part 100. Alternatively, the frequency selection part 110 may store the selected frequency in the sensor driving part ICP.
The frequency setting part 120 may fetch the frequency selected by the frequency selection part 110 in the inspection mode and may set the fetched frequency to the inspection frequency. In the case where the input sensor ISP switches from the sensing mode to the inspection mode, the frequency setting part 120 may set the inspection frequency for driving the input sensor ISP in the inspection mode. In detail, the frequency setting part 120 may be electrically connected with the sensor driving part ICP and may set a frequency of the input sensor ISP to the inspection frequency through the sensor driving part ICP.
The defect detection part 130 may detect a defect of a specific portion of a display panel, which is adjacent to a specific sensing electrode detected at the set inspection frequency. That is, the defect detection part 130 may detect the defect of the display panel DP.
In an embodiment of the present disclosure, in the inspection mode, the defect detection part 130 may extract specific sensing electrodes, at which a jitter level is higher than a reference level, from among the plurality of sensing electrodes SE1_1 to SE1_5 and SE2_1 to SE2_4 (refer to
A control part 140 may perform the signal transfer between the frequency selection part 110, the frequency setting part 120, and the defect detection part 130 and may control the frequency selection part 110, the frequency setting part 120, and the defect detection part 130.
In
The defect inspecting method may include setting an inspection frequency of an input sensor and driving the input sensor (S200) at the inspection frequency. The inspection frequency of the input sensor may include the harmonic of the driving frequency of the display panel. The input sensor may be driven at the inspection mode in which the input sensor is driven at the inspection frequency. The harmonic may not be used in the sensing mode of the input sensor.
The defect inspecting method may include detecting a change in the jitter of the input sensor (S300). A level change of the jitter for the plurality of sensing electrodes of the input sensor may increase in the inspection frequency. That is, a jitter level of the input sensor when the input sensor is driven at the inspection frequency may have a significant difference at a portion of the display panel, at which a defect occurs. For example, the inspection part 100 may be connected with the sensor driving part ICP, and configured to set a frequency of the input sensor ISP to an inspection frequency and to detect the defect of the display panel based on a change in a jitter occurring when the input sensor ISP is driven at the inspection frequency. In operation S300 in which the jitter change is detected, a sensing electrode at which a jitter level is relatively high may be distinguished from a sensing electrode at which a jitter level is not relatively high.
The defect inspecting method may include determining a defect of the display panel based on the jitter change (S400). The portion of the display panel, at which the defect occurs, may correspond to a portion of the display panel overlapping a sensing electrode, at which a jitter level is relatively high, from among sensing electrodes of the input sensor. In detail, it may be determined that a defect occurs at a specific portion of the display panel overlapping a specific sensing electrode, at which a jitter level is relatively high, from among the sensing electrodes.
In
The determining of the defect of the display panel may include extracting a specific sensing electrode including a jitter level higher than the reference level from among extracted jitter levels (S420). The specific sensing electrode including the jitter level higher than the reference level may include at least one sensing electrode or a plurality of sensing electrodes. The number of specific sensing electrodes may indicate the number of portions of the display panel, at which a defect occurs.
The determining of the defect of the display panel may include determining a specific portion of the display panel overlapping the extracted sensing electrode as a defect (S430).
The defect inspecting method may include inspecting the defect of the display panel based on the jitter level of the input sensor. That is, according to the defect inspecting method, when there is detected at least one specific sensing electrode having a specific jitter level exceeding the reference level, a specific portion of the display panel, which overlaps the specific sensing electrode, may be determined as a defect.
When a frequency belongs to a range from 290 KHz to 296 KHz, a maximum jitter level is “8695”. That is, when a frequency belongs to a range from 290 KHz to 296 KHz, the jitter level may exceed “279” being the reference level, and thus, the inspection frequency may be the frequency belonging to the range from 290 KHz to 296 KHz.
Except for some frequencies at which the jitter level is less than “279”, most frequencies from 200 KHz to 500 KHz may be selected as the inspection frequency. For example, all of a plurality of frequencies including about 215 KHz, about 224 KHz, about 338 KHz, about 370 KHz, about 422 KHz, and about 440 KHz at which the jitter level is about “1000” may exceed the reference level and may be selected as the inspection frequency.
In
In an embodiment of the present disclosure, the display panel DP (refer to
It is observed that, when the number of frames to be driven is 10 or 20, the event where the jitter level exceeds 50 being a reference level occurs limitedly. However, in the case where the number of frames to be driven is 100, it is observed that sensing electrodes each having a jitter level exceeding the reference level of 50 appear clearly. For example, when the number of frames to be driven is 10 or 20, because jitter levels of sensing electrodes Rx4 and Rx5 are equal to or less than the reference level, it may be difficult to detect a defect of the display panel. In contrast, when the number of frames to be driven is 100, because the jitter levels of the sensing electrodes Rx4 and Rx5 are about 200 exceeding the reference level of 50, it may be possible to detect a defect of the display panel.
The inspection part 100 (refer to
According to an embodiment of the present disclosure, an apparatus and a method for inspecting a defect of a display panel may effectively detect the defect of the display panel, which reduces performance of an input sensor.
According to an embodiment of the present disclosure, an apparatus and a method for inspecting a defect of a display panel may determine a specific inspection frequency increasing a magnitude of a jitter of an input sensor and may detect the defect of the display panel based on a clear change of the jitter of the input sensor driven at the inspection frequency thus determined.
While the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made therein without departing from the spirit and scope of the present disclosure as defined in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0039295 | Mar 2022 | KR | national |
