Patent Application
20060190888
This invention relates to a system and method for transistor design.
Software products are commercially available that can be used for simulating circuit designs. A circuit designer can input information regarding the layout of a circuit and run a simulation. The simulation then provides the circuit designer with an idea of how a physical implementation of the circuit is likely to perform. If the circuit does not perform as desired, the circuit designer can change the layout of the circuit and run further simulations until desirable circuit function is achieved. This type of designing and testing is more efficient than building and testing physical test circuits, so the use of computers and software for circuit design has become commonplace.
Software products have also been proposed that can be used for simulating the operation of electronic component designs. A designer can provide the software with physical characteristics of an electronic device, and the software then simulates the operation of the device. The simulation can provide the device designer with operational characteristics of the device, allowing the designer to make changes to the physical structure of the device until desired operation has been achieved.
Prior systems and software products, such as those described above, are useful to a circuit or electronic device designer in that they allow ideas to be tested and improved before time and money is spent building an actual product. These systems still require, however, the time of a skilled designer who interprets the simulation results and makes changes to a device based on the simulation results in order to achieve desired performance.
The present disclosure presents a system and method for device design wherein a user can provide desired performance parameters and, in return, receive an indication of physical characteristics of a device that can achieve the desired performance parameters. For example, disclosed herein is a system and method for translating an existing design of one technology type to another technology type. An existing design for a transistor of one technology type can be translated to design a new transistor of another technology type.
Embodiments are illustrated by way of example in the accompanying figures, in which like reference numbers indicate similar parts, and in which:
The present invention is directed to apparatuses and methods for a transistor design system. The transistor design system can comprise a software product executable by a computer system, for example as shown in
The present disclosure presents a system and method for device design wherein a user can provide desired performance parameters and, in return, receive an indication of physical characteristics of a device that can achieve the desired performance parameters. For example, disclosed herein is a system and method for translating an existing design of one technology type to another technology type. An existing design for a transistor of one technology type can be translated to design a new transistor of another.
Next, at block 42, the system uses data received for the existing transistor design to calculate additional parameters related to the existing transistor. In some embodiments, block 42 can be optional since such additional parameters may have been previously calculated or otherwise obtained.
Next, at block 44, the system inputs information related to the new transistor design. This can include inputting information such as a technology node or family for the new transistor design, design rules for the new transistor design, and/or equations for calculating parameters of the new transistor design. At block 46, the system establishes constraints for the new transistor design. Constraints can include parameters or characteristics of the existing transistor design that should be implemented in the new transistor design.
Next, at block 48, the system calculates characteristics and parameters of the new transistor design. In some embodiments, this includes calculating a geometry of the new transistor design. The results of the calculations are output (e.g., provided to the user) at block 50.
The process in
At block 40, the system establishes a particular existing transistor design to be used for the translation process. This can be accomplished in any of a number of ways, including allowing a user to select “NMOS low Vt” from a list of existing transistor designs, by receiving imported design or model data for the “NMOS low Vt”, or by allowing manual input of design data for “NMOS low Vt”.
Next, at block 42, the system calculates device parameters for the existing NMOS low Vt design. In this case, the design data includes information for the NMOS low Vt transistor including a channel length L=0.2 μm, a gate width W=25 μm, and terminal voltages Vgs=Vds=1.2v (where Vgs is a gate-source voltage and Vds is a drain-source voltage). The design data can also include equations for calculating other parameters of the transistor. For example, for the NMOS low Vt, drain current Id can be calculated to be 16 mA according to equation (1) below, transconductance (Gm) can be calculated to be 21 mS according to equation (2) below, output resistance (Ro) can be calculated to be 692 ohms according to equation (3) below, and gate capacitance (Cg) can be calculated to be 37 fF according to equation (4) below.
Id=f1(W,L,Vgs, Vds) (1)
Gm=f2(W,L,Vgs, Vds)=d(f1)/d(Vgs) (2)
Ro=f3(W,L,Vgs, Vds)=d(f1)/d(Vds) (3)
Cg=f4(W,L) (4)
More specifically, since the existing transistor design is an NMOS, the drain current Id can be calculated according to equation (5) below.
Id=(W/L)(K)(Vgs−Vt)2 (5)
In equation (5), Vt is the threshold voltage, and K is a value that can be expressed according to equations (6) and (7) below.
K=(½)μeCox (6)
Cox=εoεr/tox (7)
In equation (6), μe is the electron mobility and Cox is capacitance per unit area. In equation (7), εo is the permittivity constant (εo=8.85×10−12 F/m), εr is the relative permittivity (e.g., εr=3.9 for SiO2), tox is the gate-oxide thickness. In the present example, the calculations can result in Id=16 mA, Gm=21 mS, Ro=692 ohms, and Cg=37 fF.
Next, at block 44, the system establishes a particular type of transistor (“NMOS standard Vt” in the present example) to which the previously-established existing transistor design (“NMOS low Vt” in the present example) will be translated. This can be accomplished in any of a number of ways, including allowing a user to select “NMOS standard Vt” from a list, by receiving imported data for the “NMOS standard Vt”, or by allowing manual input of data for “NMOS standard Vt”. Then, at block 46, the system establishes constraints related to the new transistor design. This can include design rules specific to the type of transistor to which the existing transistor design is being translated. This can also include allowing the designation of parameters of the existing transistor design that should be the same for the new transistor design. In the present example, the system can be instructed to match Id and Ro (e.g., the new transistor should have Id=16 mA and Ro=692 ohms).
Next, at block 48, the system can calculate device characteristics, for example device geometry, for the new transistor design. This can be accomplished by solving a series of equations based on Equations (1)-(4) above using a Taylor series expansion and the Newton-Raphson method. In the present example, such calculations can provide the following results: gate width W=42 μm, channel length L=0.3 μm, drain current Id=16 mA, transconductance Gm=25 mS, output resistance Ro=692 ohms, and gate capacitance Cg=108 fF. These results are then output at block 50 via any type of one or more output devices (including a display).
While various embodiments in accordance with the principles disclosed herein have been described above, it should be understood that they have been presented by way of example only, and are not limiting. Thus, the breadth and scope of the invention(s) should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the claims and their equivalents issuing from this disclosure. Furthermore, the above advantages and features are provided in described embodiments, but shall not limit the application of such issued claims to processes and structures accomplishing any or all of the above advantages.
Additionally, the section headings herein are provided for consistency with the suggestions under 37 CFR 1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the invention(s) set out in any claims that may issue from this disclosure. Specifically and by way of example, although the headings refer to a “Technical Field,” such claims should not be limited by the language chosen under this heading to describe the so-called technical field. Further, a description of a technology in the “Background” is not to be construed as an admission that technology is prior art to any invention(s) in this disclosure. Neither is the “Brief Summary” to be considered as a characterization of the invention(s) set forth in issued claims. Furthermore, any reference in this disclosure to “invention” in the singular should not be used to argue that there is only a single point of novelty in this disclosure. Multiple inventions may be set forth according to the limitations of the multiple claims issuing from this disclosure, and such claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of such claims shall be considered on their own merits in light of this disclosure, but should not be constrained by the headings set forth herein.
