Claims
- 1. In a digital signal processing system, an apparatus for communicating digital signals in a plurality of domains, comprising:a first clock generating first timing signals for a first timing domain; a second clock generating second timing signals for a second timing domain, the first and second clocks operating substantially independent of each other; a clock sensitive device, connected to the first and second clocks, operating in the first timing domain, the first timing domain synchronized to the first timing signals of the first clock; and, means, responsive to an event, for dynamically transitioning the operation of the clock sensitive device to the second timing domain, the second domain synchronized to the second timing signals of the second clock.
- 2. The apparatus as in claim 1 wherein the first clock is a processor clock, and wherein the clock sensitive device is a synchronous memory communicating address and data signals with a processor operating in the first timing domain, and wherein the second clock is a system clock, and wherein the synchronous memory communicates address and data signals with an asynchronous data processing device operating in the second timing domain.
- 3. The apparatus as in claim 2 further comprising:a phase locked loop circuit connected to the first and second clocks to synchronize the first and second timing signals of the processor clock and the system clock.
- 4. The apparatus as in claim 1 wherein the first timing domain is synchronized to a processor clock, and the second timing domain is synchronized to a system clock, the frequency of the processor clock and the frequency of the system clock being different, and where the clock sensitive device is a synchronous memory, the synchronous memory communicating address and data signals with a processor while operating in the first timing domain, and the synchronous memory communicating address and data signals with an asynchronous data processing device while operating in the second timing domain.
- 5. The apparatus as in claim 4 further comprising:an issue state machine generating an issue signal in response to the event; an address generator, in response to the issue signal, generating an address signal of the data to be communicated; a clock generator generating an access clock signal in response to the issue signal, the access clock signal to propagate the address signal of the data.
- 6. The apparatus as in claim 5 wherein the address generator further comprises:a counter to increment the address signal a predetermined number of times in response to the event.
- 7. The apparatus as in claim 5 wherein the clock generator further comprises:a divide-by-two circuit coupled to the processor clock and the issue state machine, the divide-by-two circuit deriving the access clock signal from the processor clock in response to the issue signal.
- 8. The apparatus as in claim 5 further comprising:a control register, the control register storing a ratio, a read size, a read speed, a write speed, and a wave, the control register coupled to the issue state machine, the ratio indicating the number of pulses generated by the processor clock for every one pulse generated by the system clock, the read size indicating the predetermined number of times the address signal is incremented by the counter, the read speed indicating a number of access clock signals required to process a read access, the write speed indicating a number of access clock signals required to process a write access, and the wave indicating the number of access clock signals required before a next read access can be processed after a last read access has been initiated by the issue signal.
- 9. The apparatus as in claim 5 further comprising:means for generating the issue signal independent of when a last system clock signal was generated.
- 10. The apparatus as in claim 1 wherein the clock sensitive device is a synchronous memory, further comprising:means for initiating a data access in the second timing domain using the second timing signals; means, while processing the data access in the second timing domain, for transitioning the synchronous device to operate in the first timing domain.
- 11. The apparatus as in claim 1 wherein the first clock is a processor clock to synchronize the first timing signals, the second clock is a system clock to synchronize the second timing signals, a processor operating in the first timing domain, an asynchronous data processing device operating in the second timing domain, and the clock sensitive device is a synchronous memory, the synchronous memory communicating address and data signals with the processor while operating in the first timing domain and the synchronous memory communicating address and data signals with the asynchronous data processing device while operating in the second timing domain.
- 12. The apparatus as in claim 11 wherein the asynchronous device is a random access memory, and wherein the event is a data miss in the synchronous memory, the data miss requiring missing data at a first miss address and at a second miss address of the synchronous memory, and further comprising:means, in response to the data miss, for initiating the processing of the data miss at the first miss address in the second domain; means, while processing the data miss at the first miss address in the second domain, for continuing to operate the synchronous memory in the first timing domain; and means, in response to a completion of the processing of the data miss at the first miss address, for transitioning the synchronous memory to operate in the second timing domain to receive the missing data at the first miss address, and for transitioning the synchronous memory to operate in the first timing domain after receiving the missing data at the first miss address in the second timing domain.
- 13. The apparatus as in claim 12 further comprising:means, while processing the data miss at the first miss address in the second timing domain, for incrementing the first miss address to a second miss address; and means, while processing the data miss at the first miss address in the second timing domain, initiating the processing of the data miss at the second miss address in the second timing domain.
- 14. The apparatus as in claim 12 further comprising:means for determining a next processor clock signal to transitioning the operation of the synchronous memory from the first timing domain to the second timing domain.
- 15. In a digital signal processing system, a method for operating a clock sensitive device in a plurality of domains, comprising:generating first timing signals form a first clock for a first timing domain; generating second timing signals form a second clock for a second timing domain; operating the first and second clocks substantially independent of each other; operating a clock sensitive device connected to the first and second clocks in the first timing domain; in response to an event, dynamically transitioning the operation of the clock sensitive device to the second timing domain, the second timing domain synchronized to the second timing signals of the second clock, the first timing and signals being different in frequency, shape, and protocol than the second timing signals.
- 16. The method as in claim 15 wherein the first clock is a processor clock, and wherein the clock sensitive device is a synchronous memory communicating address and data signals with a processor operating in the first timing domain, and wherein the second clock is a system clock, and wherein the synchronous memory communicates address and data signals with an asynchronous data processing device operating in the second timing domain.
- 17. The method as in claim 15 wherein first timing signals are synchronized to a processor clock, and the second timing signals are synchronized to a system clock, and where the clock sensitive device is a synchronous memory, and further comprising:communicating address and data signals between the synchronous memory and a processor while operating in the first timing domain; and communicating address and data signals between the synchronous memory and an asynchronous data processing device while operating in the second timing domain.
Parent Case Info
This application is a continuation of application Ser. No. 08/440,151, filed May 12, 1995 now abandoned.
US Referenced Citations (12)
Non-Patent Literature Citations (2)
Entry |
DeLano et al., “A High Speed Superscalar PA-RISC Processor”, IEEE COMPCON Conference, 1992, pp. 116-121.* |
Liu et al., “Microcomputer Systems: The 8086/8088 Family Architecture, Programming and Design”, Prentice-Hall, 1986, pp. 16-20. |
Continuations (1)
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Number |
Date |
Country |
Parent |
08/440151 |
May 1995 |
US |
Child |
08/893309 |
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US |