for memories with random access ports synchronised on clock signal pulse trains

Industry

CPC
G11C7/1072

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/1072for memories with random access ports synchronised on clock signal pulse trains

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Memory system and method of controlling a memory chip
- Patent number 12,154,659
- Issue date Nov 26, 2024
- Kioxia Corporation
- Shinya Koizumi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread scheduling control and memory splitting in a barrel processor
- Patent number 12,135,987
- Issue date Nov 5, 2024
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array reset read operation
- Patent number 12,119,051
- Issue date Oct 15, 2024
- Jeremy Binfet
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for memory power management and memory devices and systems...
- Patent number 12,112,830
- Issue date Oct 8, 2024
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component with adjustable core-to-interface data rate ratio
- Patent number 12,094,565
- Issue date Sep 17, 2024
- RAMBUS INC.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Grant
Banked memory architecture for multiple parallel datapath channels...
- Patent number 12,079,137
- Issue date Sep 3, 2024
- Microsoft Technology Licensing, LLC
- Stephen Sangho Youn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to control system updates and configuration changes via...
- Patent number 12,081,323
- Issue date Sep 3, 2024
- Intel Corporation
- Murugasamy K. Nachimuthu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal receiver with skew-tolerant strobe gating
- Patent number 12,062,413
- Issue date Aug 13, 2024
- RAMBUS INC.
- Andrew M. Fuller
- G11 - INFORMATION STORAGE
Information Patent Grant
Technologies for switching network traffic in a data center
- Patent number 12,040,889
- Issue date Jul 16, 2024
- Intel Corporation
- Matthew Adiletta
- B25 - HAND TOOLS PORTABLE POWER-DRIVEN TOOLS MANIPULATORS
Information Patent Grant
Mitigating interference between commands for different access reque...
- Patent number 12,026,107
- Issue date Jul 2, 2024
- PANASONIC AUTOMOTIVE SYSTEMS CO., LTD.
- Kazuhito Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for data movement
- Patent number 12,019,895
- Issue date Jun 25, 2024
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double data rate (DDR) memory controller apparatus and method
- Patent number 12,014,767
- Issue date Jun 18, 2024
- Uniquify, Inc.
- Mahesh Gopalan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic device test method and test device
- Patent number 11,994,558
- Issue date May 28, 2024
- Realtek Semiconductor Corp.
- Han-Yun Tsai
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal processing circuit, chip and electronic device
- Patent number 11,972,838
- Issue date Apr 30, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Zequn Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and operating method of the memory system
- Patent number 11,972,839
- Issue date Apr 30, 2024
- SK Hynix Inc.
- Chang Kyun Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device delaying mode control signals
- Patent number 11,967,398
- Issue date Apr 23, 2024
- SK hynix Inc.
- Haeng Seon Chae
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system with multiple striping of RAID groups and method for...
- Patent number 11,960,743
- Issue date Apr 16, 2024
- Innovations In Memory LLC
- Jon C. R. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with looped-back calibration data receiver
- Patent number 11,960,344
- Issue date Apr 16, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory systems with on-die data buffering
- Patent number 11,960,418
- Issue date Apr 16, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command-triggered data clock distribution mode
- Patent number 11,955,161
- Issue date Apr 9, 2024
- RAMBUS INC.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device including internal transmission path and stack...
- Patent number 11,942,181
- Issue date Mar 26, 2024
- SK Hynix Inc.
- Jinhyung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for addressing memory caches
- Patent number 11,921,642
- Issue date Mar 5, 2024
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system and operating method of the memory system
- Patent number 11,915,790
- Issue date Feb 27, 2024
- SK Hynix Inc.
- Chang Kyun Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory-based distributed processor architecture
- Patent number 11,914,487
- Issue date Feb 27, 2024
- NeuroBlade Ltd.
- Elad Sity
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory component for deployment in a dynamic stripe width memory sy...
- Patent number 11,862,236
- Issue date Jan 2, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable trim settings on a memory device
- Patent number 11,854,634
- Issue date Dec 26, 2023
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for dynamically managing resources in disaggregated ac...
- Patent number 11,855,766
- Issue date Dec 26, 2023
- Intel Corporation
- Francesc Guim Bernat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory buffer with data scrambling and error correction
- Patent number 11,854,658
- Issue date Dec 26, 2023
- RAMBUS INC.
- Christopher Haywood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to verify and authenticate resources in a data center co...
- Patent number 11,838,113
- Issue date Dec 5, 2023
- Intel Corporation
- Alberto J. Munoz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock locking for packet based communications of memory devices
- Patent number 11,837,318
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES
- Publication number 20240402788
- Publication date Dec 5, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO CONTROL SYSTEM UPDATES AND CONFIGURATION CHANGES VIA...
- Publication number 20240372792
- Publication date Nov 7, 2024
- Intel Corporation
- MURUGASAMY K. NACHIMUTHU
- B25 - HAND TOOLS PORTABLE POWER-DRIVEN TOOLS MANIPULATORS
Information Patent Application
STACKED MEMORY DEVICES, SYSTEMS, AND METHODS
- Publication number 20240345737
- Publication date Oct 17, 2024
- Lodestar Licensing Group, LLC
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR DATA MOVEMENT
- Publication number 20240345756
- Publication date Oct 17, 2024
- Lodestar Licensing Group LLC
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20240345971
- Publication date Oct 17, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM WITH MULTIPLE STRIPING OF RAID GROUPS AND METHOD FOR...
- Publication number 20240302983
- Publication date Sep 12, 2024
- Innovations In Memory LLC
- Jon C.R. BENNETT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APERTURE ACCESS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
- Publication number 20240289160
- Publication date Aug 29, 2024
- Intel Corporation
- Barry E. Huntley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
- Publication number 20240290372
- Publication date Aug 29, 2024
- Uniquify, Inc.
- Mahesh GOPALAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT
- Publication number 20240282357
- Publication date Aug 22, 2024
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatuses for Addressing Memory Caches
- Publication number 20240273032
- Publication date Aug 15, 2024
- Rambus Inc.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR APPARATUS INCLUDING A PLURALITY OF CLOCK PATHS AND A...
- Publication number 20240203469
- Publication date Jun 20, 2024
- SK HYNIX INC.
- Ji Hyo KANG
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE
- Publication number 20240203516
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACK...
- Publication number 20240194232
- Publication date Jun 13, 2024
- SK HYNIX INC.
- Jinhyung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES F...
- Publication number 20240184451
- Publication date Jun 6, 2024
- Lodestar Licensing Group LLC
- Timothy Hollis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEM
- Publication number 20240177754
- Publication date May 30, 2024
- SK HYNIX INC.
- Chang Kyun PARK
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
- Publication number 20240177747
- Publication date May 30, 2024
- Rambus Inc.
- Ian P. Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH OPERATION IN MULTI-DIE MEMORY
- Publication number 20240170035
- Publication date May 23, 2024
- Lodestar Licensing Group LLC
- Matthew A. Prather
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY BUFFER WITH DATA SCRAMBLING AND ERROR CORRECTION
- Publication number 20240161795
- Publication date May 16, 2024
- Rambus Inc.
- Christopher HAYWOOD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method to Provide Cache Move with Non-Volatile Mass M...
- Publication number 20240152274
- Publication date May 9, 2024
- Memory Technologies LLC
- Kimmo J. Mylly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE PROCESSOR FOR LOW-WAY AND HIGH-LATENCY MEMORY INST...
- Publication number 20240143457
- Publication date May 2, 2024
- NeuroBlade Ltd.
- Elad SITY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR DYNAMICALLY MANAGING RESOURCES IN DISAGGREGATED AC...
- Publication number 20240113954
- Publication date Apr 4, 2024
- Intel Corporation
- Francesc GUIM BERNAT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
- Publication number 20240112721
- Publication date Apr 4, 2024
- Uniquify, Inc.
- Mahesh GOPALAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP
- Publication number 20240046971
- Publication date Feb 8, 2024
- KIOXIA Corporation
- Shinya KOIZUMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controllers, systems, and methods supporting multiple reques...
- Publication number 20230420010
- Publication date Dec 28, 2023
- Rambus Inc.
- Richard E. Perego
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low-Pincount High-Bandwidth Memory And Memory Bus
- Publication number 20230385224
- Publication date Nov 30, 2023
- ETRON TECHNOLOGY, INC.
- Richard Dewitt Crisp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE HAVING VOLATILE AND NON-VOLATILE MEMORY SUBSYSTEMS AN...
- Publication number 20230385192
- Publication date Nov 30, 2023
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER WITH SKEW COMPENSATED DATA TRANSMIT TIMING
- Publication number 20230335177
- Publication date Oct 19, 2023
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES HAVING SPECIAL MODE ACCESS
- Publication number 20230335166
- Publication date Oct 19, 2023
- Micron Technology, Inc.
- Theodore T. Pekny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT
- Publication number 20230326513
- Publication date Oct 12, 2023
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...
- Publication number 20230317128
- Publication date Oct 5, 2023
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE

for memories with random access ports synchronised on clock signal pulse trains

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory system and method of controlling a memory chip

Thread scheduling control and memory splitting in a barrel processor

Memory array reset read operation

Methods for memory power management and memory devices and systems...

Memory component with adjustable core-to-interface data rate ratio

Banked memory architecture for multiple parallel datapath channels...

Techniques to control system updates and configuration changes via...

Signal receiver with skew-tolerant strobe gating

Technologies for switching network traffic in a data center

Mitigating interference between commands for different access reque...

Apparatuses and methods for data movement

Double data rate (DDR) memory controller apparatus and method

Electronic device test method and test device

Signal processing circuit, chip and electronic device

Memory system and operating method of the memory system

Semiconductor device delaying mode control signals

Memory system with multiple striping of RAID groups and method for...

Memory controller with looped-back calibration data receiver

Semiconductor memory systems with on-die data buffering

Command-triggered data clock distribution mode

Semiconductor device including internal transmission path and stack...

Methods and apparatuses for addressing memory caches

Memory system and operating method of the memory system

Memory-based distributed processor architecture

Memory component for deployment in a dynamic stripe width memory sy...

Selectable trim settings on a memory device

Technologies for dynamically managing resources in disaggregated ac...

Memory buffer with data scrambling and error correction

Techniques to verify and authenticate resources in a data center co...

Clock locking for packet based communications of memory devices

Patents Applicationslast 30 patents

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

TECHNIQUES TO CONTROL SYSTEM UPDATES AND CONFIGURATION CHANGES VIA...

STACKED MEMORY DEVICES, SYSTEMS, AND METHODS

APPARATUSES AND METHODS FOR DATA MOVEMENT

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

MEMORY SYSTEM WITH MULTIPLE STRIPING OF RAID GROUPS AND METHOD FOR...

APERTURE ACCESS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT

Methods and Apparatuses for Addressing Memory Caches

SEMICONDUCTOR APPARATUS INCLUDING A PLURALITY OF CLOCK PATHS AND A...

SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE

SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACK...

APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES F...

MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEM

MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT

REFRESH OPERATION IN MULTI-DIE MEMORY

MEMORY BUFFER WITH DATA SCRAMBLING AND ERROR CORRECTION

Apparatus and Method to Provide Cache Move with Non-Volatile Mass M...

HIGH PERFORMANCE PROCESSOR FOR LOW-WAY AND HIGH-LATENCY MEMORY INST...

TECHNOLOGIES FOR DYNAMICALLY MANAGING RESOURCES IN DISAGGREGATED AC...

DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP

Memory controllers, systems, and methods supporting multiple reques...

Low-Pincount High-Bandwidth Memory And Memory Bus

MEMORY MODULE HAVING VOLATILE AND NON-VOLATILE MEMORY SUBSYSTEMS AN...

MEMORY CONTROLLER WITH SKEW COMPENSATED DATA TRANSMIT TIMING

MEMORY DEVICES HAVING SPECIAL MODE ACCESS

MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT

MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...