for memories with random access ports synchronised on clock signal pulse trains

Industry

CPC
G11C7/1072

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/1072for memories with random access ports synchronised on clock signal pulse trains

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Aperture access processors, methods, systems, and instructions
- Patent number 12,333,325
- Issue date Jun 17, 2025
- Intel Corporation
- Barry E. Huntley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read cache memory
- Patent number 12,321,608
- Issue date Jun 3, 2025
- Micron Technology, Inc.
- Eugene Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refresh operation in multi-die memory
- Patent number 12,315,547
- Issue date May 27, 2025
- Matthew A. Prather
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller operable in data loop-back mode
- Patent number 12,314,113
- Issue date May 27, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reading from a mode register having different read and write timing
- Patent number RE50373
- Issue date Apr 8, 2025
- Sony Group Corporation
- Christopher E. Cox
Information Patent Grant
Semiconductor device including internal transmission path and stack...
- Patent number 12,260,929
- Issue date Mar 25, 2025
- SK Hynix Inc.
- Jinhyung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
System on chip for reducing wake-up time, method of operating same,...
- Patent number 12,248,355
- Issue date Mar 11, 2025
- Samsung Electronics Co., Ltd.
- Hee Dong Shin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with staggered request signal output
- Patent number 12,249,392
- Issue date Mar 11, 2025
- RAMBUS INC.
- Ian P. Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for addressing memory caches
- Patent number 12,222,871
- Issue date Feb 11, 2025
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module with data buffering
- Patent number 12,222,878
- Issue date Feb 11, 2025
- Netlist, Inc.
- Jefferey C. Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device for supporting command bus training mode and method o...
- Patent number 12,217,823
- Issue date Feb 4, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout for dual in-line memory to support 128-byte cache line proce...
- Patent number 12,211,577
- Issue date Jan 28, 2025
- Tachyum Ltd.
- Radoslav Danilak
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory buffer with data scrambling and error correction
- Patent number 12,205,669
- Issue date Jan 21, 2025
- RAMBUS INC.
- Christopher Haywood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controllers, systems, and methods supporting multiple reques...
- Patent number 12,198,780
- Issue date Jan 14, 2025
- RAMBUS INC.
- Richard E. Perego
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Algorithmic TCAM based ternary lookup
- Patent number 12,197,509
- Issue date Jan 14, 2025
- BAREFOOT NETWORKS, INC.
- Patrick Bosshart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, memory device, and method for multi-phase clock training
- Patent number 12,198,783
- Issue date Jan 14, 2025
- Samsung Electronics Co., Ltd.
- Taegook Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Technologies for dynamically managing resources in disaggregated ac...
- Patent number 12,191,987
- Issue date Jan 7, 2025
- Intel Corporation
- Francesc Guim Bernat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system and method of controlling a memory chip
- Patent number 12,154,659
- Issue date Nov 26, 2024
- Kioxia Corporation
- Shinya Koizumi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread scheduling control and memory splitting in a barrel processor
- Patent number 12,135,987
- Issue date Nov 5, 2024
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array reset read operation
- Patent number 12,119,051
- Issue date Oct 15, 2024
- Jeremy Binfet
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for memory power management and memory devices and systems...
- Patent number 12,112,830
- Issue date Oct 8, 2024
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component with adjustable core-to-interface data rate ratio
- Patent number 12,094,565
- Issue date Sep 17, 2024
- RAMBUS INC.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Grant
Banked memory architecture for multiple parallel datapath channels...
- Patent number 12,079,137
- Issue date Sep 3, 2024
- Microsoft Technology Licensing, LLC
- Stephen Sangho Youn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to control system updates and configuration changes via...
- Patent number 12,081,323
- Issue date Sep 3, 2024
- Intel Corporation
- Murugasamy K. Nachimuthu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal receiver with skew-tolerant strobe gating
- Patent number 12,062,413
- Issue date Aug 13, 2024
- RAMBUS INC.
- Andrew M. Fuller
- G11 - INFORMATION STORAGE
Information Patent Grant
Technologies for switching network traffic in a data center
- Patent number 12,040,889
- Issue date Jul 16, 2024
- Intel Corporation
- Matthew Adiletta
- B25 - HAND TOOLS PORTABLE POWER-DRIVEN TOOLS MANIPULATORS
Information Patent Grant
Mitigating interference between commands for different access reque...
- Patent number 12,026,107
- Issue date Jul 2, 2024
- PANASONIC AUTOMOTIVE SYSTEMS CO., LTD.
- Kazuhito Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for data movement
- Patent number 12,019,895
- Issue date Jun 25, 2024
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double data rate (DDR) memory controller apparatus and method
- Patent number 12,014,767
- Issue date Jun 18, 2024
- Uniquify, Inc.
- Mahesh Gopalan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic device test method and test device
- Patent number 11,994,558
- Issue date May 28, 2024
- Realtek Semiconductor Corp.
- Han-Yun Tsai
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACK...
- Publication number 20250201284
- Publication date Jun 19, 2025
- SK HYNIX INC.
- Jinhyung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Memory controllers, systems and methods supporting multiple request...
- Publication number 20250182801
- Publication date Jun 5, 2025
- Rambus Inc.
- Richard E. Perego
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ON CHIP FOR REDUCING WAKE-UP TIME, METHOD OF OPERATING SAME,...
- Publication number 20250165054
- Publication date May 22, 2025
- Samsung Electronics Co., Ltd.
- Hee Dong SHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACTIVATION FUNCTIONS FOR ARTIFICIAL INTELLIGENCE OPERATIONS
- Publication number 20250157509
- Publication date May 15, 2025
- Micron Technology, Inc.
- Alberto Troia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...
- Publication number 20250149076
- Publication date May 8, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUT FOR DUAL IN-LINE MEMORY TO SUPPORT 128-BYTE CACHE LINE PROCE...
- Publication number 20250131947
- Publication date Apr 24, 2025
- TACHYUM LTD.
- Radoslav DANILAK
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...
- Publication number 20250124959
- Publication date Apr 17, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP
- Publication number 20250095703
- Publication date Mar 20, 2025
- KIOXIA Corporation
- Shinya KOIZUMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALGORITHMIC TCAM BASED TERNARY LOOKUP
- Publication number 20250094497
- Publication date Mar 20, 2025
- Barefoot Networks, Inc.
- Patrick BOSSHART
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA ALIGNMENT FOR MEMORY
- Publication number 20250069631
- Publication date Feb 27, 2025
- Micron Technology, Inc.
- Martin Bach
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO
- Publication number 20250054525
- Publication date Feb 13, 2025
- Rambus Inc.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING
- Publication number 20240428835
- Publication date Dec 26, 2024
- Rambus Inc.
- Andrew M. Fuller
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES
- Publication number 20240402788
- Publication date Dec 5, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO CONTROL SYSTEM UPDATES AND CONFIGURATION CHANGES VIA...
- Publication number 20240372792
- Publication date Nov 7, 2024
- Intel Corporation
- MURUGASAMY K. NACHIMUTHU
- B25 - HAND TOOLS PORTABLE POWER-DRIVEN TOOLS MANIPULATORS
Information Patent Application
STACKED MEMORY DEVICES, SYSTEMS, AND METHODS
- Publication number 20240345737
- Publication date Oct 17, 2024
- Lodestar Licensing Group, LLC
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR DATA MOVEMENT
- Publication number 20240345756
- Publication date Oct 17, 2024
- Lodestar Licensing Group LLC
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20240345971
- Publication date Oct 17, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM WITH MULTIPLE STRIPING OF RAID GROUPS AND METHOD FOR...
- Publication number 20240302983
- Publication date Sep 12, 2024
- Innovations In Memory LLC
- Jon C.R. BENNETT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APERTURE ACCESS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
- Publication number 20240289160
- Publication date Aug 29, 2024
- Intel Corporation
- Barry E. Huntley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
- Publication number 20240290372
- Publication date Aug 29, 2024
- Uniquify, Inc.
- Mahesh GOPALAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT
- Publication number 20240282357
- Publication date Aug 22, 2024
- Rambus Inc.
- Ian Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatuses for Addressing Memory Caches
- Publication number 20240273032
- Publication date Aug 15, 2024
- Rambus Inc.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR APPARATUS INCLUDING A PLURALITY OF CLOCK PATHS AND A...
- Publication number 20240203469
- Publication date Jun 20, 2024
- SK HYNIX INC.
- Ji Hyo KANG
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE
- Publication number 20240203516
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACK...
- Publication number 20240194232
- Publication date Jun 13, 2024
- SK HYNIX INC.
- Jinhyung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES F...
- Publication number 20240184451
- Publication date Jun 6, 2024
- Lodestar Licensing Group LLC
- Timothy Hollis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEM
- Publication number 20240177754
- Publication date May 30, 2024
- SK HYNIX INC.
- Chang Kyun PARK
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
- Publication number 20240177747
- Publication date May 30, 2024
- Rambus Inc.
- Ian P. Shaeffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH OPERATION IN MULTI-DIE MEMORY
- Publication number 20240170035
- Publication date May 23, 2024
- Lodestar Licensing Group LLC
- Matthew A. Prather
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY BUFFER WITH DATA SCRAMBLING AND ERROR CORRECTION
- Publication number 20240161795
- Publication date May 16, 2024
- Rambus Inc.
- Christopher HAYWOOD
- G06 - COMPUTING CALCULATING COUNTING

for memories with random access ports synchronised on clock signal pulse trains

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Aperture access processors, methods, systems, and instructions

Read cache memory

Refresh operation in multi-die memory

Memory controller operable in data loop-back mode

Reading from a mode register having different read and write timing

Semiconductor device including internal transmission path and stack...

System on chip for reducing wake-up time, method of operating same,...

Memory controller with staggered request signal output

Methods and apparatuses for addressing memory caches

Memory module with data buffering

Memory device for supporting command bus training mode and method o...

Layout for dual in-line memory to support 128-byte cache line proce...

Memory buffer with data scrambling and error correction

Memory controllers, systems, and methods supporting multiple reques...

Algorithmic TCAM based ternary lookup

Apparatus, memory device, and method for multi-phase clock training

Technologies for dynamically managing resources in disaggregated ac...

Memory system and method of controlling a memory chip

Thread scheduling control and memory splitting in a barrel processor

Memory array reset read operation

Methods for memory power management and memory devices and systems...

Memory component with adjustable core-to-interface data rate ratio

Banked memory architecture for multiple parallel datapath channels...

Techniques to control system updates and configuration changes via...

Signal receiver with skew-tolerant strobe gating

Technologies for switching network traffic in a data center

Mitigating interference between commands for different access reque...

Apparatuses and methods for data movement

Double data rate (DDR) memory controller apparatus and method

Electronic device test method and test device

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACK...

Memory controllers, systems and methods supporting multiple request...

SYSTEM ON CHIP FOR REDUCING WAKE-UP TIME, METHOD OF OPERATING SAME,...

ACTIVATION FUNCTIONS FOR ARTIFICIAL INTELLIGENCE OPERATIONS

MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...

LAYOUT FOR DUAL IN-LINE MEMORY TO SUPPORT 128-BYTE CACHE LINE PROCE...

MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...

MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP

ALGORITHMIC TCAM BASED TERNARY LOOKUP

DATA ALIGNMENT FOR MEMORY

MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO

SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

TECHNIQUES TO CONTROL SYSTEM UPDATES AND CONFIGURATION CHANGES VIA...

STACKED MEMORY DEVICES, SYSTEMS, AND METHODS

APPARATUSES AND METHODS FOR DATA MOVEMENT

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

MEMORY SYSTEM WITH MULTIPLE STRIPING OF RAID GROUPS AND METHOD FOR...

APERTURE ACCESS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT

Methods and Apparatuses for Addressing Memory Caches

SEMICONDUCTOR APPARATUS INCLUDING A PLURALITY OF CLOCK PATHS AND A...

SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE

SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACK...

APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES F...

MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEM

MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT

REFRESH OPERATION IN MULTI-DIE MEMORY

MEMORY BUFFER WITH DATA SCRAMBLING AND ERROR CORRECTION