Claims
- 1. A method for renaming logical source registers to physical registers for a set of operations comprising the computer implemented steps of:
- providing first, second, and third physical source registers corresponding to first, second, and third logical source registers associated with first, second, and third operations, respectively;
- providing first, second, and third physical destination registers associated with said first, second, and third operations;
- comparing said second physical source register with said first physical destination register to identify a first match;
- bypassing said second physical source register with said first physical destination register in response to said first match;
- comparing said second logical source register with said first logical destination register to identify a second match;
- comparing said second logical source register with said second logical destination register to identify a first difference;
- simultaneously bypassing said third physical source register with said first physical destination register in response to said second match and said first difference.
- 2. The method of claim 1 further comprising the steps of:
- comparing said third logical source register with said second logical destination register to identify a third match; and
- bypassing said third physical source register with said second physical destination register in response to said third match.
- 3. An apparatus for renaming a set of logical source registers associated with a set of ordered computer operations to a corresponding set of physical registers, said set of ordered computer operations comprising a first, a second, and a third operation, each operation including at least one logical source register and at least one logical destination register, said apparatus comprising:
- an array memory indexed by first, second, and third logical source registers associated with said first, second, and third operations, said array memory providing corresponding first, second, and third physical source registers, respectively;
- allocation circuitry for allocating first, second, and third physical destination registers corresponding to said first, second, and third computer operations;
- first, second, and third comparators, said first comparator comparing a logical source register of said second operation with said first logical destination register, said second comparator comparing a logical source register of said third operation with said first logical destination register, and said third comparator comparing a logical source register of said third operation with said second logical destination register;
- a bypass mechanism coupled to said first, second, and third comparators for simultaneously bypassing said third physical source register with said second physical destination register in the event that said logical source register of said third operation matches said second logical destination register so that said logical source register of said third operation is renamed to said second physical destination register, said bypass mechanism also bypassing said second physical source register with said first physical destination register in the event that said logical source register of said second operation matches said first logical destination register.
- 4. The apparatus of claim 3 wherein said bypass mechanism further bypasses said third physical source register with said first physical destination register in the event that said logical source register of said third operation matches said first logical destination register and said logical source register of said third operation does not match said second logical destination register.
- 5. The apparatus of claim 3 further comprising a reorder buffer coupled to said allocation circuitry, said reorder buffer providing said first, second, and third physical registers.
Parent Case Info
This is a continuation of application Ser. No. 08/129,867, filed Sep. 30, 1993.
US Referenced Citations (7)
Non-Patent Literature Citations (2)
Entry |
Val Popescu, et al. entitled, "The Metaflow Architecture", IEEE Micro, Jun. 1991, pp. 10-13, 63-73. |
Mike Johnson, entitled, "Superscala Microprocessor Design", Advance Micro Devices, Prentice Hall Series in Innovative Technology, 1991, pp. 1-289. |
Continuations (1)
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Number |
Date |
Country |
Parent |
129867 |
Sep 1993 |
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