BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing an apparatus for designing a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 shows a hardware configuration of the apparatus for designing a semiconductor integrated circuit.
FIG. 3 shows a model circuit representing delay characteristics of a path circuit.
FIG. 4 is a graph showing Kp, Kp max and the Kp correction value with respect to a circuit parameter Kw.
FIG. 5 is a block diagram showing an apparatus for designing a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 6 is a block diagram showing an apparatus for designing a semiconductor integrated circuit according to a third embodiment of the present invention.
FIG. 7 is a block diagram showing a conventional static timing analysis apparatus.
FIG. 8 shows an output device provided in the apparatus for designing a semiconductor integrated circuit according to a fourth embodiment of the present invention.
FIG. 9 shows an output device provided in the apparatus for designing a semiconductor integrated circuit according to a fifth embodiment of the present invention.