Apparatus and methods for translating test vectors

Abstract

Apparatus and methods for translating test vectors between a format suitable for use with a standalone integrated circuit tester and a format suitable for use with an in-circuit tester are disclosed. Methods according to the invention include: providing a first test file in a first format that is suitable for use with the standalone integrated circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the in-circuit tester. Methods according to the invention also include: providing a first test file in a first format that is suitable for use with the in-circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the standalone integrated circuit tester. Apparatus according to the invention include computer-readable media having stored thereon computer-executable instructions for performing these methods.

Description

FIELD OF THE INVENTION

The present invention relates generally to integrated circuit (IC) testing. More particularly, the present invention relates to translating test vectors from a first format suitable for use with a standalone IC tester into a second format suitable for use with an in-circuit tester, and vice versa.

BACKGROUND OF THE INVENTION

During design and development, ICs, such as application specific ICs (ASICs), field programmable gate arrays (FPGAs), and so on, are routinely subjected to a series of tests, including standalone chip tests and in-circuit tests. A chip test typically tests all the logic within an individual IC using an input set of test vectors in a format suitable for use by the chip tester. One known chip tester is the Logic Master XL60, which is available from Integrated Measurement Systems. This tester uses, as input, a test file including test vectors in a proprietary format.

An in-circuit tester tests a completed printed circuit board assembly, which typically includes one or more ICs. The purpose of in-circuit testing is to verify that the assembly is free of manufacturing defects, such as solder shorts or opens, incorrect components, misoriented components, and so on. A typical in-circuit test assumes that the individual components that make up the assembly are defect free. The in-circuit tester uses a second set of test vectors in a format that differs, sometimes significantly, from the format of the test vectors used during chip testing. One such example is Hewlett-Packard Company's pattern conversion format (PCF).

In-circuit testing is also commonly referred to as ‘bed-of-nails’ testing. These nails make physical contact with routing traces on the printed circuit board, and can be used to drive stimuli to devices under test, and to receive responses to verify that all the device connections have been made. Typically, the stimuli used to test these device connections are generated programmatically from one of three types of files: 1) a device model for simple devices; 2) boundary scan device logic (BSDL) for large complicated devices with design-for-test; or 3) a device netlist for programmable devices. In all three cases an additional file that represents the printed circuit boards's topology or connection order is used to generate tests for each device.

The process described above is a common way to generate in-circuit tests for such devices. In some cases, however, the necessary inputs do not exist. For example, older chips that were designed before boundary scan was popular were too complicated to be represented by a model, and most likely used a non-standard netlist format. Quite often, modern designs have this same problem, as short cuts are taken to save time or money. Generating in-circuit tests for these devices has posed a unique challenge. In many cases the solution has been simply not to test the device once the assembly is complete. Obviously, this can create reliability and system test yield problems.

Typically, millions of test vectors must be developed to test an IC at the chip test level. Many thousands of these represent connections that will be tested again during in-circuit testing. Consequently, once a chip test has been successfully conducted, and the test vectors have been proven, it would be desirable to reuse as much as possible of this subset of test vectors in conducting the in-circuit test. Because of the very different formats required by the above-described chip test and in-circuit test tools, however, this subset is frequently unusable. Similarly, if an in-circuit test fails, it is sometimes necessary to verify that the test vectors being used for the in-circuit test are accurate. Under such circumstances, it would be desirable to use the in-circuit test vectors in a standalone chip test to determine whether the fault is due to the chip, or to the in-circuit test vectors. Again, due to the varying formats of the two sets of test vectors, the in-circuit test vectors frequently cannot be used in the chip test environment.

U.S. Pat. No. 5,778,004, issued in the names of Jennion, et al. (“Jennion '004”), discloses an IC test environment which includes at least two test configurations where each test configuration employs a different test vector format. Jennion '004 discloses apparatus and methods for translating a first set of test vectors having a first format used in a first test configuration into a second set of test vectors in a second format to be used in a second test configuration. The system disclosed therein includes means for receiving user selections representing at least one of a desired set of signals and a desired range of test vectors to be processed from the first set of test vectors; means for extracting data related to the user selections from the first set of test vectors; and means for converting the extracted data into the second set of test vectors in the second format.

The prior art does not seem to disclose a vector translator that provides a method for translating test vectors from a format suitable for use with a chip tester (such as the XL60 format) into a format suitable for use with an in-circuit tester, and vice versa. Thus, there is a need in the art for such a vector translator.

SUMMARY OF THE INVENTION

The present invention satisfies these needs in the art by providing apparatus and methods for translating test vectors from a format suitable for use with a chip tester into a format suitable for use with an in-circuit tester, as well as apparatus and methods for translating test vectors from a format suitable for use with an in-circuit tester into a format suitable for use with a chip tester.

Methods for translating test vectors from a format suitable for use with an integrated circuit tester into a format suitable for use with an in-circuit tester include providing a first test file in a first format that is suitable for use with the integrated circuit tester for standalone testing of an integrated circuit. The first test file is then translated into a second test file in a second format. The second format is suitable for use with the in-circuit tester for in-circuit testing of the integrated circuit. Preferably, the format of the first file is IMS format and file includes a set of test vectors for standalone testing of the integrated circuit, as well as a set of pin definitions that define pins of the integrated circuit. The format of the second file is preferably PCF.

The first test file can be provided, at least in part, by providing a complete test file that includes test vectors for testing logic within the integrated circuit, and selecting a subset of the test vectors included in the complete test file. The selected subset can then be included in the first test file. The first test file can be translated into the second test file by identifying in the first file test vector data in the first format, and writing to the second file test vector data in the second format that corresponds to the test vector data in the first format. The translation can also include identifying in the first file pin information in the first format. Based on the pin information, pin assignment statements, pin definitions, and pin functionality statements can be written to the second file in the second format.

Similarly, methods for translating test vectors from a format suitable for use with an in-circuit tester into a format suitable for use with an integrated circuit tester include providing a first test file in a first format that is suitable for use with the in-circuit tester for in-circuit testing of an integrated circuit. The first test file is then translated into a second test file in a second format. The second format is suitable for use with the integrated circuit tester for standalone testing of the integrated circuit. Preferably, the first file is in PCF, and the second file is in IMS format.

Apparatus according to the invention include computer-readable media having stored thereon computer-executable instructions for performing these methods.

The methods and apparatus of the present invention can be used in a test evaluation method to verify that a device being subjected to an in-circuit test is not flawed. The test evaluation method comprises performing an in-circuit test on a device under test (DUT) using an in-circuit test file in a format suitable for input into an in-circuit tester. If the DUT fails the in-circuit test, then the in-circuit test file is translated into an integrated circuit test file in a format that is suitable for input into a standalone integrated circuit tester. A standalone integrated circuit test is performed on a golden device using the integrated circuit test file. A golden device is a device of the kind under test that has been proven to work properly. If the golden device passes the standalone integrated circuit test, then it can be reasonably concluded that the DUT is not flawed. The invention thus provides a mechanism for verifying (with a reasonable degree of certainty) that a DUT is not flawed despite the fact that it may have failed an in-circuit test. This could indicate that, for example, the circuit board itself is flawed. Other aspects of the present invention are described below. If the golden device fails the standalone integrated circuit test, then it can be reasonably concluded that the in-circuit test file is flawed, or that the in-circuit test file introduced certain tests that were not conducted during previous standalone integrated circuit testing on the golden device.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing summary, as well as the following detailed description of the preferred embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there is shown in the drawings an embodiment that is presently preferred, it being understood, however, that the invention is not limited to the specific apparatus and methods disclosed.

FIG. 1 is a high level flow diagram of a presently preferred embodiment of the invention.

FIGS. 2A and 2B depict an exemplary hybrid test environment for which the apparatus and methods of the present invention are particularly suitable.

FIGS. 3A and 3B illustrate both the chip test generation process, and the in-circuit test generation process.

FIGS. 4A-4J provide a flowchart of a presently preferred process in accordance with the present invention.

FIG. 5 provides a flowchart of a method for debugging an in-circuit test using a vector translator according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Overview

The present invention provides apparatus and methods for translating test vectors from a format suitable for use with a chip tester (such as, for example, the XL60 tester) into a format suitable for use with an in-circuit tester (for example, the HP tester) and vice versa. In the case of chip tests, the test vectors can be verified initially against a so-called “golden device,” i.e., a device of the kind under test that has been proven to work properly. These proven vectors then can be converted into a format suitable for in-circuit test execution. Conversely, an existing in-circuit test for a particular device can be extracted and converted into a chip level test.

For purposes of the following description, the test vector format suitable for use with the chip tester will be referred to as “IMS format,” while the test vector format suitable for use with the in-circuit tester will be referred to as “PCF.” It should be understood, however, that the present invention is equally applicable to test configurations using other test vector formats.

An exemplary IMS input file is included as Appendix A hereof. As shown, the exemplary IMS file includes a set of configuration statements (shown as “Config” in Appendix A) that describe the resources available on the test platform (e.g., data cards). Preferably, the file also includes a set of resource statements (shown as “Resource” in Appendix A). The resource statements assign specific tester resources to specific input/output pins of the device under test. Note that, in IMS format, “force” refers to a tester resource that sends data to an input pin of the device under test. Conversely, “compare” refers to a tester resource that receives data from an output pin of the device under test, and compares the received data against expected data. If the received data differs from the expected data, an error is flagged. The IMS test file also includes a set of test vectors. For each signal name provided in the resource statements, there should be a corresponding column of data in each test vector. In the exemplary file shown in Appendix A, as one reads down the list of resource statements, one can locate the corresponding data columns by moving left to right in the vectors. If the device signal or pin is input only, a 1 or 0 is provided in the column corresponding to that pin. Data shown as “z” in Appendix A represents an “input don't care,” i.e., no specific input signal needs to be sent to this pin. Typically, this is used for bi-directional pins where the input is irrelevant to the test. Finally, data shown as “x” in Appendix A represents a “compare don't care,” i.e., the pin's output value is irrelevant to the test.

An exemplary PCF input file is included as Appendix B hereof. As shown, the exemplary PCF file includes a set of assignment statements (shown as “assign” in Appendix B). The assign statements assign specific tester resources to specific input/output pins of the device under test. Preferably, the PCF file also includes one or more data order statements (shown as “pcf_order” in Appendix B). The data order statement defines the structure of the columns of the test vectors that follow. Each test vector includes the actual data corresponding to the device as shown in the pcf_order satement. That is, as one reads across the resources provided in the pcf_order statement, one also reads across the test vectors to determine the actual datum corresponding to that resource. The notations “1,” “0,” “z,” and “x” represent the same data as discussed above in connection with the IMS test file.

The present invention is useful in several ways. First, it provides a user with a convenient way to create in-circuit tests on a chip tester such as the LogicMaster XL60. It is much easier for a developer to create and debug a test for a stand-alone device than it is to create the test for a device mounted in the board. Second, the invention is useful for debugging non-working in-circuit tests, since it allows a user to isolate a certain failing device and then to test it independently from the board to find the cause of a problem.

Preferably, the present invention is implemented in software, in the C programming language. The program can be stored as a set of computer executable instructions on a disk or any other computer readable data storage medium. from which the program can be downloaded or executed. It should be understood, however, that the invention is in no way limited to a software program, nor is its implementation limited to a “C” program.

A high level flow diagram of a preferred embodiment of the present invention is illustrated in FIG. 1 . The program 10 can accept either IMS or PCF test files as input, and produces either PCF or IMS test files, respectively, as output. The input “Test File” 12 and the output “New Test File” 14 can be in either of the two formats, depending on which direction is desired. The in-circuit test platform supplies the “Constraint File” 16 , which describes tester resources and how tester drivers are allocated. Each of these files is described in greater detail below in connection with FIGS. 4A-4J .

The program 10 also accepts user input 18 , and then preprocesses input data from Test File 12 , Constraint File 16 , and user input 18 . As shown in block 17 , the program extracts data, such as device settings, pin names, and pin data, from the test file, and creates an internal database to store the extracted data. After the database is created, the program writes the settings information to New Test File 14 . As shown in block 19 , the program uses the database to translate the input test vectors into the desired format by converting from 1 vector/clock to 2 vectors/clock, if necessary, and then writing the translated vectors to New Test File 14 . Sometimes, it is necessary to convert the vectors from 1 vector/clock to 2 vectors/clock, because IMS automatically understands whether one or two vectors per clock is required, while, in PCF, it must be specifically indicated whether one or two vectors per clock is required.

Exemplary Test Environment

FIGS. 2A and 2B depict an exemplary hybrid test environment for which the apparatus and methods of the present invention are particularly suitable. In FIG. 2A , a chip test configuration is depicted including a host device 20 , such as a personal computer (PC) or workstation, that can be used for generating vectors in IMS format for use with a chip tester 22 . It should be noted that the connection 21 between host device 20 and chip tester 22 can be, for example, an Ethernet connection, a general purpose interface bus (GPIB) connection, or the like. As shown, chip tester 22 includes a circuit board 24 , on which resides the IC 26 under test. Circuit board 24 provides various connections between chip tester 22 and IC 26 .

In this particular illustration, a second host device 28 is connected, via a GPIB connection 27 , for example, to chip tester 22 . Preferably, software implemented apparatus embodying the present invention executes on host device 28 , where it communicates with chip tester 22 to extract IMS vectors, process them, and produce PCF vectors. The user interface with the present invention and the extraction and processing of the IMS vectors is described in detail below.

Once the PCF vectors are produced, they are downloaded to in-circuit tester 30 . In the configuration shown in FIGS. 2A and 2B , this is accomplished by storing the PCF vectors on a floppy disk (not shown), and carrying the floppy disk to a third host device 32 that is connected, via a GPIB connection 31 , for example, to in-circuit tester 30 . It should be understood, however, that other suitable techniques for transferring this data are also contemplated. For example, host device 28 can be connected directly to in-circuit tester 30 , or via a local area network (LAN) connection to host device 32 . Basically, any suitable interconnections that provide for the necessary transfer of data can be used. Once the PCF vectors are loaded onto in-circuit tester 30 , the in-circuit tests can be run and, with the aid of diagnostic equipment (not shown), various signals can be monitored, captured, and/or analyzed.

It should be understood that the configuration depicted in FIGS. 2A and 2B can also be used for translating PCF vectors suitable for use with in-circuit tester 30 into IMS vectors suitable for use with chip tester 22 , and for loading the output IMS file onto chip tester 22 .

FIGS. 3A and 3B illustrate both the chip test generation process and the in-circuit test generation process. One purpose of the present invention is to bridge the gap between chip testers and in-circuit testers, thereby allowing for reuse of test data. It provides a user with a convenient way to port chip tests into the in-circuit test environment. Similarly, it allows for in-circuit tests to be converted into standalone chip tests and used on a chip tester. It is much easier for an IC test engineer to create and debug a test for a standalone device than to create the test for a device mounted in the board. When debugging a device within the in-circuit test environment, the developer should consider the effects caused by other board logic and the test environment itself. This program is particularly suitable for debugging in-circuit tests, as it allows a user to isolate a particular device and test it independently of the aforementioned complications.

The purpose of each test platform is, in general, very different. In some ways, however, they are related. Chip testers, for example, are typically expected to test all the internal logic of the device under test (DUT), looking for shorts, opens, and other defects at the sub-micron level. The amount of test data to do this is enormous for today's designs, and is very complicated to generate. An in-circuit tester looks for similar types of defects, but at a device interconnect level. It is expected to find these defects when they are introduced during the board's assembly in the manufacturing environment. This test data set is also very large and complex, as it has to account for a large number of unique devices made of different technologies with different logical design methodologies.

FIG. 3A shows possible test data origins for a chip tester. The chip tester can accept input data from deterministic algorithms, functional simulator output, programmable device files, and also semi-manually generated data. The chip tester then uses the input tester pattern data to stimulate the device under test (DUT).

Similarly, FIG. 3B shows possible test data origins for an in-circuit tester. The in-circuit tester can accept input data from schematics and data sheets, BSDL, simple I/O device models, programmable device data, and manually or semi-manually generated data. The in-circuit tester then uses the input tester pattern data to stimulate the DUT. Typically, the in-circuit tester tests a populated PC board comprising the device under test (DUT) and, in general, a plurality of additional ICs.

Methods for Translating Test Vectors

FIGS. 4A-4J provide a flowchart of a preferred embodiment of the present invention, which, as discussed above, has been implemented in software, in the C programming language. Several advantages of the present invention should be readily apparent to those skilled in the art. For example, it supplies an alternative test data origin for device designs that fall outside of the normal in-circuit test development process. Examples of this include tests to be conducted on proprietary custom ASICs or non-standard FPGAs. Second, it supports the portation of in-circuit tests to a chip test platform for verification or debug. In case of an ICT failure, this method provides an opportunity to isolate a test for a particular device and reproduce the failure in an isolated environment on the chip tester. These techniques can be invaluable in some cases and can save enormous amounts of time and resources. Third, it enables development of specific tests to supplement existing test coverage. Even when the desired test approach is taken, it is common for holes in test coverage to occur. This program provides a vehicle to increase the effective coverage of weak tests. Fourth, it is suitable for generating level 3 functional tests for some devices. That is, there are cases when in-circuit tests are required to test all the internal logic of a device within the assembly. This can be done relatively easily where functional tests already exist from a previous stage of development.

The invention provides a unique ability to take a proven chip test of any type (e.g., parametric, boundary, built-in self-test, etc.) directly from a chip tester and generate an in-circuit test. It also provides the ability to add additional device tests to increase coverage of known weak test coverage areas (either specific pins or logic areas). It provides the ability to capture non-working in-circuit tests, and to create an environment to isolate the chip from the board. This allows easy manipulation of voltage, sample and clock rate, and other parameters that cannot be easily manipulated in board environment.

A preferred embodiment of the present invention will now be described in detail with reference to the flowcharts shown in FIGS. 4A-4J . As shown in FIG. 4A , at step 102 , the program initially presents a user with a user interface via which the user can identify the type of conversion the program is to perform. If, at step 102 , the user elects to convert an IMS file to PCF, the program performs the conversion at step 104 . FIGS. 4B-4E provide a detailed flowchart of a method for converting IMS files to PCF. The user can also choose, at step 102 , to convert a PCF file to IMS. If the user selects this option, the program performs the conversion at step 106 . FIGS. 4F-4H provide a detailed flowchart of a method for converting PCF files to IMS. In some instances (e.g., during test debug), the user might wish to convert the test vectors from 1 clock/vector to 2 clocks/vector. The user can select this option, at step 102 , in which case the program will perform this conversion at step 108 . FIGS. 4I and 4J provide a detailed flowchart of a method for converting test vectors from 1 clock/vector to 2 clocks/vector.

Translation of IMS vectors to PCF

FIGS. 4B-4E provide a detailed flowchart of a method for converting IMS files to PCF. An exemplary IMS input file is included as Appendix A hereof. First, a parameter file is opened at step 110 . Preferably, the parameter file includes predefined pin information such as a generic name for the pin, an IMS resource name, a package name, and so on. If the parameter file is missing, the user is prompted at step 112 to input the required parameter information. Otherwise, the parameter information is read from the file at step 114 . Once the parameter information is obtained, the IMS file that is to be translated into PCF is opened at step 116 . If the IMS file cannot be found, or cannot be opened for any reason, the program exits at step 118 .

If the IMS file is opened at step 116 , the program loops through the IMS file, at step 120 , to find and extract the relevant pin information. The pin information is stored in the IMS file as four word strings. Thus, the first step in loop 120 is to divide the string into four words, and then to read the resource information from the IMS file. The resource information is stored in an appropriate data structure.

If any comments are to be written to the PCF file, they are written at step 126 . Thereafter, a number of functions are performed to generate the required data in the PCF file. At step 128 , bidirectional pins are found by searching for pins defined twice (i.e., as both “force” and “compare”). This information is then stored in a two-dimensional array called a “group mask.” At step 130 , assignment statements are written to the PCF file. The information in the group mask is used to ensure that bidirectional pins are assigned only once. Preferably, the power pin is not assigned because, in a preferred embodiment, the user provides this assignment.

At step 132 , the pin definitions are written to the PCF file. At this point, strings are created that list all groups of the same type (i.e., Input, Output, Bidirectional, and Nondigital groups. First, all “Force” (i.e., input) groups are listed in an input buffer string. Next, all “Compare” (i.e., output) groups are listed in an output buffer string. Third, all “Nondigital” (i.e., unused) groups are listed in a nondigital string buffer and, finally, all “Bidirectional” groups are listed in a bidirectional string buffer.

At step 134 , a filename is created for the PCF test file, preferably by changing the extension of the input filename from “*.tst” to “*.pcf.” Pin assignment statements and pin functionality statements are written to the output PCF file at step 136 . The pin functionality statements include whether the pin is an input pin, an output pin, or a bidirectional pin.

Finally, at step 138 , the data is converted. FIG. 4C provides a detailed flowchart for converting the data. First, program variables are created and initialized at step 140 . At step 142 , a pin mask is created to store certain information in a two-dimensional array. Preferably, the pin mask includes pin type, i.e., whether the pin is input (force), output (compare), bidirectional, or nondigital. The pin mask also preferably includes a pointer to group information in the group mask, and an indicator of the total number of pins in the current group.

A copy of the pin mask is then created at step 144 . This allows the pin mask to be changed, and then returned to its original state for every vector. At step 146 , the formatting of bidirectional pins in IMS is addressed. FIG. 4D provides a detailed flowchart for formatting bidirectional pins in IMS. In PCF, pins can be defined as bidirectional, while in IMS format, pins can be only “force” (i.e., input), or “compare” (i.e., output). This function locates each bidirectional pin and determines whether, for the current test, the pin is being used as an input pin or an output pin. At step 174 , an index variable for the current pin is established. An index is needed to access information about current pin in the pin mask. At step 176 , the pin mask index is found for the first pin in the bidirectional group (i.e., compare group if this is force, and force if this is compare). The pin is located at step 178 . At step 180 , for bidirectional pins used as outputs, only the Compare Group is written to the output test file, while the Force Group is ignored. Similarly, at step 182 , for bidirectional pins used as inputs, only the Force Group is written, while the Compare Group is ignored.

Returning to FIG. 4C , at step 148 , the first vector in the IMS file is found. If no vector is found, then the program exits at step 150 . If the first vector is found at step 148 , then, at step 152 , the program loops through the IMS file to perform the appropriate conversion, according to the information stored in the pin mask, for every character of every IMS vector. For each vector, any LOOP or REPEAT instructions or comments are isolated at step 154 . LOOP or REPEAT instructions or comments indicate the number of times to execute a loop. At step 156 , isolated instructions are executed, while isolated comments are placed in a comment field at the end of the corresponding PCF vector. At step 158 , the PCF vector is written to the output PCF file.

FIG. 4E provides a detailed flowchart for writing a PCF vector to a PCF file. For each IMS vector in the input IMS file, two PCF vectors are written to the output PCF file. The order in which the two vectors are written depends on the clock being used. A determination is made as to what type of clock is to be used at step 208 . If the clock type is “R1,” (return to 1) then, at step 210 , the first of the two vectors is written with a “1” for clock data, while the second is written with a “0” for clock data. If the clock type is “RZ,” then, at step 212 , the first vector is written with a “0” for clock data, while the second is written with a “1” for clock data.

Once all of the vector data has been converted from IMS format into PCF, and written to the output PCF file, the program exits at step 160 as shown in FIG. 4 C.

Translation of PCF Vectors to IMS

FIG. 4F provides a detailed flowchart of a method for converting PCF files to IMS format. An exemplary PCF input file is included as Appendix B hereof. At step 226 , the program asks the user for the filename of the input PCF test file. The program also requests the filename of the file that includes the pin descriptions of the pins of the IC under test, and the number of lines in the input PCF file that represent a single PCF vector. At step 228 , the input files are opened. If any of the required files is missing, or for any reason cannot be opened, the program exits at step 230 . At step 234 , a filename is created for the output IMS test file by changing the extension of the input PCF filename from “*.pcf” to “*.tst.”

At step 236 , internal data structures for the IMS vectors are created based on the PCF Order statement in the input PCF file. FIG. 4G provides the details of creating these data structures. First, the PCF order statement is read from the input test file at step 256 . An array of data structures is created with an element for every IMS group. At step 262 , the group name for the new group is determined, and resources for the new group are allocated. If, for some reason, step 262 goes awry, the program exits at step 264 . Otherwise, the new group is saved, at step 266 , in newly allocated space in a database.

Group assignments are made at step 238 . First, a group assignment statement (i.e., “assign”) is located in the PCF test file. Preferably, this statement assigns listed pins to a group name. After the group assignment statement is found, a check is made to determine if the group listed in the group assignment statement exists in the database. If the group exists, the program copies all pins to pin name variables in the appropriate structures in the database.

At step 240 , a search is conducted for group type statements such as input, output, or bidirectional. If the group type is “input,” then “input” is written into a “pin type” variable of the corresponding structure in the database. This procedure is repeated for every group found. Similarly, if the group type is “output,” then “output” is written into the pin type variable of the corresponding structure in the database. Again, this procedure is repeated for every group found in the current line. Finally, if the group is “bidirectional,” then the group is first set to “input” in the database. Then, a copy of the group is placed at the end of the resource array, with a modified name and pin type set to “output.”

At step 242 , pin information is read from the input parameter file. First, the line in the parameter file that includes the pin information is located. Preferably, the user inputs this information, or it is included in a separate file, such as the input PCF test file. Once it is read, the pin information is saved in an appropriate structure in the database.

Next, a pin mask is generated at step 244 . First, the pin mask is initialized with pin order and pin type, and then it is initialized for bidirectional pins. Next, constraint data is read from the parameter file or the input PCF test file. Preferably, a constraint data section is added to the input PCF test file manually before the file is input to the translation program. A copy of the pin mask is generated, at step 246 , and filled with the constraint data.

The groups are then checked, at step 248 , to verify that each group has at least one pin defined, and that every pin has at least three names defined. If an error is found at this step, the program calls a general error handler. If no errors are found at step 248 , then, at step 250 , the pin information stored in the database is used to write IMS settings to the output IMS file.

The IMS data is written to the output IMS file at step 252 . FIG. 4H provides a detailed flowchart for this function. At step 298 , the program loops through the PCF vectors, converting each into a corresponding IMS vector. As discussed above, IMS can recognize whether one or two clocks per vector are required. However, it has been found during test debug that, sometimes, more than 2 clocks/vector is required. If this is the case, it is preferred that the user simply input the required number of clocks per vector. At step 300 , this user input (i.e., number of lines per vector) is taken and valid lines are appended to the output file, thereby creating enough IMS vectors to satisfy the required number of clocks/vector. The PCF vector strings are read at step 302 . Every character of the PCF vector string is read and, if the current character is valid, the program converts the character from PCF to IMS format using information stored in the pin mask.

Once all of the vector data has been converted from PCF into IMS format, and written to the output IMS file, the program exits at step 254 as shown in FIG. 4 F.

Vector Clock Conversion

FIG. 4I provides a detailed flowchart of a method for converting test vectors from 1 clock/vector to 2 clocks/vector. At step 214 , the program accepts the filename of the input IMS test file to be processed, as well as a filename for the new output test file to be generated. At step 216 , resource information is read from the IMS file, and stored in an appropriate data structure. At step 218 , the program prompts the user for the name of the clock to be used in the vector conversion. A temporary copy of the test file is made, at step 220 , so that the temporary file can then be updated, without affecting the original input file. At step 222 , the program loops through the IMS test file, reading each vector from the file and then processing it at step 224 .

FIG. 4J provides a detailed flowchart of the processing performed for each vector. At step 312 , the program loops through the vector to search for the vector's comment section. If a comment section is found, the program determines, at step 314 , whether an instruction, such as a REPEAT or LOOP instruction, is found in the comment section. If so, the instruction is stored in an appropriate data structure. At step 318 , all vectors that are part of the loop are written to the temporary file. First, the column in the data vector where the selected clock is defined is found for each vector. Then, the vectors are written to the temporary file with 2 vectors/clock instead of 1 vector/clock. After all of the vectors have been written to the temporary file, the vectors are written, at step 322 , from the temporary file to the test file for the number of times defined in the loop statement.

Methods for Evaluating In-Circuit Tests Using Vector Translation

Throughout the process of in-circuit testing, it is often the case that an in-circuit test performed on a particular device under test (DUT) will fail. Frequently, the test operator will be unsure whether the test failed because the DUT is flawed or whether the board design is flawed. According to another aspect of the present invention, a test operator can use the vector translator described above to determine whether the DUT is flawed.

FIG. 5 provides a flowchart of a method for verifying an in-circuit test using a vector translator according to the present invention. At step 402 an in-circuit test file (such as described above) is generated in a format suitable for use with an in-circuit tester. At step 404 , the in-circuit test file is used as input to the in-circuit tester to perform an in-circuit test on a device under test (DUT). The test operator then determines, at step 406 , whether the in-circuit test is successful. If so, the test operator can reasonably conclude that neither the DUT nor the in-circuit test file is flawed.

If, on the other hand, the test operator determines at step 406 that the in-circuit test failed, the test operator cannot be sure whether it is the DUT, or some other aspect of the in-circuit test, that caused the failure. According to the present invention, however, the test operator can use a vector translator to verify that the DUT is not flawed.

To perform this analysis, the in-circuit test file is translated, at step 408 , using the methods and apparatus described in detail above, into an IC test file in a format that is suitable for use with a standalone integrated circuit tester. The IC test file is then input into a standalone integrated circuit tester that has been set up to test a golden device, i.e., a device of the kind under test that has been proven to work properly. The operator can then determine, at step 412 , whether the standalone IC test against the golden device is successful.

If the operator determines, at step 412 , that the test against the golden device is successful, then the operator can reasonably conclude, at step 416 , that the DUT works properly. Similarly, the operator can conclude that something else in the in-circuit test is flawed (e.g., the board design). If, however, the operator determines, at step 412 , that the test against the golden device is not successful, further investigation is necessary to pinpoint whether it is the DUT, the in-circuit test file, the board design, or some other aspect of the in-circuit test that is flawed.

Thus there have been described apparatus and methods for translating test vectors between a format suitable for use with a standalone integrated circuit tester and a format suitable for use with an in-circuit tester. Those skilled in the art will appreciate that numerous changes and modifications may be made to the preferred embodiments of the invention and that such changes and modifications may be made without departing from the spirit of the invention. It is therefore intended that the appended claims cover all such equivalent variations as fall within the true spirit and scope of the invention.

Claims

1. A method for translating test vectors from a format suitable for use with an integrated circuit tester into a format suitable for use with an in-circuit tester, comprising:providing a first test file in a first format that is suitable for use with the integrated circuit tester for standalone testing of an integrated circuit; translating the first test file into a second test file in a second format that is suitable for use with the in-circuit tester for in-circuit testing of the integrated circuit, comprising the steps of: identifying in the first file, test vector data in the first format; identifying in the first file, pin information in the first format, writing to the second file, test vector data in the second format, the test vector data in the second format corresponding to the test vector data in the first format; writing to the second file, a plurality of pin data in the second format, the plurality of pin data based on the pin information.

2. The method of claim 1, wherein the first test file includes a set of test vectors for standalone testing of the integrated circuit.

3. The method of claim 1, wherein the first test file includes a set of pin definitions that define pins of the integrated circuit.

4. The method of claim 1, wherein the first test file is provided, at least in part, byproviding a complete test file that includes test vectors for testing logic within the integrated circuit; selecting a subset of the test vectors included in the complete test file; and including the selected subset in the first test file.

5. The method of claim 1, wherein the plurality of pin data includes pin assignment statements, pin definitions, and pin functionality statements.

6. The method of claim 1, wherein the first format is IMS format.

7. The method of claim 1, wherein the second format is pattern conversion format.

8. A method for translating test vectors from a format suitable for use with an in-circuit tester into a format suitable for use with an integrated circuit tester, comprising:providing a first test file in a first format that is suitable for use with the in-circuit tester for in-circuit testing of an integrated circuit; translating the first test file into a second test file in a second format that is suitable for use with the integrated circuit tester for standalone testing of the integrated circuit, comprising the steps of: identifying in the first file, test vector data in the first format; identifying in the first file, pin information in the first format; writing to the second file, test vector data in the second format, the test vector data in the second format corresponding to the test vector data in the first format; writing to the second file, a plurality of pin data in the second format, the plurality of pin data based on the pin information.

9. The method of claim 8, wherein the first test file includes a set of test vectors for in-circuit testing of the integrated circuit.

10. The method of claim 8, wherein the first test file includes a set of pin definitions that define pins of the integrated circuit.

11. The method of claim 8, wherein the first test file is provided, at least in part, byproviding a complete test file that includes test vectors for testing the integrated circuit in a completed printed circuit board assembly; selecting a subset of the test vectors included in the complete test file; and including the selected subset in the first test file.

12. The method of claim 8, wherein the plurality of pin data includes pin assignment statements, pin definitions, and pin functionally statements.

13. The method of claim 8, wherein the first format is pattern conversion format.

14. The method of claim 8, wherein the second format is IMS format.

15. A computer-readable medium having stored thereon computer-executable instructions for performing a method comprising:providing a first test file in a first format that is suitable for use with the integrated circuit tester for standalone testing of an integrated circuit; translating the first test file into a second test file in a second format that is suitable for use with the in-circuit tester for in-circuit testing of the integrated circuit, comprising the steps of: identifying in the first file, test vector data in the first format; identifying in the first file, pin information in the first format; writing to the second file, test vector data in the second format, the test vector data in the second format corresponding to the test vector data in the first format; writing to the second file, a plurality of pin data in the second format, the plurality of pin data based on the pin information.

16. A computer-readable medium having stored thereon computer-executable instructions for performing a method comprising:providing a first test file in a first format that is suitable for use with the in-circuit tester for in-circuit testing of an integrated circuit; translating the first test file into a second test file in a second format that is suitable for use with the integrated circuit tester for standalone testing of the integrated circuit, comprising the steps of: identifying in the first file, test vector data in the first format; identifying in the first file, pin information in the first format; writing to the second file, test vector data in the second format, the test vector data in the second format corresponding to the test vector data in the first format; writing to the second file, a plurality of pin data in the second format, the plurality of pin data based on the pin information.