Patent Application
20050010886
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. P2002-313172, filed on Oct. 28, 2002; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The invention relates to a delay fault test of a semiconductor integrated circuit. More particularly, the invention relates to a method of generating a test vector for a delay fault test and to a method of analyzing a delay fault in a semiconductor integrated circuit which has failed in a delay fault test.
2. Description of the Related Art
Verification of functions and timing in a semiconductor integrated circuit, mainly, in a logic circuit product is performed by simulation. A test vector used in the simulation is used in a test for analysis of timing in a test of the semiconductor integrated circuit. Moreover, automatic generation of a test vector for the delay fault test is executed in order to activate a critical path which has been identified by the timing analysis.
In the verification of timing in the semiconductor integrated circuit, confirmation is made as to whether delays in signals on each path breaches a timing at a target operation frequency. Since a path with a large signal delay is assumed to easily breach timing and timing verification of a path is executed for the path with a large signal delay, there is a case that object paths to be verified are centered on specific circuit blocks and paths which have breached timing are centered on specific circuit blocks. Moreover, there is a case that test vectors for delay fault tests exist only in specific regions in the semiconductor integrated circuit.
On the other hand, there is dispersion of size and density in manufacturing of a semiconductor integrated circuit. Also, there is structural scattering in the semiconductor integrated circuit. The structural scattering may occur that a path, which is assumed at verification of timing during a design stage to easily breach timing, does not necessarily become an actual breach path, after the semiconductor integrated circuit is actually manufactured. The timing breach is generated on another path in some cases.
Accordingly, there have been requirements to execute the delay fault test on a path which is selected so that the path is distributed all over the area of the semiconductor integrated circuit. However, no apparatus is available which generates a test vector by which a specific region is tested by designating the specific region. Such apparatus is needed to satisfy the requirements, on the semiconductor integrated circuit.
The delay fault analysis of paths on the semiconductor integrated circuit is examined, using a path with a delay fault test, to determine what cell has the delay fault in a plurality of cells forming a path with a delay fault. There has been no apparatus which generates a test vector by which a specific region is tested by designating the specific region, which apparatus is needed to execute the above examination, on the semiconductor integrated circuit.
An aspect of the present invention inheres in an apparatus for generating a test vector of a semiconductor integrated circuit according to embodiments of the present invention. The apparatus includes a retrieval-condition designation section designating a retrieval condition configured to select a path on which a signal can be transmitted in the semiconductor integrated circuit, a path-list generation section executing a timing analysis of the semiconductor integrated circuit based on circuit information of the semiconductor integrated circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis, a test-vector generation section generating a test vector configured to test a path delay fault of the semiconductor integrated circuit based on the path list, an ending-condition designation section designating an ending condition configured to end generation of the test vector when the path in the path list for the test vector is distributed over the semiconductor integrated circuit, and an ending-condition determination on judgment section stopping generation of the path list when the ending condition is satisfied.
Another aspect of the present invention inheres in an apparatus for debugging an failure of a semiconductor integrated circuit according to embodiments of the present invention. The apparatus includes a cell-list generation section generating a list of cells composing a path in the semiconductor integrated circuit with a delay fault based on a test result of whether the delay fault is generated on the path, a retrieval-condition designation section designating a retrieval condition configured to retrieve a fault-cell searching path, which includes a part of the path with the delay fault, a path-list generation section for fault-cell searching, which retrieves the fault-cell searching path based on the retrieval condition, and generates a fault-cell searching path list in which cells composing the retrieved fault-cell searching path are put in an order of transmitting a signal, a test-vector generation section for fault-cell searching, which generates a test vector based on the fault-cell searching path list, an ending-condition designation section designating an ending condition configured to end generation of the test vector, and an ending-condition determination or judgment section stopping generation of the path list when the ending condition is satisfied.
Still another aspect of the present invention inheres in a computer-implemented method for generating a test vector of a semiconductor integrated circuit according to embodiments of the present invention. The method includes designating a retrieval condition configured to select a path on which a signal can be transmitted in the semiconductor integrated circuit, executing a timing analysis of the semiconductor integrated circuit based on circuit information of the semiconductor integrated circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in an order of executing the timing analysis, generating a test vector configured to test a path delay fault of the semiconductor integrated circuit based on the path list, designating an ending condition configured to end generation of the test vector when the path in the path list for the test vector is distributed over the semiconductor integrated circuit, and stopping generation of the path list when the ending condition is satisfied.
Still another aspect of the present invention inheres in a computer program product to be executed by a computer for generating a test vector of a semiconductor integrated circuit according to embodiments of the present invention. The program product includes instructions designating a retrieval condition configured to select a path on which a signal can be transmitted in the semiconductor integrated circuit, instructions executing a timing analysis of the semiconductor integrated circuit based on circuit information of the semiconductor integrated circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in an order of executing the timing analysis, instructions generating a test vector configured to test a path delay fault of the semiconductor integrated circuit based on the path list instructions designating an ending condition configured to end generation of the test vector when the path in the path list for the test vector is distributed over the semiconductor integrated circuit, and instructions stopping generation of the path list when the ending condition is satisfied.
Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.
(First Embodiment)
In a method for designing and manufacturing a semiconductor integrated circuit according to the first embodiment, specifications of the semiconductor integrated circuit are input at STEP S1, as shown in
A test pattern is generated at STEP S3. A test vector 1 is generated, based on the test pattern. The test vector 1 by which a specific region is tested by designating the specific region on the semiconductor integrated circuit is generated in order to execute the delay fault test over all of the area of the semiconductor integrated circuit, to the extent possible.
The test vector 1 includes; a preparation vector; a system clock vector; and a detection vector. Initial logical-values of external pins and internal pins of the semiconductor integrated circuit can be set, using the preparation vector. Using the system clock vector, control signals are input, not only from the clock line, but also from arbitrary external pins and arbitrary internal pins to the semiconductor integrated circuit. The initial logical-values of the external and the internal pins are set, using the preparation vector, and the logic of the external and the internal pins are controlled, using the system clock vector, to activate a desired path of the semiconductor integrated circuit and to operate the cells and the circuit blocks on the path. In the detection vector, the expectation values which are expected to be output from the cells and the circuit blocks, which have been operated based on the preparation vector and the system clock vector, to the external and the internal pins are arranged. Simulation is executed for verification of the functions and the timing in a semiconductor integrated circuit. The simulation is executed, based on the test pattern. The test vector 1 is used in the simulation.
It is judged or determined at STEP S4 whether a logical operation value which is output based on the preparation vector and the system clock vector is in agreement with the expectation value based on the detection vector. The processing proceeds to STEP S5 when there is an agreement between the logical operation value and the expectation value and the processing returns to STEP S2 when there is no agreement between the logical operation value and the expectation value for correcting the netlist and the layout pattern of the semiconductor integrated circuit
At STEP S5, a semiconductor substrate is processed and the semiconductor integrated circuit for which operation tests can be conducted is manufactured.
The delay fault test of the manufactured semiconductor integrated circuit is executed at STEP S6. The test vector 1 is used for the delay fault test at STEP S6. Here, a delay fault test may be executed, using the corresponding test vector 1, especially, for a critical path which has been identified as a result of verification for timing at STEP S3. The test vector 1, by which a specific region is tested by designating the specific region on the semiconductor integrated circuit, may be generated in order to execute the delay fault test over all of the area of the semiconductor integrated circuit, to the extent possible. A test for confirming whether a signal corresponding to the expectation value is output or not within a predetermined delay time, which is defined so that there is no breach in the operation frequency of the semiconductor integrated circuit, is executed for obtaining a measurement value of the delay time. Moreover, the test vector, which activates the critical path, for the delay fault test may be generated at STEP S6.
It is determined or judged at STEP S7 whether the delay fault occurs by the activated path. Based on the decision, it is determined or judged whether a fault analysis of the semiconductor integrated circuit is required or not. When a delay fault occurs, it is determined or judged that a fault analysis is required and the processing proceeds to STEP S8. When a delay fault does not occur, it is determined or judged that a fault analysis is not required and the processing proceeds to STEP S9 at which the semiconductor integrated circuit is completed. Accordingly, the method for manufacturing the semiconductor integrated circuit is completed.
The fault analysis of a fault path on which the delay fault occurs is executed at STEP S8. In the delay fault analysis of the path, the fault path is estimated, using a test vector which failed in the delay fault test and circuit information on the semiconductor integrated circuit. Alternatively, the fault path is identified, using a path input at generation of the test vector which failed in the test when a test vector for the delay fault is generated.
In order to determine or judge what circuit blocks and what cells of the semiconductor integrated circuit have been tested by the fault path, the fault path can be displayed on a screen displaying the layout pattern when information on the fault path is added to the layout pattern of the semiconductor integrated circuit. It is possible to limit a range in which the fault path exists.
However, it is impossible to identify what cell has the delay fault, because the fault path has a configuration in which a plurality of cells is connected. In order to determine the cell which causes the delay fault, a new path, which shares a part of the cells with the fault path, for fault-cell searching is searched. A test vector which activates the path for fault-cell searching is generated. The delay fault test of the path for fault-cell searching is executed, using the test vector.
Test vectors for a plurality of paths, each of which shares respectively different parts of the cells with the fault path, for fault-cell searching are generated for the test. At this time, only the test vectors including the cells which cause the delay fault fail the testing. Then, the range of cells which cause failure is narrowed to specify the cell which is finally identified as the cell which causes the failure.
(Apparatus for Generating a Test Vector)
An apparatus for generating a test vector according to the first embodiment is a computer. As shown in
In the retrieval-condition designation section 11, a retrieval condition is designated for selecting a path on which a signal can be transmitted in the semiconductor integrated circuit.
In the circuit-information storage section 13, circuit information on the semiconductor integrated circuit is recorded so that the computer can read the information.
In the path-list generation section 14, timing analysis is executed, based on the circuit information on the semiconductor integrated circuit, a path satisfing the retrieval conditions is retrieved, and a path-list in which cells forming a retrieved path are arranged in the order of executing the timing analysis of the cells forming the retrieved path is generated.
In the path-list storage section 15, the generated path-list is recorded so that the computer can read the list.
In the test-vector generation section 16, the test vector 1 and test-vector-generation information are generated for the delay fault test of the path on the semiconductor integrated circuit, based on the path-list.
In the test-vector storage section 17, the generated test vector 1 is recorded so that the computer can read the vector.
In the test-vector-generation information storage section 18, the generated test-vector-generation information is recorded so that the computer can read the vector.
In the ending-condition designation section 12, an ending condition is designated for ending generation of the test vector 1. Moreover, the ending-condition designation section 12 includes a coverage-judging-condition designation section 201 and a coverage-rate definition section 202. When the ending condition is satisfied in the ending-condition determination or judgment section 19, generation of the path-list in the path-list generation section 14 is stopped.
The coverage-judging-condition designation section 201 divides the semiconductor integrated circuit into a plurality of regions, and designates a coverage determining or judging condition for determining or judging that a region is covered by the path-list path, which is the base of the generated test vector. In the ending-condition determination or judgment section 19, judging or determination of covered regions is executed by assuming that the coverage judging condition is treated as an ending condition. The path-list generation section 14 and the test-vector generation section 16 executed judging of covered regions, assuming that the coverage judging condition is treated as a retrieval condition and a path-list or a test vector of a path which is judged to be covered is extracted. A coverage judging condition considers several factors. For example, the number of paths passing the region, the logic elements in the path in the region, the wiring length of the path, the number of vias and contacts is larger than a predetermined value, and that a layer of wiring on the path and via is a predetermined layer. Tests can be suitably executed for each region by using a concept of the coverage. That is, it is difficult to execute suitable testing of a region, using a test vector for one path, when the path passes very close to the edge of the region. Then, a path is required to pass the region so that suitable testing can be executed. The concept of the coverage can satisfy the above requirement.
The coverage-rate definition section 202 designates the coverage rate as a ratio of the number of the regions which are judged to be covered to the total number of regions. The ending-condition designation section 12 designates the ending condition as that the coverage rate, as a result of the generation of the test vector, of the path is larger than the predetermined coverage rate. The retrieval-condition designation section 11 designates the retrieval condition as that the coverage rate of the path is larger than the predetermined coverage rate.
The input section 204 and the output section 206 exchange data between the apparatus for generating a test vector, and external apparatuss or operators.
A plurality of test vectors, which are based on a plurality of paths which have coverage rates larger than a predetermined value, can be generated by using coverage rates, in the selected chip regions, of paths, which have succeeded in generation of test vectors, as the retrieval condition and the ending conditions. Thereby, test vectors, by which a chip can be uniformly tested with high quality can be generated, because paths are not concentrated in an unbalanced manner on a part of the regions on the chip.
An apparatus for generating a test vector may be a computer and an apparatus for generating a test vector may be provided by executing procedures in accordance with a program in the computer.
(Test-Vector Generating Method)
The test-vector-generating method according to the first embodiment can be executed in a computer. At STEP 11, circuit information is input from the circuit-information storage section 13 to the path-list generation section 14 in the test-vector-generating method according to the first embodiment, as shown in
Then, the ending-condition designation section 12 generates a condition, at STEP S12, which ends the generation process of the test vector 1. At generation of the ending condition, the ending-condition designation section 12 generates and designates a numerical value which is an ending condition which is, for example, the number of test vectors 1 which succeed in generation, the sum of the logic elements which the generated test vectors 1 pass, and the sum of the start points and the end points that the generated test vectors 1 are required to exceed the predetermined value.
At STEP 13, the retrieval-condition designation section 11 generates a condition on which a path of the logic circuit to be tested is retrieved. At generation of the retrieval condition, the retrieval condition for a first retrieval operation and the retrieval conditions for retrieval operations after a second retrieval operation are generated.
At generation of the retrieval condition for the first retrieval operation, the retrieval-condition designation section 11 generates and designates a specific ranking as the retrieval condition, wherein the ranking of the path is required to be higher than the specific ranking, when the paths are arranged in the decreasing order of, for example, signal-propagation-time, that is, delay time on the path.
At generation of the retrieval condition for retrieval operations after the second operation, the retrieval-condition designation section 11 generates and designates a retrieval condition “the interior of the semiconductor integrated circuit is divided to generate divided regions and a path is required to pass through the divided regions where no path has passed, determined by using a result of generation of a path which has succeeded in generation of the test vector according to the retrieval conditions for retrievals at the first retrieval operation and after the second operations”.
Designation of the number of total steps which is the sum of the numbers of cells on the paths, designation of the total wiring length of the wiring for signal transmission on the path, designation of the number of vias or of contacts on the path of a signal transmission line, and designation of a layer to which wiring or the vias belong are assumed as other retrieval conditions for the first retrieval operation.
Moreover, a coverage condition can be set in which the coverage is defined so that a path passes a divided region. The total number of steps and the total wiring lengths on the path, the number of vias and contacts, designation of a layer to which wiring or the vias belong, and the like in the divided region of an target are considered as the coverage condition.
Here, the executing order of STEPs S11, S12 and S13 may be arbitrary, or the above STEP S11, S12, and S13 may be simultaneously executed.
Subsequently, a path-list for paths of an object of the test-pattern generation on the semiconductor integrated circuit is generated at STEP S14 in the path-list generation section 14 under a timing analysis of the semiconductor integrated circuit, based on the designated retrieval condition. The path list is stored in the path-list storage section 15.
It is judged or determined at STEP S15 whether the path list for the path of a target of the test pattern generation has been newly extracted. In the flow chart of
At STEP S16, the path-list stored in the storage section 15 and circuit information on the semiconductor integrated circuit stored in the circuit-information storage section 13 are input to the test-vector generation section 16. Then, test vectors by which delay faults can be detected are generated for each path. The circuit information to be input may be different in the degree of details and the level of the description form that of the circuit information used for generating path lists at STEP S14. The test-vector generation section 16 records and stores the test vectors, which have succeeded in the generation, in the test-vector storage section 17. Moreover, the test-vector-generation information as to whether test vectors are successfully generated for each path is recorded and stored in the test-vector-generation information storage section 18.
At STEP S17, the ending-condition judgment section 19 judges or determines whether the current situations of generation of test vectors, stored in the test-vector-generation information storage section 18, satisfy the ending requirements designated at STEP 12 for designation of an ending condition.
At STEP S18, the processing returns to STEP S13 when the current situations of generation of test vectors, stored in the test-vector-generation information storage section 18, do not satisfy the ending requirements. At STEP S13, a retrieval condition is updated to a new retrieval condition for designation. The new retrieval condition is changed so that a test vector is more successfully generated in comparison with the case using the previous retrieval condition. Subsequently, a new path is retrieved at STEP S14 to generate a path-list of the path again, based on the new retrieval condition. It is judged at STEP S15 whether a path-list of new paths is generated, based on the new retrieval condition. When the path-list of new paths is generated, the processing proceeds to STEP S16. When the path-list of new paths is not generated, the processing proceeds to STEP S19. At STEP S19, a final test-vector-generation information is output to an external memory. Moreover, a final test vector is output to the external memory at STEP S20. Thereafter, the test-vector generating method is ended. Here, the processing may return to STEP S13 again when the path-list of the new paths is not generated.
At STEP S18, the processing proceeds to STEP S19, at which a final test-vector-generation information is output to an external memory when the current situations of generation of test vectors, stored in the test-vector-generation information storage section 18, satisfy the ending requirements. A final test vector is output to the external memory at STEP S20. That is, the processing is ended in the test-vector generating method when another path satisfying the retrieval condition is not newly retrieved, or when generation situations of test vectors satisfy the ending condition.
Thus, the test-vector generating method can be highly automated and the quality of the generated test vector can be improved according to the apparatus for generating a test vector, because a test vector for a path can be generated by executing the test-vector generating method, using the retrieval condition and the ending condition. Moreover, in the past, the period required for generating the test vector has been several weeks because substantial manpower was required. However, the period according to the invention is only several days.
For the test-vector generating method, a program which can be executed as a procedure by a computer, for generating the test vector is made. The test-vector generating method can be executed the program for generating the test vector.
(Variant 1 of the First Embodiment)
In an apparatus for generating a test vector according to the first embodiment of
The chip-region designation section 20 reads information on the logic circuit of the semiconductor integrated circuit from the circuit-information storage section 13. The chip-region designation section 20 generates a screen image of the entire chip area of the semiconductor integrated circuit, or a part of the logic circuit (a so-called user logic section except for circuit blocks which are generally built in) which is a part of the chip area and an object for forming a test vector for a path delay-fault test. The screen image is a display section of the chip-region designation section 20 which an operator of the apparatus for generating a test vector can recognize. Then, the chip-region designation section 20 is configured to generate regions which divide the screen image of the logic circuit part which is the object for forming a test vector. According to a method for dividing the screen image, the section 20 decides and designates a number of divisions in the vertical direction and in the horizontal one of the screen image of the logic circuit part, respectively, and the screen image of the logic circuit part is equally divided into the designated numbers of regions in both directions for display. The chip-region designation section 20 generates display-image division information which has display positions for line segments for dividing the screen image of the logic circuit part on the screen image. The chip region specification part 20 divides the screen image of the logic circuit part by superposing the screen image of line segments for divisions on the screen image of the logic circuit part, based on the display-image division information.
The chip-region designation section 20 displays the screen image of the semiconductor integrated circuit, wherein the image is divided into the regions. Using the display, an operator of the apparatus for generating a test vector is requested to designate a divided region, based on the screen image of the semiconductor integrated circuit. Preferably, a screen image of a path which has already succeeded in generation of a test vector is superposed and displayed on the screen image of the semiconductor integrated circuit when the operator is requested to designate a divided region. By seeing a display screen on which the screen image of a path is superposed on the screen image of the semiconductor integrated circuit, the operator can instantaneously discriminate between a divided region in which a path for a test vector is generated is arranged and a divided region in which a path for a test vector is not generated. The operator of the apparatus for generating a test vector designates a divided region in which the operator desires to arrange a path, responding to a request of the chip-region designation section 20, and inputs the designated specific divided region. The operator is required only to select one of the regions, in which test vectors have not yet been generated, as a region in which the path is desired to be arranged. Preferably, the output section and the input section are an input and output section such as an integral touch panel. A touch panel is used because a screen image is required to be displayed on a screen as an output and, at the same time, input is required to be executed on the screen. An intent of the operator to designate a specific region is realized when the operator touches a screen image in the specific region displayed on the touch panel so as to provide an input.
Retrieval-condition designation section 11 designates a retrieval condition by which a designated path arranged in the designated region can be retrieved, based on the fact that the specific input region is designated. In the retrieval-condition designation section 11, a device user explicitly designates a region in which the user desires to arrange a path on the displayed semiconductor integrated circuit and a retrieval condition to be recreated is that a path is arranged in the designated region. In the path-list generation section 14, generation is executed, based on the recreated retrieval condition.
Here, in the retrieval-condition designation section 11, a retrieval condition that a path is arranged in a region, in which a path had not been previously arranged is automatically designated without depending on an operator input and the retrieval condition may be recreated. Thereby, paths can be uniformly arranged on the semiconductor integrated circuit.
In the chip-region designation section 20, a single region has been designated as described above. But, not only a single region, but also a plurality of regions can be designated and a priority among the plurality of regions can be designated. Thereby, paths arranged in each region are retrieved in a decreasing order of priority. Moreover, designation of regions in the chip-region designation section 20 may be performed whenever the processing returns to STEP S13, or after the loop in the flow chart of
Thus, situations for generation of test vectors are displayed at designation of a retrieval condition at STEP S13 to allow an operator to confirm the situations, or to designate conditions, such as a priority, at the following generation of test vectors. Accordingly, a set of test vectors which are finally generated can be adjusted according to the intention of the device user.
Moreover, the operator designates a region in which the operator desires to form a test vector in a path, and, at the same time, repeatedly selects a new path while changing the retrieval condition which the apparatus for generating a test vector has designated. Thereby, a higher quality test vector which is finally generated can be obtained by the operator's designation of regions.
(Variant 2 of the First Embodiment)
An apparatus for generating a test vector according to a second variant of the first embodiment has a configuration, as shown in
In the circuit-information setting section 21, a retrieval item relating to the circuit information and a setting range for path retrieving corresponding to the retrieval item are set. The circuit-information setting section 21 selects an item of a retrieval condition, as to whether a path is extracted by a retrieval based on a plurality of items relating to process and design. The circuit-information setting section 21 decides and sets a target value which an extracted cell is required to have for the gauge. The following combination is assumed to be considered. For example, the items relating to process and design, and the gauges for the items and the target values. When the item is a pin name of a cell, the gauge and the target value are a specific pin name of the start point or the end point of a path. When the item is wiring, the gauge is a sum of the wiring length of the wiring for a signal route of a path and the target value is the range of lengths, such as 2 mm or more. When the item is via, the gauge is a number of vias which provide a signal route of a path, and the target value is the range of a number such as 700 or more. When the item is a contact, the gauge and the target value can be treated in a similar manner to the case of the via. When the item is a layer of wiring and the via, the gauge and the target value are such that the signal route of the path includes the layer of the wiring and the via. When the target is the number of steps of the path, the gauge is a number of cells forming the path, and the target value is the range of numbers such as 20 or more. Here, a plurality of gauges and a plurality of target values may be set for one item. Moreover, a plurality of target values may be set for one gauge.
In the retrieval-priority decision section 22, a priority is decided among combinations of retrieval items to be satisfied by a path to be retrieved. In the retrieval-priority decision section 22, precedence such as the priority determining a cycle at which a retrieval condition is adopted is set as an item gauge target value for process and design to be adopted as a retrieval condition to be updated every cycle in the loop of
In the circuit-information changing section 23, a set value at the circuit-information setting section 21 is relieved and a new path-list or a new test vector is more easily generated when a new path-list is not generated in the path-list generation section 14, or when a new test vector is not generated in the test-vector generation section 16. In the circuit-information changing section 23, a retrieval condition is recreated and relieved when a path is not selected, based on a retrieval condition, or when generation of a test vector for a selected path results in failure.
That is, the retrieval condition includes: a circuit-information condition; a retrieval-priority condition; and a circuit-information changing condition. The circuit-information condition includes: a retrieval item concerning circuit information; and a set value corresponding to the retrieval item and determining a range in which a path is retrieved. The retrieval-order condition includes priorities among combinations of retrieval items upon determination of a path to be retrieved. The circuit-information changing condition includes a relieved set value by which a new path-list or a new test vector is more easily generated, when a new path-list is not generated in the path-list generation section 14, or when a new test vector is not generated in the test-vector generation section 16.
Since the retrieval-condition designation section 11 includes the circuit-information setting section 21, the retrieval-priority decision section 22, and the circuit-information changing section 23, the retrieval condition can be relieved and updated. For example, a large number of items are adopted as a retrieval condition for the first cycle and items which have been adopted can be deleted from the retrieval condition at cycles after the second cycle. Moreover, a target value with which a path is not easily extracted is adopted as the retrieval condition of the first cycle, and a target value which is changed so that a path is more easily extracted can be adopted at cycles after the second cycle, based on the same gauges for the same items with those for the target value which have already been adopted.
Here, it is obvious that the retrieval-condition designation section 11 can be provided with all sections of the circuit-information setting section 21, the retrieval-priority decision section 22, and that the circuit-information changing section 23, and the section 11 can include at least one of the sections 21-23.
The test-vector generating method according to the second variant of the first embodiment is obtained by adding STEPs S21 and S22 to the test-vector generating method according to the first embodiment shown in
When it is decided at STEP S15 that extraction of a new path has failed at generation of the path-list of STEP S14, the processing proceeds to STEP S22 and the path-list generation section 14 sets a failed-retrieval flag in the path-list storage section 15. Similarly, when it is decided at STEP S21 that generation of a new test vector has failed at generation of the test vector of STEP S16, the processing proceeds to STEP S22 and the test-vector generation section 16 sets a failed-retrieval flag in the test-vector storage section 17.
At STEP S22, the circuit-information changing section 23 detects the failed-retrieval flag for relieving the retrieval condition. By this operation, while changing the retrieval condition, selection of a new path can be repeatedly executed.
As described above, an operator can adjust the quality of the test vector which is finally generated in order to obtain a higher quality test vector, because a new path can be repeatedly selected while changing the designated retrieval condition and a test vector for a selected path can be repeatedly generated while changing the condition, in the process for generation of a test vector.
(Variant 3 of the First Embodiment)
An apparatus for generating a test vector according to a third variant of the first embodiment has a configuration, as shown in
In the pin-name-list providing section 25, a pin-name list extracting pin names of cells in the designated regions is compiled, based on the detailed placing and routing of layout information for cells in the circuit information on the designated regions in the chip. In the circuit-information extraction section 24, circuit information according to the retrieval item is extracted for each pin-name list.
A flow chart for a method which generates a test vector is basically the same as that of
Based on data of circuit information in the circuit-information storage section 13, the circuit-information extraction section 24 extracts circuit information with regard to an item, which is set in the circuit-information setting section 21, in each pin-name list which is stored in the pin-list storage section 26. Here, the circuit information for each pin-name list is, for example, a wiring length of each wiring which is connected to each pin corresponding to each pin name described for each pin-name list. Moreover, the circuit information in each pin-name list is information such as the names of the wiring layers for each wiring which is connected to each pin corresponding to each pin name described for each pin-name list. The extracted circuit information is stored in the circuit-information for each pin-list storage section 27.
Thus, the retrieval-condition designation section 11 and an operator can adjust the quality of the test vector which is finally generated in order to obtain a higher quality test vector, because information such as a pin-name list for a selected region, a wiring length and a wiring layer corresponding the pin-name list can be automatically obtained when the chip-region designation section 20 selects a region for which a test vector is required to be made in the test-vector generating method. According to an adjustment method, a retrieval condition of a path may be designated so that a pin to which specific wiring having, for example, the longest wiring length is connected is included.
(Variant 4 of the First Embodiment)
In an apparatus for generating a test vector according to a fourth variant of the first embodiment, a pin list input from a pin-list storage section 26 and circuit information for each pin list input from a circuit-information for each pin-list storage section 27 are further input to a path-list generation section 14 corresponding to the path-list generation section 14 in the apparatus for generating a test vector according to the third variant of the first embodiment shown in
The chip-region designation section 20 designates a region in the chip. The pin-name-list providing section 25 makes a pin-name list for the designated region. The compiled pin-name list is memorized and reserved in the pin-list storage section 26. In the circuit-information extraction section 24, the circuit information with regard to retrieval items of the retrieval condition is extracted for each pin-name list, based on the pin-name list, the circuit information and the retrieval condition and circuit information for each pin list is generated. The generated circuit information for each pin list is memorized and reserved in the circuit-information for each pin-list storage section 27.
Based on the pin-name list stored in the pin-list storage section 26 and circuit information for each pin list stored in the circuit-information for each pin-list storage section 27, the path-list generation section 14 makes a path list for new paths. The path-list generation section 14 is not required to make a path list by reading required circuit information from a vast amount of circuit information recorded in the circuit-information storage section 13. The amount of the circuit information for each pin list is far smaller than that of the circuit information recorded in the circuit-information storage section 13. Moreover, the amount of information can be much more reduced because the circuit information is stored with regard to only the pin-name list.
When a path-list of new paths cannot be generated so as to fail to extract the new path, the path-list generation section 14 set a failed extraction flag. The circuit-information changing section 23 detects the failed-extraction flag to relieve the retrieval condition. The path-list generation section 14 makes a path-list of new paths, based on the relieved retrieval condition, and extraction of a new path is continued.
A compiled path-list is for paths which pass a region designated by the chip-region designation section 20. The test-vector generation section 16 generates a test vector for the path list. The region designated by the test vector can be tested. When the test-vector generation section 16 fails in generation of the test vector, the circuit-information changing section 23 relieved the retrieval condition. The test-vector generation section 16 continues the generation of the test vector, based on the relieved retrieval condition. That is, retrieval conditions for generation of a path list at STEP S14 after STEPs S17, S18, S13 are not relieved in some cases, depending on retrieval conditions which have been relieved at STEP S22 in
Thus, a test vector which is finally generated can have higher quality in the apparatus for generating a test vector, because a region to which a path for which the operator desires to form a test vector is designated, a new path can be repeatedly retrieved while changing the retrieval condition for a path list in the designated region, and a new test vector can be repeatedly formed while changing the generation condition of test vectors for the extracted path.
Furthermore, an operator of the apparatus for generating a test vector can input a desired region into the chip-region designation section 20, responding to a request of the section 20 when a region to which a path for which a test vector is desired to be formed is designated. By the input of the desired region, the chip-region designation section 20, which designates a region the operator desires as a region in which a path for a test vector is made. Thus, the operator can adjust the quality of the test vector.
(Variant 5 of the First Embodiment)
An apparatus for generating a test vector according to a fifth variant of the first embodiment has a configuration, as shown in
The path-circuit-information making section 191 makes circuit information for each retrieval item on a path which covers regions are designated by the chip-region designation section 20. The circuit information is made based on the circuit information, which has been extracted in the circuit-information extraction section 24, for each pin list according to the retrieval items.
The delimiter-value designation section 195 sets a delimiter value within or beyond a setting range of retrieval items for the retrieval condition. If the setting range is divided into a plurality of zones with the delimiter value, generating priorities can be assigned to paths at generation of a test vector. If the delimiter value is set beyond the setting range, the number of paths is increased by extending the setting range to the delimiter value to satisfy the ending condition when a path satisfying the setting range does not satisfy an ending condition. Here, the delimiter-value designation section 195 is preferably provided in the retrieval-condition designation section 11 because the delimiter value is set with regard to items selected from retrieval items for the retrieval condition.
The highlighted-path selection section 193 compares the circuit information on paths according to each retrieval item with the delimiter value. The paths are distinguishably displayed and are superposed on a screen image of the semiconductor integrated circuit for each zone, which is divided by the delimiter value, and to which the circuit information on paths belongs, according to each retrieval item.
The path-list generation section 14 generates a path-list. The generated path-list is stored in the path-list storage section 15. The circuit information on paths in the path list is made or compiled in the circuit-information making section 191. The made circuit information on the paths is stored in the path-circuit-information storage section 192.
The highlighted-path selection section 193 selects a path, which has the value of the circuit information on the path which exceeds the delimiter value which the delimiter-value designation section 195 has set, from the paths stored in the path-circuit-information storage section 192. With regard to a retrieval item for which the delimiter value is provided, the larger the value of a path is, the stronger the tendency to extract the path. Accordingly, exceeding the set delimiter value is a standard for extracting the path. The highlighted-path selection section 193 makes a list of paths for which the screen images are superposed on the screen image of the semiconductor integrated circuit while highlighting the screen images of the paths. The list of paths for which the highlighting is executed is stored in the highlighted-path information storage section 194.
In the chip-region designation section 20, paths in the path-list stored in the highlighted-path information storage section 194 are superposed on the screen image of the semiconductor integrated circuit and are highlighted. A method in which the line width of the line segment of a highlighted path is more thicker than that of a non-highlighted path, or another path by which the color of the line segment of a path is changed, depending on a path to be highlighted or a path not to be highlighted can be used as the highlighting method.
In the above-described test-vector generating method, the chip-region designation section 20 can select a region of a path, the delimiter-value designation section 195 sets a delimiter value for highlighting of a retrieval item as the retrieval condition, the highlighted-path selection section 193 selects a path to be highlighted based on the delimiter value, and the chip-region designation section 20 highlights the selected path. Accordingly, an operator can confirm whether a highlighted path is arranged in a selected region or not. By the above confirmation the operator can effectively select a chip-region again so that a set of the test vectors finally generated becomes higher quality test vectors. For example, the operator can select a region in which a highlighted path is not arranged.
(Second Embodiment)
A fault analysis apparatus of a semiconductor integrated circuit according to the second embodiment executes operations corresponding to STEPs S6 through S8 in
A fault analysis apparatus of a semiconductor integrated circuit according to the second embodiment includes as shown in
The test execution section 41 executes a test for judging whether a delay fault is caused on a path in the processed semiconductor integrated circuit. A test vector 1 in
The cell-list generation section 43 generates a cell list of cells forming the fail path, based on the result of a delay fault test and the semiconductor integrated circuit stored in the circuit-information storage section 33. The cell-list storage section 44 stores the cell list of cells forming the generated fail path.
The retrieval-condition designation section 31 designates a retrieval condition which retrieves a path for searching a fault cell having a part of the fail path.
The path-list generation section 34 retrieves the path for searching a fault cell, based on the designated retrieval condition, and generates a path list for fault-cell searching, wherein cells forming the retrieved path for fault-cell searching are arranged in the order by which a signal can be transmitted. The path-list storage section 35 stores the generated path list for fault-cell searching.
The test-vector generation section 36 generates a test vector for fault-cell searching, based on the circuit information in the circuit-information storage section 33, for each path in the path list for fault-cell searching. The test-vector storage section 37 stores the test vector for fault-cell searching. The vector-generation-information storage section 38 stores a generation state of the test vector as vector-generation information.
The ending-condition designation section 32 designates an ending condition which ends the generation of the test vector. Here, the ending condition to be designated may be of a fixed type or of a variable type. The ending-condition judgment section 39 stops generation of the path-list when the vector-generation information satisfys the ending condition.
The input section 204 and the output section 206 exchange data between the fault analysis apparatus of the semiconductor integrated circuit, and the external apparatus or the operator.
(Fault Analysis Method for a Semiconductor Integrated Circuit)
A fault analysis method of a semiconductor integrated circuit according to the second embodiment can be executed by a computer. In the fault analysis method of a semiconductor integrated circuit according to the second embodiment, a test for a delay fault in the semiconductor integrated circuit is executed by the test execution section 41 at STEP S31, as shown in
When a fail path is generated at the test, the test execution section 41 makes or compiles fail data including a distinguishable display number of the fail path as the test result at STEP S32. The fail-data storage section 42 stores the made or compiled fail data. The fail data is the judgment results of the tests for each path, test numbers, measured delay time and the like.
Then, circuit information on the semiconductor integrated circuit is input from the circuit-information storage section 33 to the cell-list generation section 43 at STEP S33. The circuit information to be input may be a netlist in which information on cell connection is described, or layout information on a circuit of placing and routing of layout of the cells when a more details placing and routing of layout of the cells is a retrieval condition for path retrieval.
The cell-list generation section 43 generates at STEP S34 a cell list of cells forming the fail path, based on the fail data and the circuit information. The generated cell list is stored in the cell-list storage section 44.
The retrieval-condition designation section 31 designates at STEP S35 a retrieval condition, based on which, a path sharing a part of the fail path is retrieved, for fault-cell searching. The total number of steps and the total wiring lengths on the path, the number of contacts and vias, designation of a layer to which wiring and the vias belong, and the like can be listed as a retrieval condition for fault-cell searching in a similar manner to that of STEP S13 in
At STEP S36, the ending-condition designation section 32 designates the ending condition for fault-cell searching to end generation of a test vector. A condition that a number of test vectors which have succeeded in generation is equal to or larger than a predetermined number, or a trial of generation of test vectors for all the paths to be tested is assumed to be as an ending condition for fault-cell searching in a similar manner to that of STEP S12 in
AT STEP S37, the path-list generation section 34 extracts cells, based on the cell list of the fail path and the retrieval condition; performs timing analysis of the path circuit according to the retrieval condition after designating a cell name as a distinguishable display number of the cell; and makes a path list for fault-cell searching for a path, which satisfys the retrieval condition. The path-list for fault-cell searching made by the path-list storage section 35 is stored. It is judged in the path-list generation section 34 at STEP S38 whether a path for fault-cell searching, which satisfys the retrieval condition for fault-cell searching is extracted or not. When extracted, the processing proceeds to STEP S39. When not extracted, the processing returns to STEP S35 and the retrieval condition is adjusted again. When a path exists for fault-cell searching which has already been extracted and a test vector for fault-cell searching with regard to the path is generated after a loop from STEP S35 through STEP S41, wherein the processing proceeds into the loop in the case of NO at STEP S41, then the processing proceeds to STEP S42.
The path-list for fault-cell searching and the circuit information on the semiconductor integrated circuit stored in the circuit-information storage section 33 are input to the test-vector generation section 36, at STEP S39 and a test vector for fault-cell searching is generated, wherein the test vector can detect a delay fault in each path included in the path-list for fault-cell searching. The circuit information may have a detail level and description format different from that of the circuit information used in generate the path-list at STEP S37. When the test vector is successfully generated for fault-cell searching, the test-vector generation section 36 stores the test vector in the test-vector storage section 37. Moreover, the section 36 stores a distinguishable display number of a path for fault-cell searching and vector-generation information, whether the test vector is successfully generated or not, in the vector-generation-information storage section 38.
The ending-condition judgment section 39 judges at STEP S40 whether the vector-generation information satisfys the ending condition for fault-cell searching.
When it is decided at STEP S41 in the ending-condition judgment section 39 that the vector-generation information is in accordance with the ending condition for fault-cell searching, the processing proceeds to STEP S42 to stop generation of the test vector.
When it is decided at STEP S41 in the ending-condition judgment section 39 that the information is not in accordance with the ending condition for fault-cell searching, the processing returns to STEP S35. The retrieval-condition designation section 31 updates the retrieval condition to a new condition for fault-cell searching at STEP S35. A new path for fault-cell searching, which satisfys the updated retrieval condition for fault-cell searching, is retrieved and a path-list and a test vector for fault-cell searching are generated by processing between STEP S35 and STEP S41. The loop is ended when a new path in accordance with the retrieval condition for fault-cell searching is not retrieved, or when the vector-generation information is in accordance with the ending condition for fault-cell searching, and the processing proceeds to STEP S42.
At STEP S42, the test-vector generation section 36 extracts a final vector-generation information and outputs the final vector-generation information to the external memory. At STEP S43, the test-vector generation section 36 outputs the generated test vector for fault-cell searching to the external memory.
Thus, a generating method of a test-vector for analysis of a delay fault path can be highly automated and the quality of a generated test vector for fault-cell searching can be improved to a higher and more uniform test vector by generating the test vector for a path for fault-cell searching, based on the cell list for the fail path, the retrieval condition and the ending condition. Moreover, the period which has been required for fault analysis has been from several weeks through several months in manpower, but the period according to the invention is reduced to several days through several weeks.
(Variant 1 of the Second Embodiment)
As shown in
The chip-region designation section 50 displays a line segment of a fail path on the screen image of the semiconductor integrated circuit including the screen image of the fail path so that the line segment is along the screen image of the path. The line segment of the fail path can be distinguished from the screen image of the semiconductor integrated circuit. Preferably, the line segment of the fail path is highlighted.
The chip-region designation section 50 displays a line segment of a path for fault-cell searching so that the segment is along the screen image of the path, which includes a part of the fail path, for fault-cell searching. The line segment of a path for fault-cell searching can be distinguished from the screen images of the semiconductor integrated circuit and the fail path, and the line segment of the fail path. Preferably, the line segment of a path for fault-cell searching is highlighted. Especially, it is preferable to change colors of the line segments in order to distinguish the line segment of the fail path from that of the path for fault-cell searching. Other methods, such as a method for changing the widths of the line segments and a method for using a solid line and a dotted line for the distinction between the segments, can be used as a distinguishing method for the segments.
The fault-analysis method of the semiconductor integrated circuit, using the above fault-analysis apparatus basically has the same configuration as that of
The chip-region designation section 50 requests an operator, using an image display, to update a retrieval condition for a path to be newly retrieved when there is not a sufficient test vector for fault analysis. Responding to the request, the operator inputs an intent for updating the retrieval condition or a concrete retrieval condition to the section 50. The section 50 outputs the input retrieval condition and the like to the retrieval-condition designation section 31. The retrieval-condition designation section 31 updates the retrieval condition to the input one and the like. Accordingly, a test vector finally generated can be adjusted in such a way that the vector becomes the best available as a vector for fault analysis.
The chip-region designation section 50 checks the degree of overlap of the fail path with the path for which a new test vector is generated, using an image display. The chip-region designation section 50 requests the retrieval-condition designation section 31 to update the retrieval condition to a new condition for retrieval of a path passing a cell when there is a cell which cannot share a new path, in the fail path. The retrieval-condition designation section 31 updates the retrieval condition to a retrieval condition by which a path passing the cell can be retrieved.
(Variant 2 of the Second Embodiment)
As shown in
In the cell-list generation section 43, the placing and routing of layout information of a cell in the semiconductor integrated circuit is read from the circuit-information storage section 33 and pin-coordinate information of the input/output pin of a cell forming the fail path is generated, based on the placing and routing of layout information of the cell. The pin-coordinate storage section 51 stores pin-coordinate information. In the pin-coordinate information, an x-coordinate and a y-coordinate of a pin of the cell are associated with a pin name, which is written in a netlist, of the cell in such a way that both coordinates can be retrieved. The pin-coordinate information includes a data region which can memorize the pin name and another data region which can memorize x- and y-coordinates of the pin.
In the fault analysis technique of the semiconductor integrated circuit, a test method by which electron beams are irradiated on a chip for analysis of electric potential is simultaneously used in some cases. In the above test method, the pin-coordinate information of the input/output pin of the cell is indispensable in order to irradiate electron beams on the input/output pin of the cell. According to the above test method, the pin-coordinate information is automatically generated as fail-path information to reduce time required for fault analysis.
(Variant 3 of the Second Embodiment)
In a fault analysis apparatus of a semiconductor integrated circuit according to a third variant of the second embodiment, fail data from a fail-data storage section 42 is further input to a chip-region designation section 50 according to the first variant of the second embodiment of
By the above differences, the chip-region designation section 50 reads the logic circuit information of the semiconductor integrated circuit from a circuit-information storage section 33, and an image of a logic circuit part, for which a test vector for a path test is desired to be made, of a user logic having the peculiar specifications of a user on a chip is displayed. Moreover, the chip-region designation section 50 designates a method by which the logic circuit part for which the test vector is desired is divided into regions, divides the part into the regions, and generates divided-region information including shapes, sizes and arranged positions of the regions. The chip-region designation section 50 displays the images of the divided regions on the image of the logic circuit part in a superposed manner, based on the divided-region information. The region dividing method has a configuration in which the logic circuit part may be equally divided into regions by designating numbers of partitions in the vertical and horizontal directions, respectively, or, an operator may designate a region on a display screen.
A successful path, i.e., a no fail path and fail data on a fail path are input from the fail-data storage section 42 to the chip-region designation section 50, images of the successful path and a physical position of the fail path on the chip are displayed. The fail path and the successful path are displayed so that both paths can be distinguished from each other. By display of the successful and fail paths, an operator can confirm a ratio between the successful paths and the fail paths in each region and a distribution bias between the successful paths and the fail paths in all the chip.
The chip-region designation section 50 sets a coverage condition for the fail paths, based on the coverage of the fail paths, which is obtained by replacing the generated path by the fail path, and coverage regions satisfying the coverage condition and non-satisfying regions are displayed so as to be distinguished from each other. The above display may be achieved by changing colors for images. A condition that a number of fail paths passing a region is equal to or larger than a predetermined value can be applied for a coverage condition for the fail paths.
In the retrieval-condition designation section 31, a condition that a region which the fail path covers is covered by a path for fault-cell search is newly set as a retrieval condition. Alternatively, the chip-region designation section 50 requests an operator to displaying regions, which the fail paths cover, on the chip to specify and input a region which is desired to be covered with a path for fault-cell searching. The operator inputs regions to be covered into the chip-region designation section 50, responding to the above request. The chip-region designation section 50 outputs the operator input region to the retrieval-condition designation section 31. In the retrieval-condition designation section 31, a condition that a region which an operator desires to cover is covered is newly set as a retrieval condition.
Based on the new retrieval conditions, the path-list generation section 34 retrieves a path for fault-cell searching and generates a path-list of the path. The test-vector generation section 36 generates a test vector for the generated path-list. The test-vector generation section 36 outputs vector-generation information to the vector-generation information storage section 38 for storage when the test vector is successfully generated. The chip-region designation section 50 also displays the image of the new path for fault-cell search, based on the vector-generation information.
The chip-region designation section 50 can designate not only a retrieval condition for designating a region, but priorities for generation of a path list as a retrieval condition. Furthermore, the chip-region designation section 50 can designate priorities for generation of a test vector as a retrieval condition. Furthermore, the designation of a region by the chip-region designation section 50 may be performed at STEP S35 and S36 in the loop after a test vector is generated at STEP S40 in
Thus, situations of paths which succeed in the test, and of failed paths, or situations of test-vector generation during generation of paths for fault-cell searching can be displayed. The following priorities in the retrieval condition for path lists and in the ending condition for test vectors can be automatically designated by an operator, based on the above display. Thereby, the set of test vectors finally generated can provide a highly accurate fault-analysis.
In a test-vector generating method according to an example 1 of the first embodiment, circuit information is input from the circuit-information storage section 13 to the path-list generation section 14 at STEP S11, as shown in
Then, an ending condition shown in
At STEP S13, a retrieval condition for retrieval is generated in the retrieval-condition designation section 11 as shown in
Then, a path-list of paths as shown in
It is judged at STEP S15 whether a new path-list of paths is extracted. Since the path-list for a new path of path 1 has been generated, the processing proceeds to STEP S16.
At STEP S16, the test-vector generation section 16 generates test vectors and test-vector generation information of whether the test vectors have succeeded in generation for each path as shown in
It is judged at STEP S17 in the ending-condition judgment section 19 whether the test-vector generation information satisfys the ending condition. While the number of generated test vectors for test-vector generation information in
At STEP S13, a new retrieval condition is designated for updating. At STEP S14, a new path is retrieved and a path-list for the path is generated again. At STEP S15, it is judged whether a path-list for the new path is generated. When the path-list for the new path is generated, the processing proceeds to STEPs S16, S17, S18, and, finally, to STEP S19. Even when the path-list for the new path is not generated, the processing proceeds to STEP S19. At STEP S19, final test-vector generation information is output to the external memory. Furthermore, a final test vector is output to the external memory at STEP S20.
Thus, the test-vector generating method can be highly automated according to the apparatus for generating a test vector, because a test vector for a path can be generated by executing the test-vector generating method, using the retrieval condition and the ending condition.
A second example of the first embodiment is a case of an apparatus for generating a test vector similar to the apparatus for generating a test vector shown in
The chip-region designation section 20 generates a screen image 61 of the entire chip area of the semiconductor integrated circuit, based on logic-circuit information of a semiconductor integrated circuit, as shown in
Then, the chip-region designation section 20 generates regions 69 through 80 which divide the screen image 61. The chip-region designation section 20 decides to divide the screen image 61 so that the image is equally separated to three sections in the vertical direction and four sections in the horizontal direction. The chip-region designation section 20 generates display-image division information including positions for images of line segments which divide the screen image 61. The section 20 divides the screen image 61 into 69 through 80 sections of regions by superposing the images of line segments, which divide the screen image 61 on the screen image 61, based on the display-image division information. There are provided 62 through 66 sections of display regions for electrode pads on the peripheral part of the screen image 61. For example, a display 67 of a path is provided between the displays 63 and 66 for the electrode pads. The display 67 of the path passes through regions 71 and 73 through 75. A display 68 of a path is provided between the displays 64 and 65 of the electrode pad. The display 68 of the path passes through only the region 69.
The screen image 61 of the entire chip area of the semiconductor integrated circuit shown in
The large-scale logic circuit 93 includes: a flip-flop register 100 for scanning; and electrode pads 87, 88 connected to the register 100 through wiring 109. Similarly, the circuit 93 includes: a flip-flop registers 98, 99 for scanning; and electrode pads 89, 90 connected to the registers 98, 99 through wiring 110. A path 101 is provided between the registers 99, 100. A signal cannot be input or output directly to or from the registers 99, 100, different from the electrode pads 87 through 90. Accordingly, a preparation vector, a system-clock vector, and a detection vector are used as a test vector in order to test the path 101. The preparation vector is input from the electrode pads 87, 89 to set initial logic for the registers 99, 100 and the like before the testing. The system clock vector is input from the electrode pads 87, 89, 97, and the like to activate the path 101. The detection vector is an expectation value of the testing and is compared with an output vector from the electrode pad 88, caused by an output signal from the activated path 101.
Similarly, the large-scale logic circuit 94 includes: registers 103, 105, 106, 111 and electrode pads 91, 92 connected to the above registers 103, 105, 106, 111 by wiring. The path 104 is provided between the electrode pad 102 and the register 103. A path 107 is provided between the registers 105, 106. A test vector is generated for input or output of a signal to or from the registers 103, 105, 106.
When the large-scale logic circuits 93, 94 are equally divided into regions in a similar manner to that of
Therefore, the large-scale logic circuits 93, 94 are divided into regions 116 through 128, as shown in
The chip-region designation section 20 displays the screen images of the large-scale logic circuit 93, 94 of the semiconductor integrated circuit. Using the screen displays, an operator of the apparatus for generating a test vector is requested to divide the screen images of the large-scale logic circuits 93, 94 into regions, based on the screen image of the semiconductor integrated circuit and to designate a divided region. The operator selects the screen image of the large-scale logic circuit 94, responding to the request of the chip-region designation section 20 and inputs an intent to divide the screen image of the circuit 94 into five regions 116 through 120 to the section 20 with equal area as shown in
As shown in
The chip-region designation section 20 generates definition, as shown in
The chip-region designation section 20 authorizes, after checking, that the total wiring length connected to a path with regions 69, 70, 73, 74, 77, 78 is 2 mm or more and the regions 69, 70, 73, 74, 77, 78 are distinguishably hatched for coverage as shown in
An ending-condition designation section 12 generates ending-conditions shown in
The ending-condition judgment section 19 judges that the coverage rate is 50% and does not satisfy the condition of a range of 70% or more.
Accordingly, the chip-region designation section 20 generates a retrieval condition shown in
The chip-region designation section 20 requests an operator of the apparatus for generating a test vector to designate one of divided regions 69 through 80 based on the screen image 61 of the semiconductor integrated circuit, using a hatched screen image 61 shown in
The operator designates a region 80, which a path is desired to be arranged, by seeing the hatched screen image 61, as shown in
The retrieval-condition designation section 11 recreates a retrieval condition by adding a retrieval condition on which a path arranged in the designated region 80 can be retrieved to the retrieval condition in
The chip-region designation section 20 highlights a path 148, as shown in
It is judged in the ending-condition judgment section 19 whether generation situations of the test vector satisfy the ending condition in
An example 3 of the first embodiment is a case of an apparatus for generating a test vector similar to the apparatus for generating a test vector shown in
The circuit-information setting section 21 generates circuit-information set data in a circuit-information set-data region 152 in a retrieval-condition data region 151 as shown in
The retrieval-priority decision section 22 generates priority decision data in a priority-decision data region 153 of the retrieval-condition data region 151. In the data structure of the priority-decision data, the item data of the circuit-information set data is arranged in the order of the priority and is associated so that the item data can be retrieved, using the priority. Accordingly, a first retrieval condition is that the total number of steps for the path is 20 steps or more and the number of vias is 700 or more. Moreover, a retrieval condition, which is updated after situations where test-vector generation does not satisfy the ending condition, is only that the total number of steps for the path is 20 steps or more. Moreover, the retrieval condition after updating is only that the number of logic elements is 300 gates or more. Furthermore, the retrieval condition after updating is only that the number of vias is 700 or more.
The circuit-information changing section 23 generates the circuit-information changing data in the circuit information changing data region 157 of the retrieval-condition data region 151 of the retrieval condition. The data structure of the circuit-information changing data includes: an item data region 154; a first-changing-condition range data region 155; and a second-changing-condition range data region 156. The item data region 154 includes the same item data as that of the item data region in the circuit-information set data region 152. The first-changing-condition range data region 155 is associated so that the first-changing-condition range data can be retrieved, using the item data. The first-changing-condition range data is relieved, in comparison with the range data of the circuit-information set data. Accordingly, a retrieval condition after further updating is that the total number of steps for the path is 15 steps or more and the number of vias is 500 or more. Similarly, the second changing condition can be applied to the retrieval condition.
As described above, a set of test vectors which have been finally generated are repeatable, not depending on operators, because the retrieval condition is relieved according to a predetermined rule.
An example 4 of the first embodiment is a case of an apparatus for generating a test vector similar to the apparatus for generating a test vector shown in
The chip-region designation section 20 designates a region on the chip, or the entire chip area. The pin-name-list providing section 25 makes or compiles a pin-name list as shown in
The pin-name data region 158 includes, as pin-name data: a cell name; CLTOP/peace/U268/Z representing the pin name of the cell, and the like. The pin-information data region 159 has pin-information data associated so that retrieval can be executed using each pin-name data. The pin-information data is stored in the data region provided for each item. The pin-information data includes, as an item: an X coordinate and a Y coordinate of the pin; a wiring length of wiring connected to the pin; and the number of contacts and vias on a signal transmission line in a cell having the pin.
The circuit-information extraction section 24 extracts circuit information on the retrieval item for the retrieval condition for each pin-name list and generates circuit information for each pin list, based on the pin-name list, and the circuit-information and the retrieval condition.
Based on the pin-name list and the circuit information for each pin list, the path-list generation section 14 generates a path list for a new path. It is not required to make a path list, while reading required circuit information from a vast amount of circuit information recorded in the circuit-information storage section 13. The amount of circuit information for each pin list can be reduced to a much smaller amount of information than that of the circuit information recorded in the circuit-information storage section 13. The amount of information can be reduced further, because the circuit information is stored only for the pin-name list.
An example 5 of the first embodiment is a case of an apparatus for generating a test vector similar to the apparatus for generating a test vector shown in
The circuit-information extraction section 24 generates circuit information for each pin list for the retrieval items of the latest retrieval condition after updating, as shown in
The delimiter-value designation section 195 sets a delimiter value shown in
The highlighted-path selection section 193 generates a path-list for a path satisfying the delimiter value, based on the circuit information for each retrieval item. As shown in
In a fault analysis method of the semiconductor integrated circuit according to an example 1 of the second embodiment, a test execution section 41 executes a delay fault test for the semiconductor integrated circuit at STEP S31, as shown in
The data region 165 includes as data: a serial number of a test such as Test NO. 701; a distinguishable display number of a test vector used for a test such as Pattern Name: Pat1; Pass for the success of a path or Fail for a failed path; delay time measured in a test of Delay Time, such as Delay Time=7.5 nsec; and the like.
Then, a cell-list generation section 43 inputs circuit information on the semiconductor integrated circuit from the circuit-information storage section 33 at STEP S33. At STEP S34, the section 43 generates a cell list shown in
The data structure of the cell list includes a circuit-identifier-name data region 166 for a cell and a cell-name data region 167. In the circuit-identifier-name data region 166 for a cell, the names of circuit-identifiers for cells forming a fail path are arranged in the order of signal transmission of cells. The wiring length of a signal transmission line of cells and the like can be retrieved as circuit information, using the names of circuit-identifiers for cells. In the cell-name data region 167, cell names of cells forming a fail path are arranged in the order of signal transmission of the cells.
At STEP S35, a retrieval-condition designation section 31 generates a retrieval condition, as shown in
At STEP S36, the ending-condition designation section 32 generates an ending condition for fault-cell searching as shown in
At STEP S37, the path-list generation section 34 generates a path list, as shown in
It is judged at STEP S38 whether a new path list for the path is extracted. Since a path list for a new path of path2 is generated, the processing proceeds to STEP S39. At STEP S39, the test-vector generation section 36 generates a test vector for fault-cell searching and vector generation information for each path in the path list for fault-cell searching. According to the vector-generation information, parts of paths 174, 175 for the generated test vector for fault-cell searching have a shared part of a fail path 173, as shown in
It is judged in the ending-condition judgment section 39 at STEP S40 whether the vector generation information in
At STEP S35, the retrieval-condition designation section 31 updates the retrieval condition to a new retrieval condition for fault-cell searching. A new path, which satisfys the updated retrieval condition for fault-cell searching is retrieved to generate a path-list and a test vector for the path for fault-cell searching. When the vector generation information satisfies the ending condition for fault-cell searching, the generated test vector is output to an external memory.
As described above, the test-vector generating method for fault analysis of the delay fault path can be highly automated by generating the test vector of the path for fault-cell searching, based on the cell list of the fail path, the retrieval condition for fault-cell searching, and the ending condition. Furthermore, the quality of the generated test vector for fault-cell searching can be improved to be much more uniform.
A fault analysis apparatus of the semiconductor integrated circuit according to an example 2 of the second embodiment is provided with a pin-coordinate storage section 51, as shown in
The cell-list generation section 43 generates pin-coordinate information, as shown in
In the fault analysis technique of the semiconductor integrated circuit, a test method by which electron beams are irradiated on a chip for analysis of electric potential is simultaneously used in some cases. In the above test method, the pin-coordinate information of the input/output terminal of the cell is indispensable in order to irradiate electron beams on the input/output pin of the cell. According to the above test method, the pin-coordinate information is automatically generated as fail-path information.
Input of a retrieval condition at STEP S35 of the fault analysis method of the semiconductor integrated circuit according to the second embodiment shown in
The circuit-information setting section 21 generates circuit-information set data in a circuit-information set data region 182 of the retrieval-condition data region 181, as shown in
The retrieval-priority decision section 22 generates priority decision data in a priority-decision data region 183 of the retrieval-condition data region 181. In the data structure of the priority-decision data, the item data of the circuit-information set data is arranged in the order of the priority and is associated so that the item data can be retrieved, using the priority. Accordingly, a first retrieval condition is that the number of sharing steps for the path is five steps or more and the wiring length is 1 mm or more. Moreover, an updated retrieval condition is only that a number of sharing steps for the path is five steps or more. Furthermore, the retrieval condition after updating is only that the wiring length is 1 mm or more. Moreover, the retrieval condition after updating is only that the number of contacts is 20 contacts or more.
The circuit-information changing section 23 generates the circuit-information changing data in the circuit information changing data region 187 of the retrieval-condition data region 181 of the retrieval condition. The data structure of the circuit-information changing data includes: an item data region 184; a first-changing-condition range data region 185; and a second-changing-condition range data region 186. The item data region 184 includes the same item data as that of the item data region in the circuit-information set data region 182. The first-changing-condition range data region 185 is associated so that the first-changing-condition range data can be retrieved, using the item data. The first-changing-condition range data is relieved, in comparison with the range data of the circuit-information set data. Accordingly, a retrieval condition after further updating is that the number of sharing steps is three steps or more, the wiring length is 0.5 mm or more, and the number of contacts for the path is 10 contacts or more. Similarly, the second changing condition can be applied to the retrieval condition.
As described above, a set of test vectors which have been finally generated can be repeated, not depending on operators, because the retrieval condition is relieved according to a predetermined rule.
At every updating of the retrieval condition, a test vector for fault-cell searching and vector-generation information for each path in a path list for fault-cell searching are generated. According to the vector-generation information, the paths 174, 175 were retrieved for the fail path 173 under the retrieval condition in the circuit-information set data region 182 and a test vector was generated, as shown in
Thus, a path is retrieved under a suitable condition for fault analysis as a path retrieving method and a test vector is generated. When a temporarily generated test vector is judged to be unsuitable for analysis, a vector best suited for fault analysis will be obtained by addition of a test vector after changing a retrieval condition.
In an example 4 of the second embodiment, a fault analysis apparatus of a semiconductor integrated circuit similar to the fault analysis apparatus of a semiconductor integrated circuit according to the third variant of the second embodiment in
First, a chip-region designation section 50 reads logic circuit information on the semiconductor integrated circuit from a circuit-information storage section 33 and displays an image of a chip 61, as shown in
Data for a success path 164, i.e., without failure, fail data for fail paths 162, 163 are input to the chip-region designation section 50 from a fail-data storage section 42 and images of physical positions of the successful path 164, the fail paths 162, 163 are displayed on the image of the chip. The fail paths 162, 163 and the success path 164 are distinguishably displayed.
By the chip-region designation section 50, covered regions 70, 71, 74, 75, 77 through 79 are configured to have a different display color, assuming that a region is defined to be a covered region when the fail paths 162, 163 pass even a part of the region.
By distinguishably displaying the regions 70, 71, 74, 75, 77 through 79, which are covered by the fail paths 162, 163, on the chip, the chip-region designation section 50 requests an operator to designate and input regions which are desired to be covered with a path for fault-cell searching. As shown in
Based on the new retrieval condition, a path-list generation section 34 retrieves a path 189 for fault-cell searching shown in
Thus, a situation of paths which succeeded in testing and failed paths, and a situation of generation of test-vectors under generation of the test vectors of paths for fault-cell searching can be displayed. The operator can designate a following retrieval condition for path-lists, based on the displayed situations. Thereby, a fault-analysis operation with high accuracy can be provided, using a set of test vectors which are finally generated.
Delay fault testing for a path is executed for each chip. A chip-region designation section 50 summarizes pieces of fail information in the testing for each of the positions at which chips are arranged on a wafer 190, and displays the pieces of fail information with the positions of each chip on the wafer 190, as shown in
In addition to the above applications, fail information can be displayed for each lot or for a plurality of lots. That is, fail paths are collected and counted for each semiconductor integrated circuit to one wafer, each wafer to one lot, or each lot to a plurality of lots. A semiconductor integrated circuit, a wafer, or a lot may be distinguishably displayed, corresponding to the counted number.
Thus, according to testing of a plurality of semiconductor integrated circuits, statistics of measured values of delay time can be collected for paths in the logic circuits which are targets of each test vector. Ratios between the measured values and calculated values used for timing analysis or for simulation at generating test vectors for delay path tests are obtained and each path may be distinguishably displayed, corresponding to the ratio. Thereby, differences between measured values for a real chip and calculated values used for timing analysis and simulation can be easily confirmed.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2002-313172 | Oct 2002 | JP | national |
