Apparatus for performing an extensive diagnostic test in conjunction with a bios test routine

Abstract

A BIOS testing routine is initiated. Control is transferred to a diagnostic routine. The diagnostic routine performs a series of test in which a plurality of components are examined. In one embodiment, a random access/random data memory test is performed on a block of memory. Subsequently, control is transferred to the BIOS testing routine.

Description

APPENDICES

Appendix A, which forms a part of this disclosure, is a list of commonly owned co-pending U.S. patent applications. Each one of the applications listed in Appendix A is hereby incorporated herein in its entirety by reference thereto.

COPYRIGHT RIGHTS

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.

BACKGROUND OF THE INVENTION

I. Field of the Invention

The invention relates to computers. Specifically, the invention relates to computer diagnostic tests.

II. Description of the Related Art

Computers are an integral part of nearly all organizations--from nonprofit charities and small businesses to multinational corporations. Nearly all of these organizations can operate more efficiently if provided an ability to share electronic data files and information among the many people within the organization. In order for an organization to share files, large computers, generally called servers, are used to provide general computing functions to a set of users. As the usage and dependency on such servers increases, the value of reliability in these servers also increases.

For an organization which has come to rely on computers, a computer "crash" may be very detrimental. For instance, a computer crash can cause the loss of productivity between the last back up and the crash. A crash may also cause the corruption of existing data.

A crash may occur when a portion of a computer which is malfunctioning is accessed by a user. For example, if a block of memory has become defective, the defect may not affect operation until data is written to or read back from the memory locations. Therefore, a memory malfunction may be undetected for some period of time if the damaged memory has not been accessed. Other malfunctions may cause a more immediate and pervasive failure. For example, if a fan which is used to maintain a proper temperature within the housing of a computer fails, as the temperature raises in the housing, several components within the computer may fail at nearly the same time, immediately affecting system operation. As the number of users whose time or data may be lost due to a crash increases, the ability to detect a malfunction before a crash occurs becomes even more beneficial.

A typical modern computer runs a series of self tests when power is initially applied to it. One such test is a basic input/output system (BIOS) test. The BIOS is a software interface to the computer hardware. Generally the BIOS is comprised of the system programs for the basic input and output operations such as access to floppy disks, hard drive disks, interfaces and graphical adapters. The tests performed on the BIOS do not extensively test the system components of the computer. Performing a BIOS test does not ensure that no malfunctioning components are present in the system. Therefore, the BIOS test is not a highly effective means of detecting a latent failure and, thereby, preventing a computer crash.

Therefore, it can be seen that there is a need in the industry for a means and method of providing an extensive diagnostic test of a computer.

SUMMARY OF THE INVENTION

The invention is method of and apparatus for performing a diagnostic test in conjunction with a BIOS test routine. A BIOS testing routine is initiated. Control is transferred to a diagnostic routine. The diagnostic routine performs a series of tests in which a plurality of components are examined. For example, in one embodiment the diagnostic routine tests a central processing unit, a peripheral component, an interconnect system, memory and system power. Subsequently, control is transferred to the BIOS testing routine.

In one embodiment, the diagnostic routine tests memory by creating a temporary table of data from stored pseudo random data. Memory is logically divided by determining a set of address blocks which specify a set of continuous address arrays. For ease of implementation, a total number of address blocks in the set of address blocks may be equal to a total number of entries on the temporary table. Data is written from the temporary table into each address block of the set of address blocks in a pseudo random order according to data from the temporary table. Data stored in the memory under test is compared to data written to the memory under test.

In yet another embodiment the diagnostic test may detect a user interrupt during performance of the diagnostic routine. In response to the user interrupt, a manual diagnostic mode is initiated in which user input may be used to perform further diagnostic tests.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, objectives, and advantages of the invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings:

FIG. 1 is a flow chart showing general operation of one embodiment of the invention;

FIGS. 2A and 2B are flow charts showing a specific random access/random data memory diagnostic routine in accordance with one embodiment of the invention;

FIG. 3 is a representative drawing showing the pseudo random data table used in one embodiment of the memory diagnostic routine; and

FIG. 4 is a representative drawing showing the temporary table created for use by one embodiment of the memory diagnostic routine.

DETAILED DESCRIPTION OF THE INVENTION

The invention resides within a general purpose or specific function computer. More specifically, the invention envisions a nonvolatile memory, such as a flash read only memory (ROM), in which is stored a BIOS test routine and an extended diagnostic routine. Under certain conditions, the BIOS test routine is paused and the extended diagnostic routine is run. Upon the completion of the extended diagnostic routine, the BIOS test routine is resumed. The diagnostic routine increases the probability of detecting a computer malfunction before the occurrence of a computer crash.

In one embodiment, the extended diagnostic routine is a separate block of code stored within a common ROM with the BIOS test routine. In another embodiment, the extended diagnostic routine is stored in a hard disk drive. Constructing the extended diagnostic routine within a separate block of code may provide several benefits. For example, existing BIOS test routines are readily available for purchase within the industry. Efficiency in development efforts may be increased if use is made of existing BIOS test routine code. If such use is made, rather than extensively modifying existing BIOS test routine code, a separate newly developed diagnostic routine can be developed. The BIOS test routine code is modified to contain a jump command, call command, procedure call or other commonly known or later developed way to transfer control to the extended diagnostic routine. In addition, standard BIOS test routine structures may not support the ability to define a large block of data which is necessary for the extended memory diagnostic test explained more fully below. A newly developed diagnostic routine may adopt a new memory structure in order to support these tests.

In addition, benefits may also be derived by the inclusion of the BIOS test routine and the diagnostic routine on a single ROM. For example, if the BIOS test routine and the extended diagnostic routine are stored within the same ROM a transfer of control to the diagnostic routine may be made without the use of I/O, thus, increasing the probability of a successful transfer of control.

Several features may be incorporated into the extended diagnostic routine in order to increase the probability of detecting a failure before a crash occurs. One such feature is to provide an option where the diagnostic routine is to be performed repetitively for an extended period time. For example, the extended diagnostic routine may run continuously overnight to detect an intermittent error. In the example below, such operation may be initialized in manual diagnostic mode.

FIG. 1 is a flow chart showing operation of the invention. In block 10, the BIOS test routine begins execution. The basic extended diagnostic routine may take several minutes to execute depending on the size of the computer, the functional units included in the computer and the speed at which the computer operates. Therefore, in the embodiment shown in FIG. 1, the extended diagnostic routine is executed only if the BIOS routine is entered during a "cold boot" of the computer. A cold boot occurs when power is initially applied to the computer or a reset button is pushed. A warm boot occurs in response to a set of key strokes such as depression of the CONTROL-ALT-DELETE keys simultaneously. In alternative embodiments, other conditions may influence the transfer of control to the diagnostic process.

Therefore, within the execution of the BIOS test routine, block 12 determines if the BIOS routine has been entered in response to a cold boot. If a warm boot has occurred, the BIOS continues to operate normally. If a cold boot has occurred, the process flow transfers control to the extended diagnostic routine according to block 14.

Within block 16 the core functions of the diagnostic routine are executed. For example, in one embodiment the diagnostic routine begins by reading to and writing from the central processing unit (CPU). The routine may check several standard CPU registers which record errors. A larger computer may have a plurality of CPU's. The operation of each CPU is tested by the extended diagnostic routine.

In one embodiment, the diagnostic routine also performs a test of the Peripheral Component Interconnect (PCI) cards and buses or other type of local bus components. The testing of these components may be as simple as a series of reads and writes which exercise the functionality of the components and the bus itself. The routine may monitor for error indications detected by the components during this process.

A diagnostic test of the service functions may also be performed. For example, a service processor which controls and/or monitors fan speed, ambient or component temperature and power supply voltage may be consulted to determine whether such functions are operating properly. Additional information concerning control and monitoring of fan speed can be found in co-pending U.S. patent application Ser. No. 08/942,447 filed Oct. 1, 1997, and entitled "Computer Fan Speed Control Device" and in co-pending U.S. patent application Ser. No. 08/942,216, filed Oct. 1, 1997, and entitled "Computer Fan Speed Control System Method."

The diagnostic routine may also run an extensive test of memory. In one embodiment, the memory test is a random access/random data routine which is explained fully below.

After completion of the automatic tests, the program may enter a manual test phase. The manual test phase may be entered, for example, by depression of the CONTROL-"d" or other designated key stroke during the diagnostic routine. Block 18 determines if key strokes indicating a desire to enter manual testing mode have been received. If not, the process flow returns control to the BIOS routine as shown by block 24. If the key strokes have been detected, the flow continues to block 20. Within block 20, more extensive diagnostic tests can be run. The user may see a screen which offers him a number of diagnostic options which may include repetition and/or modification of the tests already performed in block 16 above. In one embodiment, the screen may also provide the user with detailed results of the diagnostic tests which are run. The user may use the information to determine the source of a malfunction. When the user has completed the desired diagnostic functions, he may enter a key stroke to inform the diagnostic routine. In block 22, the process flow monitors for such an indication. If the indication is detected, process flow continues in block 24.

One integral part of a computer is memory. Memory is used to store digital information such as software programs, system data and user data. The memory generally has random access memory (RAM format meaning that data may be written to memory, read back from memory and overwritten with new data. In order for a program to run properly, each bit of the program stored in memory must be accurately written and accessible. In order for user and system data to retain its integrity, each bit of the data stored in memory must be accurately written and accessible. Therefore, the proper operation of computer memory is a major component to the proper operation of a computer.

Modern memory designs strive for maximum density so that as many memory locations as possible may reside in a chip-area that is as small as possible. Efficient designs are achieved through the use of single transistors in conjunction with multiple storage locations. Whenever a single transistor is used in conjunction with two or more storage locations, the probability increases that a write or read to one of the memory locations will affect another one of the memory locations. If the internal memory architecture is known, a custom diagnostic routine can be designed which stresses and monitors for failure modes which are probable given the shared transistor configurations.

Standard memory architectures are repetitious. A basic memory block architecture within a memory unit may be repeated millions of times. The repetitious architectures may lend themselves to patternistic failures. If the internal memory architecture is known, a custom diagnostic routine can be designed which detects patternistic failures.

However, an extensive yet "generic" test of memory is best suited to a general computer environment. In modern systems, the type of memory device used may be unknown or may change during the life of the computer. Therefore, a generic memory test is a more suitable choice than a custom routine. However, a generic patternistic memory diagnostic routine may not detect a patternistic failure because the failure mode pattern may hide within the diagnostic routine pattern. Therefore, benefits may be derived from development of a generic, non-patternistic memory diagnostic routine.

One embodiment of the invention includes a generic memory diagnostic routine. According to a top level view of the invention, a set of data is written into the memory under test. The data is subsequently read out of memory and compared with the value which was originally stored. If the data is the same, the probability that the memory is malfunctioning is low. If the data is not the same, it is highly likely that the memory has malfunctioned.

The memory diagnostic routine incorporated into the invention introduces two pseudo random components in order to avoid being patternistic: pseudo random data and pseudo random access addressing. The data which is stored during the diagnostic process is pseudo random. The order in which the data is written to the memory is also pseudo random. Thus, the process is referred to as a random access/random data process.

In order to introduce pseudo randomness into the routine, embodiments of the invention use a small stored set of pseudo random data. The pseudo random data is a list which has each numerical value between zero and a maximum value stored in a non-sequential order. The stored table is used to create a larger temporary table which is used directly in the random access/random data routine. The larger temporary table is created such that it has each numerical value between zero and a larger maximum value stored in a non-sequential order. Once the larger temporary table has been created, the temporary table data is used to determine the random access and random data of the routine.

During the diagnostic process of some embodiments, a value is written to every memory location under test. Memory may be divided into blocks for testing purposes. The memory may be divided into as many blocks as there are values stored in the larger temporary table. The writing process begins by reading a data value from the temporary table, shifting the data value a number of positions to the left such that the most significant bit of the data is in the most significant bit of the highest valid memory address range. This value becomes the first block address. A series of data, beginning with a first data address of the temporary table is written into a block of memory beginning with the first block address. When the first address block has been filled, a second address block is created in the same manner based on the data stored in a second memory location. The data written into the second address block is different from the data written into the first address block because a new address is chosen from which to start reading the data. In this way, each memory location is written to by the diagnostic process in a pseudo random order with pseudo random data.

Once this process is complete, the data may be read back from memory. Using a similar process to the one described above, the data may be read back from memory and read from the temporary table. The values in each memory location may be compared to the data which was previously written to them. If each value matches, the diagnostic routine may be continued. If any value does not match, the memory has malfunctioned and, in one embodiment, the diagnostic routine may return an error indication to the BIOS routine.

In one embodiment, the process just described is repeated multiple times within the diagnostic routine. Before subsequent memory writes begin, the data in the temporary table is shuffled so that during the next pass, different data is written in a different access pattern to the memory. For example, some data may be swapped with other data. Also, the data may be shifted within the temporary table.

In some cases, a computer may comprise more than one CPU. Each CPU within a computer may have its own bank of memory. The process that is detailed below assumes operation with just one CPU. If more than one CPU is included in a computer, the routine shown below may be executed in parallel on each CPU, meaning that one or more CPU memory banks are tested simultaneously.

FIGS. 2A and 2B are flow charts illustrating another embodiment invention. The process flow of FIGS. 2A and 2B operates based on the use of 256 bytes of pseudo random data stored in a pseudo random table 100 shown in FIG. 3. The pseudo random table 100 comprises each value from 00H to FFH in a non-sequential, preferably pseudo random, order. The pseudo random table 100 is used by the process flow of FIGS. 2A and 2B to create a larger temporary data table 110 as shown in FIG. 4. The temporary table 110 is capable of storing up to 131,072 bytes of data. In some instances, the data is read out of the temporary table 110 in 8 bit words. In other instances, the data is read out of the temporary table 110 in 16 bit words. Therefore, in FIG. 4, the table is shown in a 16 bit word format with individual addresses for each eight bits of stored data.

The creation of the temporary table from the pseudo random table 100 has several benefits. The diagnostic routine described below seeks to avoid patternistic operation in favor of a more random scheme. To aid in reaching that goal, use is made of a random set of data. As the size of the random data available increases, the amount of randomization of the diagnostic process also increases. However, the size of the flash ROM which, in some embodiments, holds both the BIOS code and the diagnostic code, is limited. Therefore, it is not practical to permanently store large amounts of random data for use by the diagnostic routine.

With particular reference to FIGS. 2A and 2B, process flow begins in start block 40. The first functional block 42 sets a series of variables which are used by the flow process. The variable "n" is the address in the pseudo random table 100 of the eight least significant bits of a newly created 16 bit word. The variable "m" is the address in the pseudo random table 100 of the eight most significant bits of a newly created 16 bit word. The variable "MN" is a tracking variable used to step the process flow through the pseudo random table 100. The variable "p" is the address in the temporary table 110 to which the newly created 16 bit word is written. The variable "R" is used to count the number of cycles of the diagnostic process that have been executed. The values of "m" and "M" are set to 255 which sets the write pointer to the last memory location in table 100. All other values are initially set to 0.

In block 44, data is read from the pseudo random table 100 into the temporary table 110. The object of the read process is to fill the temporary table 110 with each possible 16 bit word between 0000H and FFFFH. According to block 44, starting with address p of the temporary table 110, data with the following series of pseudo random table 100 addresses are written into the temporary table 110: m,n, m,n+1, m,n+2, m,n+3. Block 46 determines whether p has reached its final value indicating that the last four memory locations in the temporary table 110 have been filled. If not, the process flow continues to block 48. Block 48 increments "n" by four using modulo 256 addition, decrements "m" by 1 using modulo 256 subtraction, and increments "p" by 8. In block 52, it is determined whether "m" has reached its current terminal value of M indicating that one cycle of the read/write process has been completed. If "m" has not reached its current terminal value, flow continues to block 44 in which another series of read and write operations are executed. In this way, a first pass through the pseudo random table 100 is made while "m" cycles through from FFH to 00H and "n" cycles through four times from 00H to FFH. When "m" returns to its initial value, the response to the inquiry of block 52 is "yes" and flow continues to block 56. In block 56, the tracking variable "M" is reduced by one and "m" is set equal to "M." Again, the read and write operations are executed in block 44 until "m" has again reached its terminal value. In this way, a new set of 256 16-bit words of data are written into the temporary table 110. Process continues in this manner until the temporary table 100 has been filled with 65,536 unique 16 bit words of data.

Once temporary table 110 has been filled with data, the size of the memory to be tested is read in by the diagnostic process. For example, the diagnostic routine may determine the first invalid memory address. The first invalid memory address reflects one memory location higher than the last usable memory address. In this way, the memory address size may be determined. In block 50, the memory size is read in. A variable "B" is used to determine the address block size. In this case, 65,536 16-bit words are available and "B" is set equal to the memory size divided by the number of 16-bit words available, 65,536.

In block 54, several variables are set which are used for the data read/write process. The variable "A" is used to specify the memory location within the temporary table 110 of the data which is used to specify the current block address. The variable "D" is used to specify a memory location within the temporary table 110 of the data which is written into memory.

In block 58, a first address block memory location is set The variable "a" is set equal to the 16 bit word data stored in location "A" multiplied times the address block size "B". The variable "a" is used to step the address range through the current address block. The variable "d" is set equal to "D". The variable "d" is used to step the data pointer through the temporary table 110 to specify data which is stored in memory.

In block 60, data is read from address "d" of the temporary table 110 and written to location address "a" of the memory which is being tested. In block 62, both data pointer "d" and address pointer "a" are incremented so that upon execution of the next read/write operation, the next 8 bit word in the temporary table 110 is written into the next consecutive address location of the address block under test. Block 64 is used to determine whether the end of the current address block has been reached by inquiring whether the next address "a" is a multiple of the address block size and, therefore, the first address of another address block. If the next address "a" is not the first address of another address block, the cyclical read/write process continues back to block 60. If the end of the address block has been reached, the flow continue to block 68.

In block 68, the variable "A" is incremented by 2 in order to point to the next 16 bit word in the temporary table 110. The variable "D" is incremented so that different data is written into the next address block. Block 70 inquires whether the end of the temporary table 110 has been reached which indicates that each memory location under test has been written to. If not, flow continues back to block 58 where new values of "d" and "a" are set for the new address block.

If each memory location has been written to, flow continues to block 72. In block 72, the extended diagnostic routine checks for any error indications which may have occurred during the memory witting process.

In blocks 74, 76, 78, 80, 82, 84 and 86 the process defined by blocks 54, 58, 60, 62, 64, 68, and 70 is essentially repeated. In this case, however, rather than the read/write operation executed in block 60, data is read from both address "d" of the temporary table and address "a" of memory in block 78. Also in block 78, a comparison is made between the data stored at the indicated memory location and the data in the temporary table 110. If an unfavorable comparisons is made, in block 88, the diagnostic process flow is discontinued and an error indication is returned to the BIOS routine. If each of these comparison yields a favorable response, in block 88, process flow continues.

In the embodiment shown in FIGS. 2A and 2B, the basic diagnostic process just described is repeated three times. Therefore, block 90 determines whether the cycle variable "R" is equal to 3. If not, the value of R is incremented in block 92. In block 96, the data in the temporary table 110 is rearranged so that a different sequence of random addresses and a different sequence of random data is written on subsequent diagnostic tests. In block 96 the data in address locations A0 through A2223 are swapped with the data in address locations AA0 through AA2223 where A0 and AA0 are any 16 bit word address value in the temporary table 110. The data in temporary table 110 may also be shifted by a number of 16 bit word addresses. After execution of block 96, the temporary table 110 contains a new pseudo random set of all values from 0000H to FFFFH. The flow continues back to block 54.

After the diagnostic process has been repeated three times, the result of the comparison in block 90 is "yes" and flow continues to block 98. The diagnostic flow is complete and the process continues with the resumption of the BOIS subroutine.

The general principles of the invention have been described with reference to several embodiments in order to illustrate the features of the invention. However, many specific embodiments which do not follow exactly the specific embodiment shown above may fall within the scope of the invention. For example, the size of the pseudo random data table is arbitrary. Likewise, the size of the temporary table is also arbitrary. As noted above, the larger the size of each of these tables, the more randomness which is introduced to the process. The choice of size may be constrained by the operating environment in which the routine is executed.

In the description above, the data written to each address block is different because the address value from which the data values are read is shifted by one at the beginning of each address block. Any number of ways may be used to change the data within the scope of the invention. For example, the data may be read in a reverse order. The address step size may be increased, i.e. the data pointer may be incremented by three address locations rather than one after each memory write. Likewise, the manner in which the data is modified or shuffled at the end of each cycle may be accomplished in a variety of manners consistent with the invention. For example, the data may be modified by reversing the order of the data. The data may be shuffled by swapping consecutive even and odd values within the table. Any manner in which the data is shuffled provides the advantage of changing the random data and random access pattern for the next cycle.

The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive and the scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

APPENDIX A

Incorporation by Reference of Commonly Owned Applications

The following patent applications, commonly owned and filed Oct. 1, 1997, are hereby incorporated herein in their entirety by reference thereto:

______________________________________ ApplicationTitle No. Attorney Docket No.______________________________________"System Architecture for Remote 08/942,160 MNFRAME.002A1Access and Control ofEnvironmental Management""Method of Remote Access and 08/942,215 MNFRAME.002A2Control ofEnvironmental Management""System for Independent Powering 08/942,410 MNFRAME.002A3of Diagnostic Processes ona Computer System""Method of Independent Powering 08/942,320 MNFRAME.002A4of Diagnostic Processes ona Computer System""Diagnostic and Managing 08/942,402 MNFRAME.005A1Distributed Processor System""Method for Managing a 08/942,448 MNFRAME.005A2Distributed Processor System""System for Mapping 08/942,222 MNFRAME.005A3Environmental Resources toMemory for Program Access""Method for Mapping 08/942,214 MNFRAME.005A4Environmental Resources toMemory for Program Access""Hot Add of Devices Software 08/942,309 MNFRAME.006A1Architecture""Method for The Hot Add of 08/942,306 MNFRAME.006A2Devices""Hot Swap of Devices Software 08/942,311 MNFRAME.006A3Architecture""Method for The Hot Swap of 08/942,457 MNFRAME.006A4Devices""Method for the Hot Add of a 08/943,072 MNFRAME.006A5Network Adapter on a SystemIncluding a Dynamically LoadedAdapter Driver""Method for the Hot Add of a 08/942,069 MNFRAME.006A6Mass Storage Adapter on a SystemIncluding a Statically LoadedAdapter Driver""Method for the Hot Add of a 08/942,465 MNFRAME.006A7Network Adapter on a SystemIncluding a StaticallyLoaded Adapter Driver""Method for the Hot Add of a 08/962,963 MNFRAME.006A8Mass Storage Adapter on a SystemIncluding a Dynamically LoadedAdapter Driver""Method for the Hot Swap of a 08/943,078 MNFRAME.006A9Network Adapter on a SystemIncluding a Dynamically LoadedAdapter Driver""Method for the Hot Swap of a 08/942,336 MNFRAME.006A10Mass Storage Adapter on a SystemIncluding a Statically LoadedAdapter Driver""Method for the Hot Swap of a 08/942,459 MNFRAME.006A11Network Adapter on a SystemIncluding a StaticallyLoaded Adapter Driver""Method for the Hot Swap of a 08/942,458 MNFRAME.006A12Mass Storage Adapter on a SystemIncluding a Dynamically LoadedAdapter Driver""Method of Performing an 08/942,463 MNFRAME.008AExtensive Diagnostic Test inConjunction with a BIOSTest Routine""Configuration Management 08/941,268 MNFRAME.010AMethod for Hot Adding andHot Replacing Devices""Configuration Management 08/942,408 MNFRAME.011ASystem for Hot Adding and HotReplacing Devices""Apparatus for Interfacing Buses" 08/942,382 MNFRAME.012A"Method for Interfacing Buses" 08/942,413 MNFRAME.013A"Computer Fan Speed Control 08/942,447 MNFRAME.016ADevices""Computer Fan Speed Control 08/942,216 MNFRAME.017AMethod""System for Powering Up and 08/943,076 MNFRAME.018APowering Down a Server""Method of Powering Up and 08/943,077 MNFRAME.019APowering Down a Server""System for Resetting a Server" 08/942,333 MNFRAME.020A"Method of Resetting a Server" 08/942,405 MNFRAME.021A"System for Displaying Flight 08/942,070 MNFRAME.022ARecorder""Method of Displaying Flight 08/942,068 MNFRAME.023ARecorder""Synchronous Communication 08/943,355 MNFRAME.024AInterface""Synchronous Communication 08/942,004 MNFRAME.025AEmulation""Software System Facilitating the 08/942,317 MNFRAME.026AReplacement or Insertion ofDevices in a Computer System""Method for Facilitating the 08/942,316 MNFRAME.027AReplacement or Insertion ofDevices in a Computer System""System Management Graphical 08/943,357 MNFRAME.028AUser Interface""Display of System Information" 08/942,195 MNFRAME.029A"Data Management System 08/942,129 MNFRAME.030ASupporting Hot PlugOperations on a Computer""Data Management Method 08/942,124 MNFRAME.031ASupporting Hot PlugOperations on a Computer""Alert Configurator and Manager" 08/942,005 MNFRAME.032A"Managing Computer System 08/943,356 MNFRAME.033AAlerts""Computer Fan Speed Control 08/940,301 MNFRAME.034ASystem""Computer Fan Speed Control 08/941,267 MNFRAME.035ASystem Method""Black Box Recorder for 08/942,381 MNFRAME.036AInformation System Events""Method of Recording 08/942,164 MNFRAME.037AInformation System Events""Method for Automatically 08/942,168 MNFRAME.040AReporting a System Failurein a Server""System for Automatically 08/942,384 MNFRAME.041AReporting a System Failurein a Server""Expansion of PCI Bus Loading 08/942,404 MNFRAME.042ACapacity""Method for Expanding PCI 08/942,223 MNFRAME.043ABus Loading Capacity""System for Displaying System 08/942,347 MNFRAME.044AStatus""Method of Displaying System 08/942,071 MNFRAME.045AStatus""Fault Tolerant Computer System" 08/942,194 MNFRAME.046A"Method for Hot Swapping 08/943,044 MNFRAME.047Aof Network Components""A Method for Communicating 08/942,221 MNFRAME.048Aa Software Generated PulseWaveform Between TwoServers in a Network""A System for Communicating 08/942,409 MNFRAME.049Aa Software GeneratedPulse Waveform Between TwoServers in a Network""Method for Clustering Software 08/942,318 MNFRAME.050AApplications""System for Clustering Software 08/942,411 MNFRAME.051AApplications""Method for Automatically 08/942,319 MNFRAME.052AConfiguring a Server afterHot Add of a Device""System for Automatically 08/942,331 MNFRAME.053AConfiguring a Server afterHot Add of a Device""Method of Automatically 08/942,412 MNFRAME.054AConfiguring and Formattinga Computer System andInstalling Software""System for Automatically 08/941,955 MNFRAME.055AConfiguring and Formattinga Computer System andInstalling Software""Determining Slot Numbers in a 08/942,462 MNFRAME.056AComputer""System for Detecting Errors in 08/942,169 MNFRAME.058Aa Network""Method of Detecting Errors in 08/940,302 MNFRAME.059Aa Network""System for Detecting Network 08/942,407 MNFRAME.060AErrors""Method of Detecting Network 08/942,573 MNFRAME.061AErrors"______________________________________

Claims

1. A programmed storage device storing instructions that when executed by a computer perform the method comprising:

initiating a BIOS testing routine;

transferring control to a diagnostic test routine in the normal course of BIOS testing,

performing said diagnostic test routine in which a plurality of components are examined, said diagnostic test routine comprising

creating a temporary table of data from a smaller table of stored pseudo random data, wherein said temporary table is larger than said smaller table of stored pseudo random data,

determining a set of address blocks by logically dividing a memory under test into a set of continuous address arrays, wherein a total number of address blocks in said set of address blocks is equal to a total number of entries on said temporary table,

writing, data from said temporary table into each address block of said set of address blocks in a pseudo random order according to data from said temporary table, and

comparing data stored in said memory under test to data written to said memory under test; and

transferring control to said BIOS testing routine.

2. The program storage device of claim 1 wherein when executed the instructions stored thereon perform said diagnostic test routine by testing a central processing unit, a peripheral component, an interconnect system, memory and system power.

3. The program storage device of claim 1 wherein when executed the instructions stored hereon further perform the method comprising:

detecting a user interrupt during performance of said diagnostic test routine; and

initialing a manual diagnostic mode wherein user input is used to perform further diagnostic tests.

4. The program storage device of claim 1 herein when executed the instructions stored thereon perform said diagnostic test routine if said BIOS testing routine is initiated from a cold boot.

5. The program storage device of claim 1 wherein when executed the instructions stored thereon firer perform the method of:

re-initiating said BIOS testing routine in response to a warm boot; and

bypassing performance of said diagnostic test routine.

6. A computer comprising:

a diagnostic routine stored in read only memory; and

a smaller table of pseudo random data used to create a larder temporary table of pseudo random data, wherein said larder temporary table of pseudo random data comprises more entries tan said smaller table of pseudo random data and wherein said diagnostic routine uses said larger temporary table of pseudo random data to perform a test of memory within said computer.

7. The computer of claim 6 further comprising a BIOS testing routine stored in said read only memory, said BIOS testing routine configured to transfer control to said diagnostic routine.

8. A programmed storage device storing instructions that when executed by a computer perform the method comprising:

creating a temporary table of data from a smaller table of stored pseudo random data, wherein said temporary table is larger than said smaller table of stored pseudo random data

determining a set of address blocks by logically dividing memory under test into a set of continuous address arrays, wherein a total number of address blocks in said set of address blocks is equal to a total number of entries on said temporary table;

writing data from said temporary table into each address block of said set of address blocks in a pseudo random order according to data from said temporary table; and

comparing data stored in said memory under test to data written to said memory under test.

9. The program storage device of claim 8 wherein each entry in said smaller table of stored pseudo random data comprises a first number of digits and wherein said smaller table of stored pseudo random data comprises one entry for each possible value of said first number of digits and wherein said creating of said temporary table further comprises determining a set of temporary table entries having a second number of digits wherein said second number of digits is equal to twice said first number of digits.

10. The program storage device of claim 9 wherein when executed the inductions stored thereon determine said set of temporary value entries by sequentially attaching each entry in said smaller table of stored pseudo random data as a set of most significant bits with each entry in said smaller table of stored pseudo random data as a set of least significant bits such that said temporary table comprises an entry for each possible value of said second number of digits.

11. The program storage device of claim 10 wherein when executed the instructions stored thereon write said data from said temporary table by performing the method comprising:

determining a block address size equal to a total number of memory addresses under test divided by a number of entries in said temporary table;

reading a first entry from said temporary table;

determining a first block address by multiplying said first entry times said block address size; and

writing a series of data from said temporary table to a set of consecutive addresses beginning with said first block address.

12. The program storage device of claim 11 wherein when executed the instructions stored thereon write said data from said temporary table by performing the method further comprising:

reading a second entry from said temporary table;

determining second block address by multiplying said second entry times said block address size; and

writing a second series of data from said temporary table to a set of consecutive addresses beginning with said second block address.