Claims
- 1. An instruction pre-decoding apparatus for a processor executing variable-length instructions fetched from a memory,
- each of said instructions executing in an integral multiple of a time unit referred to as an instruction cycle, said processor executing for a plurality of said instruction cycles, said apparatus pre-decoding at least two of said instructions during one of said instruction cycles,
- said instructions having respectively associated
- lengths,
- addresses, and
- locations in said memory,
- said addresses respectively representing said locations in said memory,
- said instructions including branch instructions and target instructions, said target instructions being respectively associated with said branch instructions,
- said apparatus comprising:
- a branch prediction cache having at least one entry, said at least one entry having fields for one of said target instructions, the length of said one of said target instructions, the length of a first sequential instruction following said one of said target instructions, the address of said one of said target instructions, the address of said first sequential instruction following said one of said target instructions, and the address of a second sequential instruction following said one of said target instructions;
- means for determining the address or a first one of said instructions;
- means for fetching from said memory during one or said instruction cycles at least said first one of said instructions and a second one of said instructions, said second one of said instructions sequentially following said first one of said instructions;
- means for determining the respective lengths of said first and second ones of said instructions;
- means for determining the address of said second one or said instructions;
- means for determining whether either of said first and second ones of said instructions is one of said branch instructions and is thus a detected branch;
- means for checking whether said at least one entry of said branch prediction cache is associated with said detected branch and is thus an associated entry:
- means for substituting, said means for substituting receiving a first group of said fields from said associated entry, said first group of said fields including said one of said target instructions, said length of said one of said target instructions, and said address of said one of said target instructions, said means for substituting providing said first group of said fields as replacements respectively for said detected branch, said detected branch's determined length, and said detected branch's determined address;
- a program counter register;
- a first multiplexer having a first input coupled to an output of said program counter register and a second input for receiving said address of said one of said target instructions from said associated entry of said branch prediction cache;
- first means for adding an output of said first multiplexer and said length of said first one of said instructions from said means for determining the respective lengths;
- a second multiplexer having a first input coupled to an output of said first means for adding and a second input for receiving said address of said first sequential instruction following said one of said target instructions from said associated entry of said branch prediction cache;
- second means for adding an output of said second multiplexer and said length of said second one of said instructions from said means for determining the respective lengths; and
- a third multiplexer having a first input coupled to an output of said second means for adding and a second input for receiving said address of said second sequential instruction following said one of said target instructions from said associated entry of said branch prediction cache, an output of said third multiplexer being coupled to an input of said program counter register.
- 2. The apparatus of claim 1 further comprising:
- a first alignment circuit for aligning said first one of said instructions in response to an input of a first program count information from said output of said first multiplexer; and
- a second alignment circuit for aligning said second one of said instructions in response to an input of a second program count information from said output of said second multiplexer.
- 3. An instruction pre-decoding apparatus for a processor executing variable-length instructions fetched from a memory,
- each of said instructions executing in an integral multiple of a time unit referred to as an instruction cycle said processor executing for a plurality of said instruction cycles, said apparatus pre-decoding at least two of said instructions during one of said instruction cycles,
- said instructions having respectively associated
- lengths,
- addresses, and
- locations in said memory.
- said addresses respectively representing said locations in said memory,
- said instructions including branch instructions and target instructions, said target instructions being respectively associated with said branch instructions,
- said apparatus comprising:
- a branch prediction cache having at least one entry said at least one entry having fields for one of said target instructions, the length of said one of said target instructions, the length of a first sequential instruction following said one of said target instructions, the address of said one of said target instructions, the address of said first sequential instruction following said one of said target instructions, and the address of a second sequential instruction following said one of said target instructions;
- means for determining the address of a first one of said instructions;
- means for fetching from said memory during one of said instruction cycles at least said first one of said instructions and a second one of said instructions, said second one of said instructions sequentially following said first one of said instructions;
- means for determining the respective lengths of said first and second ones of said instructions;
- means for determining the address of said second one of said instructions;
- means for determining whether either of said first and second ones of said instructions is one of said branch instructions and is thus a detected branch;
- means for checking whether said at least one entry of said branch prediction cache is associated with said detected branch and is thus an associated entry;
- means for substituting, said means for substituting receiving a first group of said fields from said associated entry, said first group of said fields including said one of said target instructions, said length of said one of said target instructions, and said address of said one of said target instructions, said means for substituting providing said first group of said fields as replacements respectively for said detected branch, said detected branch's determined length, and said detected branch's determined address;
- a program counter register;
- a first multiplexer having a first input coupled to an output of said program counter register and a second input for receiving said address of said one of said target instructions from said associated entry of said branch prediction cache;
- first means for adding an output of said first multiplexer and said length of said first one of said instructions from said means for determining the respective lengths;
- a second multiplexer having a first input coupled to an output of said first means for adding and a second input for receiving said address of said first sequential instruction following said one of said target instructions from said associated entry of said branch prediction cache;
- second means for adding an output of said second multiplexer and said length of said second one of said instructions from said means for determining the respective lengths;
- a third multiplexer having a first input coupled to an output of said second means for adding and a second input for receiving said address of said second sequential instruction following said one of said target instructions from said associated entry of said branch prediction cache, an output of said third multiplexer being coupled to an input of said program counter register;
- a first alignment circuit for aligning said first one of said instructions in response to an input of a first program count information from said output of said first multiplexer; and
- a second alignment circuit for aligning said second one of said instructions in response to an input of a second program count information from said output of said second multiplexer.
Parent Case Info
This is a continuation of application Ser. No. 07/594,878, filed Oct. 9, 1990, now abandoned.
US Referenced Citations (6)
Continuations (1)
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Number |
Date |
Country |
Parent |
594878 |
Oct 1990 |
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