Claims
- 1. Apparatus for rapidly producing a compressed display of data in a logic analyzer, comprising:a memory for storing logic state samples representing the behavior over time of one or more input signals; a starting memory address register for storing a starting memory address; an ending time stamp comparator for comparing a current time stamp with an ending time stamp to determine the last sample associated with a given pixel, said starting address and said ending timestamp defining a timeslice; hardware circuitry for compressing data descriptive of waveform activity during said timeslice by using said hardware circuitry to compare current sample data with reference data; and further comprising a display screen for displaying waveform data; and a controller for controlling said display screen; said controller loading said starting memory address into said starting memory address register; said controller loading said ending time stamp into said comparator; said hardware circuitry evaluating data read from said acquisition memory beginning at said starting address, incrementing said memory address and reading a current timestamp until said current timestamp value exceeds said ending timestamp value; said controller receiving only said compressed waveform data for display.
- 2. Apparatus according to claim 1, whereini. said waveform data for said pixel is evaluated after a total count of samples for said pixel is determined.
- 3. Apparatus according to claim 1, whereina. said waveform data for said pixel is evaluated during a process in which a total count of samples for said pixel is determined.
Parent Case Info
This application claims benefit of provisional application Ser. No. 60/125,412 filed Mar. 22, 1999.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4608652 |
Yokokawa et al. |
Aug 1986 |
A |
5347540 |
Karrick |
Sep 1994 |
A |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/125412 |
Mar 1999 |
US |